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94bb0c1a DD |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * Copyright (c) 2010 Cavium Networks, Inc. | |
7 | */ | |
8 | ||
9 | #include <linux/jump_label.h> | |
10 | #include <linux/kernel.h> | |
11 | #include <linux/memory.h> | |
12 | #include <linux/mutex.h> | |
13 | #include <linux/types.h> | |
14 | #include <linux/cpu.h> | |
15 | ||
16 | #include <asm/cacheflush.h> | |
17 | #include <asm/inst.h> | |
18 | ||
19 | #ifdef HAVE_JUMP_LABEL | |
20 | ||
935c2dbe MR |
21 | /* |
22 | * Define parameters for the standard MIPS and the microMIPS jump | |
23 | * instruction encoding respectively: | |
24 | * | |
25 | * - the ISA bit of the target, either 0 or 1 respectively, | |
26 | * | |
27 | * - the amount the jump target address is shifted right to fit in the | |
28 | * immediate field of the machine instruction, either 2 or 1, | |
29 | * | |
30 | * - the mask determining the size of the jump region relative to the | |
31 | * delay-slot instruction, either 256MB or 128MB, | |
32 | * | |
33 | * - the jump target alignment, either 4 or 2 bytes. | |
34 | */ | |
35 | #define J_ISA_BIT IS_ENABLED(CONFIG_CPU_MICROMIPS) | |
36 | #define J_RANGE_SHIFT (2 - J_ISA_BIT) | |
37 | #define J_RANGE_MASK ((1ul << (26 + J_RANGE_SHIFT)) - 1) | |
38 | #define J_ALIGN_MASK ((1ul << J_RANGE_SHIFT) - 1) | |
94bb0c1a DD |
39 | |
40 | void arch_jump_label_transform(struct jump_entry *e, | |
41 | enum jump_label_type type) | |
42 | { | |
935c2dbe | 43 | union mips_instruction *insn_p; |
94bb0c1a | 44 | union mips_instruction insn; |
94bb0c1a | 45 | |
935c2dbe MR |
46 | insn_p = (union mips_instruction *)msk_isa16_mode(e->code); |
47 | ||
48 | /* Jump only works within an aligned region its delay slot is in. */ | |
99436f7d | 49 | BUG_ON((e->target & ~J_RANGE_MASK) != ((e->code + 4) & ~J_RANGE_MASK)); |
94bb0c1a | 50 | |
935c2dbe MR |
51 | /* Target must have the right alignment and ISA must be preserved. */ |
52 | BUG_ON((e->target & J_ALIGN_MASK) != J_ISA_BIT); | |
94bb0c1a | 53 | |
76b235c6 | 54 | if (type == JUMP_LABEL_JMP) { |
935c2dbe MR |
55 | insn.j_format.opcode = J_ISA_BIT ? mm_j32_op : j_op; |
56 | insn.j_format.target = e->target >> J_RANGE_SHIFT; | |
94bb0c1a DD |
57 | } else { |
58 | insn.word = 0; /* nop */ | |
59 | } | |
60 | ||
61 | get_online_cpus(); | |
62 | mutex_lock(&text_mutex); | |
935c2dbe MR |
63 | if (IS_ENABLED(CONFIG_CPU_MICROMIPS)) { |
64 | insn_p->halfword[0] = insn.word >> 16; | |
65 | insn_p->halfword[1] = insn.word; | |
66 | } else | |
67 | *insn_p = insn; | |
94bb0c1a DD |
68 | |
69 | flush_icache_range((unsigned long)insn_p, | |
70 | (unsigned long)insn_p + sizeof(*insn_p)); | |
71 | ||
72 | mutex_unlock(&text_mutex); | |
73 | put_online_cpus(); | |
74 | } | |
75 | ||
76 | #endif /* HAVE_JUMP_LABEL */ |