[deliverable/linux.git] / arch / mips / kernel / octeon_switch.S

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 1994, 1995, 1996, 1998, 1999, 2002, 2003 Ralf Baechle
 * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
 * Copyright (C) 1994, 1995, 1996, by Andreas Busse
 * Copyright (C) 1999 Silicon Graphics, Inc.
 * Copyright (C) 2000 MIPS Technologies, Inc.
 *    written by Carsten Langgaard, carstenl@mips.com
 */

#define USE_ALTERNATE_RESUME_IMPL 1
	.set push
	.set arch=mips64r2
#include "r4k_switch.S"
	.set pop
/*
 * task_struct *resume(task_struct *prev, task_struct *next,
 *		       struct thread_info *next_ti, int usedfpu)
 */
	.align	7
	LEAF(resume)
	.set arch=octeon
	mfc0	t1, CP0_STATUS
	LONG_S	t1, THREAD_STATUS(a0)
	cpu_save_nonscratch a0
	LONG_S	ra, THREAD_REG31(a0)

	/*
	 * check if we need to save FPU registers
	 */
	.set push
	.set noreorder
	beqz	a3, 1f
	 PTR_L	t3, TASK_THREAD_INFO(a0)
	.set pop

	/*
	 * clear saved user stack CU1 bit
	 */
	LONG_L	t0, ST_OFF(t3)
	li	t1, ~ST0_CU1
	and	t0, t0, t1
	LONG_S	t0, ST_OFF(t3)

	.set push
	.set arch=mips64r2
	fpu_save_double a0 t0 t1		# c0_status passed in t0
						# clobbers t1
	.set pop
1:

#if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
	/* Check if we need to store CVMSEG state */
	dmfc0	t0, $11,7	/* CvmMemCtl */
	bbit0	t0, 6, 3f	/* Is user access enabled? */

	/* Store the CVMSEG state */
	/* Extract the size of CVMSEG */
	andi	t0, 0x3f
	/* Multiply * (cache line size/sizeof(long)/2) */
	sll	t0, 7-LONGLOG-1
	li	t1, -32768	/* Base address of CVMSEG */
	LONG_ADDI t2, a0, THREAD_CVMSEG /* Where to store CVMSEG to */
	synciobdma
2:
	.set noreorder
	LONG_L	t8, 0(t1)	/* Load from CVMSEG */
	subu	t0, 1		/* Decrement loop var */
	LONG_L	t9, LONGSIZE(t1)/* Load from CVMSEG */
	LONG_ADDU t1, LONGSIZE*2 /* Increment loc in CVMSEG */
	LONG_S	t8, 0(t2)	/* Store CVMSEG to thread storage */
	LONG_ADDU t2, LONGSIZE*2 /* Increment loc in thread storage */
	bnez	t0, 2b		/* Loop until we've copied it all */
	 LONG_S t9, -LONGSIZE(t2)/* Store CVMSEG to thread storage */
	.set reorder

	/* Disable access to CVMSEG */
	dmfc0	t0, $11,7	/* CvmMemCtl */
	xori	t0, t0, 0x40	/* Bit 6 is CVMSEG user enable */
	dmtc0	t0, $11,7	/* CvmMemCtl */
#endif
3:

#if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
	PTR_LA	t8, __stack_chk_guard
	LONG_L	t9, TASK_STACK_CANARY(a1)
	LONG_S	t9, 0(t8)
#endif

	/*
	 * The order of restoring the registers takes care of the race
	 * updating $28, $29 and kernelsp without disabling ints.
	 */
	move	$28, a2
	cpu_restore_nonscratch a1

	PTR_ADDU	t0, $28, _THREAD_SIZE - 32
	set_saved_sp	t0, t1, t2

	mfc0	t1, CP0_STATUS		/* Do we really need this? */
	li	a3, 0xff01
	and	t1, a3
	LONG_L	a2, THREAD_STATUS(a1)
	nor	a3, $0, a3
	and	a2, a3
	or	a2, t1
	mtc0	a2, CP0_STATUS
	move	v0, a0
	jr	ra
	END(resume)

/*
 * void octeon_cop2_save(struct octeon_cop2_state *a0)
 */
	.align	7
	.set push
	.set noreorder
	LEAF(octeon_cop2_save)

	dmfc0	t9, $9,7	/* CvmCtl register. */

	/* Save the COP2 CRC state */
	dmfc2	t0, 0x0201
	dmfc2	t1, 0x0202
	dmfc2	t2, 0x0200
	sd	t0, OCTEON_CP2_CRC_IV(a0)
	sd	t1, OCTEON_CP2_CRC_LENGTH(a0)
	/* Skip next instructions if CvmCtl[NODFA_CP2] set */
	bbit1	t9, 28, 1f
	 sd	t2, OCTEON_CP2_CRC_POLY(a0)

	/* Save the LLM state */
	dmfc2	t0, 0x0402
	dmfc2	t1, 0x040A
	sd	t0, OCTEON_CP2_LLM_DAT(a0)

1:	bbit1	t9, 26, 3f	/* done if CvmCtl[NOCRYPTO] set */
	 sd	t1, OCTEON_CP2_LLM_DAT+8(a0)

	/* Save the COP2 crypto state */
	/* this part is mostly common to both pass 1 and later revisions */
	dmfc2	t0, 0x0084
	dmfc2	t1, 0x0080
	dmfc2	t2, 0x0081
	dmfc2	t3, 0x0082
	sd	t0, OCTEON_CP2_3DES_IV(a0)
	dmfc2	t0, 0x0088
	sd	t1, OCTEON_CP2_3DES_KEY(a0)
	dmfc2	t1, 0x0111			/* only necessary for pass 1 */
	sd	t2, OCTEON_CP2_3DES_KEY+8(a0)
	dmfc2	t2, 0x0102
	sd	t3, OCTEON_CP2_3DES_KEY+16(a0)
	dmfc2	t3, 0x0103
	sd	t0, OCTEON_CP2_3DES_RESULT(a0)
	dmfc2	t0, 0x0104
	sd	t1, OCTEON_CP2_AES_INP0(a0)	/* only necessary for pass 1 */
	dmfc2	t1, 0x0105
	sd	t2, OCTEON_CP2_AES_IV(a0)
	dmfc2	t2, 0x0106
	sd	t3, OCTEON_CP2_AES_IV+8(a0)
	dmfc2	t3, 0x0107
	sd	t0, OCTEON_CP2_AES_KEY(a0)
	dmfc2	t0, 0x0110
	sd	t1, OCTEON_CP2_AES_KEY+8(a0)
	dmfc2	t1, 0x0100
	sd	t2, OCTEON_CP2_AES_KEY+16(a0)
	dmfc2	t2, 0x0101
	sd	t3, OCTEON_CP2_AES_KEY+24(a0)
	mfc0	v0, $15,0	/* Get the processor ID register */
	sd	t0, OCTEON_CP2_AES_KEYLEN(a0)
	li	v1, 0x000d0000	/* This is the processor ID of Octeon Pass1 */
	sd	t1, OCTEON_CP2_AES_RESULT(a0)
	/* Skip to the Pass1 version of the remainder of the COP2 state */
	beq	v0, v1, 2f
	 sd	t2, OCTEON_CP2_AES_RESULT+8(a0)

	/* the non-pass1 state when !CvmCtl[NOCRYPTO] */
	dmfc2	t1, 0x0240
	dmfc2	t2, 0x0241
	ori	v1, v1, 0x9500 /* lowest OCTEON III PrId*/
	dmfc2	t3, 0x0242
	subu	v1, v0, v1 /* prid - lowest OCTEON III PrId */
	dmfc2	t0, 0x0243
	sd	t1, OCTEON_CP2_HSH_DATW(a0)
	dmfc2	t1, 0x0244
	sd	t2, OCTEON_CP2_HSH_DATW+8(a0)
	dmfc2	t2, 0x0245
	sd	t3, OCTEON_CP2_HSH_DATW+16(a0)
	dmfc2	t3, 0x0246
	sd	t0, OCTEON_CP2_HSH_DATW+24(a0)
	dmfc2	t0, 0x0247
	sd	t1, OCTEON_CP2_HSH_DATW+32(a0)
	dmfc2	t1, 0x0248
	sd	t2, OCTEON_CP2_HSH_DATW+40(a0)
	dmfc2	t2, 0x0249
	sd	t3, OCTEON_CP2_HSH_DATW+48(a0)
	dmfc2	t3, 0x024A
	sd	t0, OCTEON_CP2_HSH_DATW+56(a0)
	dmfc2	t0, 0x024B
	sd	t1, OCTEON_CP2_HSH_DATW+64(a0)
	dmfc2	t1, 0x024C
	sd	t2, OCTEON_CP2_HSH_DATW+72(a0)
	dmfc2	t2, 0x024D
	sd	t3, OCTEON_CP2_HSH_DATW+80(a0)
	dmfc2	t3, 0x024E
	sd	t0, OCTEON_CP2_HSH_DATW+88(a0)
	dmfc2	t0, 0x0250
	sd	t1, OCTEON_CP2_HSH_DATW+96(a0)
	dmfc2	t1, 0x0251
	sd	t2, OCTEON_CP2_HSH_DATW+104(a0)
	dmfc2	t2, 0x0252
	sd	t3, OCTEON_CP2_HSH_DATW+112(a0)
	dmfc2	t3, 0x0253
	sd	t0, OCTEON_CP2_HSH_IVW(a0)
	dmfc2	t0, 0x0254
	sd	t1, OCTEON_CP2_HSH_IVW+8(a0)
	dmfc2	t1, 0x0255
	sd	t2, OCTEON_CP2_HSH_IVW+16(a0)
	dmfc2	t2, 0x0256
	sd	t3, OCTEON_CP2_HSH_IVW+24(a0)
	dmfc2	t3, 0x0257
	sd	t0, OCTEON_CP2_HSH_IVW+32(a0)
	dmfc2	t0, 0x0258
	sd	t1, OCTEON_CP2_HSH_IVW+40(a0)
	dmfc2	t1, 0x0259
	sd	t2, OCTEON_CP2_HSH_IVW+48(a0)
	dmfc2	t2, 0x025E
	sd	t3, OCTEON_CP2_HSH_IVW+56(a0)
	dmfc2	t3, 0x025A
	sd	t0, OCTEON_CP2_GFM_MULT(a0)
	dmfc2	t0, 0x025B
	sd	t1, OCTEON_CP2_GFM_MULT+8(a0)
	sd	t2, OCTEON_CP2_GFM_POLY(a0)
	sd	t3, OCTEON_CP2_GFM_RESULT(a0)
	bltz	v1, 4f
	 sd	t0, OCTEON_CP2_GFM_RESULT+8(a0)
	/* OCTEON III things*/
	dmfc2	t0, 0x024F
	dmfc2	t1, 0x0050
	sd	t0, OCTEON_CP2_SHA3(a0)
	sd	t1, OCTEON_CP2_SHA3+8(a0)
4:
	jr	ra
	 nop

2:	/* pass 1 special stuff when !CvmCtl[NOCRYPTO] */
	dmfc2	t3, 0x0040
	dmfc2	t0, 0x0041
	dmfc2	t1, 0x0042
	dmfc2	t2, 0x0043
	sd	t3, OCTEON_CP2_HSH_DATW(a0)
	dmfc2	t3, 0x0044
	sd	t0, OCTEON_CP2_HSH_DATW+8(a0)
	dmfc2	t0, 0x0045
	sd	t1, OCTEON_CP2_HSH_DATW+16(a0)
	dmfc2	t1, 0x0046
	sd	t2, OCTEON_CP2_HSH_DATW+24(a0)
	dmfc2	t2, 0x0048
	sd	t3, OCTEON_CP2_HSH_DATW+32(a0)
	dmfc2	t3, 0x0049
	sd	t0, OCTEON_CP2_HSH_DATW+40(a0)
	dmfc2	t0, 0x004A
	sd	t1, OCTEON_CP2_HSH_DATW+48(a0)
	sd	t2, OCTEON_CP2_HSH_IVW(a0)
	sd	t3, OCTEON_CP2_HSH_IVW+8(a0)
	sd	t0, OCTEON_CP2_HSH_IVW+16(a0)

3:	/* pass 1 or CvmCtl[NOCRYPTO] set */
	jr	ra
	 nop
	END(octeon_cop2_save)
	.set pop

/*
 * void octeon_cop2_restore(struct octeon_cop2_state *a0)
 */
	.align	7
	.set push
	.set noreorder
	LEAF(octeon_cop2_restore)
	/* First cache line was prefetched before the call */
	pref	4,  128(a0)
	dmfc0	t9, $9,7	/* CvmCtl register. */

	pref	4,  256(a0)
	ld	t0, OCTEON_CP2_CRC_IV(a0)
	pref	4,  384(a0)
	ld	t1, OCTEON_CP2_CRC_LENGTH(a0)
	ld	t2, OCTEON_CP2_CRC_POLY(a0)

	/* Restore the COP2 CRC state */
	dmtc2	t0, 0x0201
	dmtc2	t1, 0x1202
	bbit1	t9, 28, 2f	/* Skip LLM if CvmCtl[NODFA_CP2] is set */
	 dmtc2	t2, 0x4200

	/* Restore the LLM state */
	ld	t0, OCTEON_CP2_LLM_DAT(a0)
	ld	t1, OCTEON_CP2_LLM_DAT+8(a0)
	dmtc2	t0, 0x0402
	dmtc2	t1, 0x040A

2:
	bbit1	t9, 26, done_restore	/* done if CvmCtl[NOCRYPTO] set */
	 nop

	/* Restore the COP2 crypto state common to pass 1 and pass 2 */
	ld	t0, OCTEON_CP2_3DES_IV(a0)
	ld	t1, OCTEON_CP2_3DES_KEY(a0)
	ld	t2, OCTEON_CP2_3DES_KEY+8(a0)
	dmtc2	t0, 0x0084
	ld	t0, OCTEON_CP2_3DES_KEY+16(a0)
	dmtc2	t1, 0x0080
	ld	t1, OCTEON_CP2_3DES_RESULT(a0)
	dmtc2	t2, 0x0081
	ld	t2, OCTEON_CP2_AES_INP0(a0) /* only really needed for pass 1 */
	dmtc2	t0, 0x0082
	ld	t0, OCTEON_CP2_AES_IV(a0)
	dmtc2	t1, 0x0098
	ld	t1, OCTEON_CP2_AES_IV+8(a0)
	dmtc2	t2, 0x010A		    /* only really needed for pass 1 */
	ld	t2, OCTEON_CP2_AES_KEY(a0)
	dmtc2	t0, 0x0102
	ld	t0, OCTEON_CP2_AES_KEY+8(a0)
	dmtc2	t1, 0x0103
	ld	t1, OCTEON_CP2_AES_KEY+16(a0)
	dmtc2	t2, 0x0104
	ld	t2, OCTEON_CP2_AES_KEY+24(a0)
	dmtc2	t0, 0x0105
	ld	t0, OCTEON_CP2_AES_KEYLEN(a0)
	dmtc2	t1, 0x0106
	ld	t1, OCTEON_CP2_AES_RESULT(a0)
	dmtc2	t2, 0x0107
	ld	t2, OCTEON_CP2_AES_RESULT+8(a0)
	mfc0	t3, $15,0	/* Get the processor ID register */
	dmtc2	t0, 0x0110
	li	v0, 0x000d0000	/* This is the processor ID of Octeon Pass1 */
	dmtc2	t1, 0x0100
	bne	v0, t3, 3f	/* Skip the next stuff for non-pass1 */
	 dmtc2	t2, 0x0101

	/* this code is specific for pass 1 */
	ld	t0, OCTEON_CP2_HSH_DATW(a0)
	ld	t1, OCTEON_CP2_HSH_DATW+8(a0)
	ld	t2, OCTEON_CP2_HSH_DATW+16(a0)
	dmtc2	t0, 0x0040
	ld	t0, OCTEON_CP2_HSH_DATW+24(a0)
	dmtc2	t1, 0x0041
	ld	t1, OCTEON_CP2_HSH_DATW+32(a0)
	dmtc2	t2, 0x0042
	ld	t2, OCTEON_CP2_HSH_DATW+40(a0)
	dmtc2	t0, 0x0043
	ld	t0, OCTEON_CP2_HSH_DATW+48(a0)
	dmtc2	t1, 0x0044
	ld	t1, OCTEON_CP2_HSH_IVW(a0)
	dmtc2	t2, 0x0045
	ld	t2, OCTEON_CP2_HSH_IVW+8(a0)
	dmtc2	t0, 0x0046
	ld	t0, OCTEON_CP2_HSH_IVW+16(a0)
	dmtc2	t1, 0x0048
	dmtc2	t2, 0x0049
	b done_restore	 /* unconditional branch */
	 dmtc2	t0, 0x004A

3:	/* this is post-pass1 code */
	ld	t2, OCTEON_CP2_HSH_DATW(a0)
	ori	v0, v0, 0x9500 /* lowest OCTEON III PrId*/
	ld	t0, OCTEON_CP2_HSH_DATW+8(a0)
	ld	t1, OCTEON_CP2_HSH_DATW+16(a0)
	dmtc2	t2, 0x0240
	ld	t2, OCTEON_CP2_HSH_DATW+24(a0)
	dmtc2	t0, 0x0241
	ld	t0, OCTEON_CP2_HSH_DATW+32(a0)
	dmtc2	t1, 0x0242
	ld	t1, OCTEON_CP2_HSH_DATW+40(a0)
	dmtc2	t2, 0x0243
	ld	t2, OCTEON_CP2_HSH_DATW+48(a0)
	dmtc2	t0, 0x0244
	ld	t0, OCTEON_CP2_HSH_DATW+56(a0)
	dmtc2	t1, 0x0245
	ld	t1, OCTEON_CP2_HSH_DATW+64(a0)
	dmtc2	t2, 0x0246
	ld	t2, OCTEON_CP2_HSH_DATW+72(a0)
	dmtc2	t0, 0x0247
	ld	t0, OCTEON_CP2_HSH_DATW+80(a0)
	dmtc2	t1, 0x0248
	ld	t1, OCTEON_CP2_HSH_DATW+88(a0)
	dmtc2	t2, 0x0249
	ld	t2, OCTEON_CP2_HSH_DATW+96(a0)
	dmtc2	t0, 0x024A
	ld	t0, OCTEON_CP2_HSH_DATW+104(a0)
	dmtc2	t1, 0x024B
	ld	t1, OCTEON_CP2_HSH_DATW+112(a0)
	dmtc2	t2, 0x024C
	ld	t2, OCTEON_CP2_HSH_IVW(a0)
	dmtc2	t0, 0x024D
	ld	t0, OCTEON_CP2_HSH_IVW+8(a0)
	dmtc2	t1, 0x024E
	ld	t1, OCTEON_CP2_HSH_IVW+16(a0)
	dmtc2	t2, 0x0250
	ld	t2, OCTEON_CP2_HSH_IVW+24(a0)
	dmtc2	t0, 0x0251
	ld	t0, OCTEON_CP2_HSH_IVW+32(a0)
	dmtc2	t1, 0x0252
	ld	t1, OCTEON_CP2_HSH_IVW+40(a0)
	dmtc2	t2, 0x0253
	ld	t2, OCTEON_CP2_HSH_IVW+48(a0)
	dmtc2	t0, 0x0254
	ld	t0, OCTEON_CP2_HSH_IVW+56(a0)
	dmtc2	t1, 0x0255
	ld	t1, OCTEON_CP2_GFM_MULT(a0)
	dmtc2	t2, 0x0256
	ld	t2, OCTEON_CP2_GFM_MULT+8(a0)
	dmtc2	t0, 0x0257
	ld	t0, OCTEON_CP2_GFM_POLY(a0)
	dmtc2	t1, 0x0258
	ld	t1, OCTEON_CP2_GFM_RESULT(a0)
	dmtc2	t2, 0x0259
	ld	t2, OCTEON_CP2_GFM_RESULT+8(a0)
	dmtc2	t0, 0x025E
	subu	v0, t3, v0 /* prid - lowest OCTEON III PrId */
	dmtc2	t1, 0x025A
	bltz	v0, done_restore
	 dmtc2	t2, 0x025B
	/* OCTEON III things*/
	ld	t0, OCTEON_CP2_SHA3(a0)
	ld	t1, OCTEON_CP2_SHA3+8(a0)
	dmtc2	t0, 0x0051
	dmtc2	t1, 0x0050
done_restore:
	jr	ra
	 nop
	END(octeon_cop2_restore)
	.set pop

/*
 * void octeon_mult_save()
 * sp is assumed to point to a struct pt_regs
 *
 * NOTE: This is called in SAVE_TEMP in stackframe.h. It can
 *       safely modify v1,k0, k1,$10-$15, and $24.  It will
 *	 be overwritten with a processor specific version of the code.
 */
	.p2align 7
	.set push
	.set noreorder
	LEAF(octeon_mult_save)
	jr	ra
	 nop
	.space 30 * 4, 0
octeon_mult_save_end:
	EXPORT(octeon_mult_save_end)
	END(octeon_mult_save)

	LEAF(octeon_mult_save2)
	/* Save the multiplier state OCTEON II and earlier*/
	v3mulu	k0, $0, $0
	v3mulu	k1, $0, $0
	sd	k0, PT_MTP(sp)	      /* PT_MTP	   has P0 */
	v3mulu	k0, $0, $0
	sd	k1, PT_MTP+8(sp)      /* PT_MTP+8  has P1 */
	ori	k1, $0, 1
	v3mulu	k1, k1, $0
	sd	k0, PT_MTP+16(sp)     /* PT_MTP+16 has P2 */
	v3mulu	k0, $0, $0
	sd	k1, PT_MPL(sp)	      /* PT_MPL	   has MPL0 */
	v3mulu	k1, $0, $0
	sd	k0, PT_MPL+8(sp)      /* PT_MPL+8  has MPL1 */
	jr	ra
	 sd	k1, PT_MPL+16(sp)     /* PT_MPL+16 has MPL2 */
octeon_mult_save2_end:
	EXPORT(octeon_mult_save2_end)
	END(octeon_mult_save2)

	LEAF(octeon_mult_save3)
	/* Save the multiplier state OCTEON III */
	v3mulu	$10, $0, $0		/* read P0 */
	v3mulu	$11, $0, $0		/* read P1 */
	v3mulu	$12, $0, $0		/* read P2 */
	sd	$10, PT_MTP+(0*8)(sp)	/* store P0 */
	v3mulu	$10, $0, $0		/* read P3 */
	sd	$11, PT_MTP+(1*8)(sp)	/*  store P1 */
	v3mulu	$11, $0, $0		/* read P4 */
	sd	$12, PT_MTP+(2*8)(sp)	/* store P2 */
	ori	$13, $0, 1
	v3mulu	$12, $0, $0		/* read P5 */
	sd	$10, PT_MTP+(3*8)(sp)	/* store P3 */
	v3mulu	$13, $13, $0		/* P4-P0 = MPL5-MPL1, $13 = MPL0 */
	sd	$11, PT_MTP+(4*8)(sp)	/* store P4 */
	v3mulu	$10, $0, $0		/* read MPL1 */
	sd	$12, PT_MTP+(5*8)(sp)	/* store P5 */
	v3mulu	$11, $0, $0		/* read MPL2 */
	sd	$13, PT_MPL+(0*8)(sp)	/* store MPL0 */
	v3mulu	$12, $0, $0		/* read MPL3 */
	sd	$10, PT_MPL+(1*8)(sp)	/* store MPL1 */
	v3mulu	$10, $0, $0		/* read MPL4 */
	sd	$11, PT_MPL+(2*8)(sp)	/* store MPL2 */
	v3mulu	$11, $0, $0		/* read MPL5 */
	sd	$12, PT_MPL+(3*8)(sp)	/* store MPL3 */
	sd	$10, PT_MPL+(4*8)(sp)	/* store MPL4 */
	jr	ra
	 sd	$11, PT_MPL+(5*8)(sp)	/* store MPL5 */
octeon_mult_save3_end:
	EXPORT(octeon_mult_save3_end)
	END(octeon_mult_save3)
	.set pop

/*
 * void octeon_mult_restore()
 * sp is assumed to point to a struct pt_regs
 *
 * NOTE: This is called in RESTORE_TEMP in stackframe.h.
 */
	.p2align 7
	.set push
	.set noreorder
	LEAF(octeon_mult_restore)
	jr	ra
	 nop
	.space 30 * 4, 0
octeon_mult_restore_end:
	EXPORT(octeon_mult_restore_end)
	END(octeon_mult_restore)

	LEAF(octeon_mult_restore2)
	ld	v0, PT_MPL(sp)        	/* MPL0 */
	ld	v1, PT_MPL+8(sp)      	/* MPL1 */
	ld	k0, PT_MPL+16(sp)     	/* MPL2 */
	/* Restore the multiplier state */
	ld	k1, PT_MTP+16(sp)     	/* P2 */
	mtm0	v0			/* MPL0 */
	ld	v0, PT_MTP+8(sp)	/* P1 */
	mtm1	v1			/* MPL1 */
	ld	v1, PT_MTP(sp)   	/* P0 */
	mtm2	k0			/* MPL2 */
	mtp2	k1			/* P2 */
	mtp1	v0			/* P1 */
	jr	ra
	 mtp0	v1			/* P0 */
octeon_mult_restore2_end:
	EXPORT(octeon_mult_restore2_end)
	END(octeon_mult_restore2)

	LEAF(octeon_mult_restore3)
	ld	$12, PT_MPL+(0*8)(sp)	/* read MPL0 */
	ld	$13, PT_MPL+(3*8)(sp)	/* read MPL3 */
	ld	$10, PT_MPL+(1*8)(sp)	/* read MPL1 */
	ld	$11, PT_MPL+(4*8)(sp)	/* read MPL4 */
	.word	0x718d0008
	/* mtm0	$12, $13		   restore MPL0 and MPL3 */
	ld	$12, PT_MPL+(2*8)(sp)	/* read MPL2 */
	.word	0x714b000c
	/* mtm1	$10, $11		   restore MPL1 and MPL4 */
	ld	$13, PT_MPL+(5*8)(sp)	/* read MPL5 */
	ld	$10, PT_MTP+(0*8)(sp)	/* read P0 */
	ld	$11, PT_MTP+(3*8)(sp)	/* read P3 */
	.word	0x718d000d
	/* mtm2	$12, $13		   restore MPL2 and MPL5 */
	ld	$12, PT_MTP+(1*8)(sp)	/* read P1 */
	.word	0x714b0009
	/* mtp0	$10, $11		   restore P0 and P3 */
	ld	$13, PT_MTP+(4*8)(sp)	/* read P4 */
	ld	$10, PT_MTP+(2*8)(sp)	/* read P2 */
	ld	$11, PT_MTP+(5*8)(sp)	/* read P5 */
	.word	0x718d000a
	/* mtp1	$12, $13		   restore P1 and P4 */
	jr	ra
	.word	0x714b000b
	/* mtp2	$10, $11		   restore P2 and P5 */

octeon_mult_restore3_end:
	EXPORT(octeon_mult_restore3_end)
	END(octeon_mult_restore3)
	.set pop
Commit	Line	Data
5b3b1688 DD	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* Copyright (C) 1994, 1995, 1996, 1998, 1999, 2002, 2003 Ralf Baechle
79add627	7	* Copyright (C) 1996 David S. Miller (davem@davemloft.net)
5b3b1688 DD	8	* Copyright (C) 1994, 1995, 1996, by Andreas Busse
	9	* Copyright (C) 1999 Silicon Graphics, Inc.
	10	* Copyright (C) 2000 MIPS Technologies, Inc.
	11	* written by Carsten Langgaard, carstenl@mips.com
	12	*/
5b3b1688	13
a36d8225 DD	14	#define USE_ALTERNATE_RESUME_IMPL 1
	15	.set push
	16	.set arch=mips64r2
	17	#include "r4k_switch.S"
	18	.set pop
5b3b1688 DD	19	/*
5b3b1688 DD	20	* task_struct resume(task_struct prev, task_struct *next,
70342287	21	* struct thread_info *next_ti, int usedfpu)
5b3b1688 DD	22	*/
	23	.align 7
	24	LEAF(resume)
	25	.set arch=octeon
5b3b1688 DD	26	mfc0 t1, CP0_STATUS
	27	LONG_S t1, THREAD_STATUS(a0)
	28	cpu_save_nonscratch a0
	29	LONG_S ra, THREAD_REG31(a0)
	30
a36d8225 DD	31	/*
	32	* check if we need to save FPU registers
	33	*/
d6e41525 DD	34	.set push
	35	.set noreorder
	36	beqz a3, 1f
	37	PTR_L t3, TASK_THREAD_INFO(a0)
	38	.set pop
a36d8225 DD	39
	40	/*
	41	* clear saved user stack CU1 bit
	42	*/
	43	LONG_L t0, ST_OFF(t3)
	44	li t1, ~ST0_CU1
	45	and t0, t0, t1
	46	LONG_S t0, ST_OFF(t3)
	47
	48	.set push
	49	.set arch=mips64r2
	50	fpu_save_double a0 t0 t1 # c0_status passed in t0
	51	# clobbers t1
	52	.set pop
	53	1:
	54
5b3b1688 DD	55	#if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
5b3b1688 DD	56	/* Check if we need to store CVMSEG state */
2d98cae6	57	dmfc0 t0, $11,7 /* CvmMemCtl */
5b3b1688 DD	58	bbit0 t0, 6, 3f /* Is user access enabled? */
	59
	60	/* Store the CVMSEG state */
	61	/* Extract the size of CVMSEG */
	62	andi t0, 0x3f
	63	/* Multiply * (cache line size/sizeof(long)/2) */
	64	sll t0, 7-LONGLOG-1
70342287 RB	65	li t1, -32768 /* Base address of CVMSEG */
70342287 RB	66	LONG_ADDI t2, a0, THREAD_CVMSEG /* Where to store CVMSEG to */
5b3b1688 DD	67	synciobdma
	68	2:
	69	.set noreorder
	70	LONG_L t8, 0(t1) /* Load from CVMSEG */
	71	subu t0, 1 /* Decrement loop var */
	72	LONG_L t9, LONGSIZE(t1)/* Load from CVMSEG */
	73	LONG_ADDU t1, LONGSIZE2 / Increment loc in CVMSEG */
	74	LONG_S t8, 0(t2) /* Store CVMSEG to thread storage */
	75	LONG_ADDU t2, LONGSIZE2 / Increment loc in thread storage */
	76	bnez t0, 2b /* Loop until we've copied it all */
70342287	77	LONG_S t9, -LONGSIZE(t2)/* Store CVMSEG to thread storage */
5b3b1688 DD	78	.set reorder
	79
	80	/* Disable access to CVMSEG */
2d98cae6	81	dmfc0 t0, $11,7 /* CvmMemCtl */
5b3b1688	82	xori t0, t0, 0x40 /* Bit 6 is CVMSEG user enable */
2d98cae6	83	dmtc0 t0, $11,7 /* CvmMemCtl */
5b3b1688 DD	84	#endif
5b3b1688 DD	85	3:
1400eb65 GF	86
1400eb65 GF	87	#if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
8b3c569a	88	PTR_LA t8, __stack_chk_guard
1400eb65 GF	89	LONG_L t9, TASK_STACK_CANARY(a1)
	90	LONG_S t9, 0(t8)
	91	#endif
	92
5b3b1688 DD	93	/*
	94	* The order of restoring the registers takes care of the race
	95	* updating $28, $29 and kernelsp without disabling ints.
	96	*/
	97	move $28, a2
	98	cpu_restore_nonscratch a1
	99
a36d8225	100	PTR_ADDU t0, $28, _THREAD_SIZE - 32
5b3b1688 DD	101	set_saved_sp t0, t1, t2
	102
	103	mfc0 t1, CP0_STATUS /* Do we really need this? */
	104	li a3, 0xff01
	105	and t1, a3
	106	LONG_L a2, THREAD_STATUS(a1)
	107	nor a3, $0, a3
	108	and a2, a3
	109	or a2, t1
	110	mtc0 a2, CP0_STATUS
	111	move v0, a0
	112	jr ra
	113	END(resume)
	114
	115	/*
	116	* void octeon_cop2_save(struct octeon_cop2_state *a0)
	117	*/
	118	.align 7
6b3a287e DD	119	.set push
6b3a287e DD	120	.set noreorder
5b3b1688 DD	121	LEAF(octeon_cop2_save)
	122
	123	dmfc0 t9, $9,7 /* CvmCtl register. */
	124
70342287	125	/* Save the COP2 CRC state */
5b3b1688 DD	126	dmfc2 t0, 0x0201
	127	dmfc2 t1, 0x0202
	128	dmfc2 t2, 0x0200
	129	sd t0, OCTEON_CP2_CRC_IV(a0)
	130	sd t1, OCTEON_CP2_CRC_LENGTH(a0)
5b3b1688 DD	131	/* Skip next instructions if CvmCtl[NODFA_CP2] set */
5b3b1688 DD	132	bbit1 t9, 28, 1f
6b3a287e	133	sd t2, OCTEON_CP2_CRC_POLY(a0)
5b3b1688 DD	134
	135	/* Save the LLM state */
	136	dmfc2 t0, 0x0402
	137	dmfc2 t1, 0x040A
	138	sd t0, OCTEON_CP2_LLM_DAT(a0)
5b3b1688	139
70342287	140	1: bbit1 t9, 26, 3f /* done if CvmCtl[NOCRYPTO] set */
6b3a287e	141	sd t1, OCTEON_CP2_LLM_DAT+8(a0)
5b3b1688 DD	142
5b3b1688 DD	143	/* Save the COP2 crypto state */
70342287 RB	144	/* this part is mostly common to both pass 1 and later revisions */
	145	dmfc2 t0, 0x0084
	146	dmfc2 t1, 0x0080
	147	dmfc2 t2, 0x0081
	148	dmfc2 t3, 0x0082
5b3b1688	149	sd t0, OCTEON_CP2_3DES_IV(a0)
70342287	150	dmfc2 t0, 0x0088
5b3b1688	151	sd t1, OCTEON_CP2_3DES_KEY(a0)
70342287	152	dmfc2 t1, 0x0111 /* only necessary for pass 1 */
5b3b1688	153	sd t2, OCTEON_CP2_3DES_KEY+8(a0)
70342287	154	dmfc2 t2, 0x0102
5b3b1688	155	sd t3, OCTEON_CP2_3DES_KEY+16(a0)
70342287	156	dmfc2 t3, 0x0103
5b3b1688	157	sd t0, OCTEON_CP2_3DES_RESULT(a0)
70342287 RB	158	dmfc2 t0, 0x0104
	159	sd t1, OCTEON_CP2_AES_INP0(a0) /* only necessary for pass 1 */
	160	dmfc2 t1, 0x0105
5b3b1688 DD	161	sd t2, OCTEON_CP2_AES_IV(a0)
	162	dmfc2 t2, 0x0106
	163	sd t3, OCTEON_CP2_AES_IV+8(a0)
70342287	164	dmfc2 t3, 0x0107
5b3b1688 DD	165	sd t0, OCTEON_CP2_AES_KEY(a0)
	166	dmfc2 t0, 0x0110
	167	sd t1, OCTEON_CP2_AES_KEY+8(a0)
	168	dmfc2 t1, 0x0100
	169	sd t2, OCTEON_CP2_AES_KEY+16(a0)
	170	dmfc2 t2, 0x0101
	171	sd t3, OCTEON_CP2_AES_KEY+24(a0)
6b3a287e	172	mfc0 v0, $15,0 /* Get the processor ID register */
5b3b1688	173	sd t0, OCTEON_CP2_AES_KEYLEN(a0)
6b3a287e	174	li v1, 0x000d0000 /* This is the processor ID of Octeon Pass1 */
5b3b1688	175	sd t1, OCTEON_CP2_AES_RESULT(a0)
5b3b1688	176	/* Skip to the Pass1 version of the remainder of the COP2 state */
6b3a287e DD	177	beq v0, v1, 2f
6b3a287e DD	178	sd t2, OCTEON_CP2_AES_RESULT+8(a0)
5b3b1688	179
70342287	180	/* the non-pass1 state when !CvmCtl[NOCRYPTO] */
5b3b1688 DD	181	dmfc2 t1, 0x0240
5b3b1688 DD	182	dmfc2 t2, 0x0241
6b3a287e	183	ori v1, v1, 0x9500 /* lowest OCTEON III PrId*/
5b3b1688	184	dmfc2 t3, 0x0242
6b3a287e	185	subu v1, v0, v1 /* prid - lowest OCTEON III PrId */
5b3b1688 DD	186	dmfc2 t0, 0x0243
	187	sd t1, OCTEON_CP2_HSH_DATW(a0)
	188	dmfc2 t1, 0x0244
	189	sd t2, OCTEON_CP2_HSH_DATW+8(a0)
	190	dmfc2 t2, 0x0245
	191	sd t3, OCTEON_CP2_HSH_DATW+16(a0)
	192	dmfc2 t3, 0x0246
	193	sd t0, OCTEON_CP2_HSH_DATW+24(a0)
	194	dmfc2 t0, 0x0247
	195	sd t1, OCTEON_CP2_HSH_DATW+32(a0)
	196	dmfc2 t1, 0x0248
	197	sd t2, OCTEON_CP2_HSH_DATW+40(a0)
	198	dmfc2 t2, 0x0249
	199	sd t3, OCTEON_CP2_HSH_DATW+48(a0)
	200	dmfc2 t3, 0x024A
	201	sd t0, OCTEON_CP2_HSH_DATW+56(a0)
	202	dmfc2 t0, 0x024B
	203	sd t1, OCTEON_CP2_HSH_DATW+64(a0)
	204	dmfc2 t1, 0x024C
	205	sd t2, OCTEON_CP2_HSH_DATW+72(a0)
	206	dmfc2 t2, 0x024D
	207	sd t3, OCTEON_CP2_HSH_DATW+80(a0)
70342287	208	dmfc2 t3, 0x024E
5b3b1688 DD	209	sd t0, OCTEON_CP2_HSH_DATW+88(a0)
	210	dmfc2 t0, 0x0250
	211	sd t1, OCTEON_CP2_HSH_DATW+96(a0)
	212	dmfc2 t1, 0x0251
	213	sd t2, OCTEON_CP2_HSH_DATW+104(a0)
	214	dmfc2 t2, 0x0252
	215	sd t3, OCTEON_CP2_HSH_DATW+112(a0)
	216	dmfc2 t3, 0x0253
	217	sd t0, OCTEON_CP2_HSH_IVW(a0)
	218	dmfc2 t0, 0x0254
	219	sd t1, OCTEON_CP2_HSH_IVW+8(a0)
	220	dmfc2 t1, 0x0255
	221	sd t2, OCTEON_CP2_HSH_IVW+16(a0)
	222	dmfc2 t2, 0x0256
	223	sd t3, OCTEON_CP2_HSH_IVW+24(a0)
	224	dmfc2 t3, 0x0257
	225	sd t0, OCTEON_CP2_HSH_IVW+32(a0)
70342287	226	dmfc2 t0, 0x0258
5b3b1688	227	sd t1, OCTEON_CP2_HSH_IVW+40(a0)
70342287	228	dmfc2 t1, 0x0259
5b3b1688 DD	229	sd t2, OCTEON_CP2_HSH_IVW+48(a0)
	230	dmfc2 t2, 0x025E
	231	sd t3, OCTEON_CP2_HSH_IVW+56(a0)
	232	dmfc2 t3, 0x025A
	233	sd t0, OCTEON_CP2_GFM_MULT(a0)
	234	dmfc2 t0, 0x025B
	235	sd t1, OCTEON_CP2_GFM_MULT+8(a0)
	236	sd t2, OCTEON_CP2_GFM_POLY(a0)
	237	sd t3, OCTEON_CP2_GFM_RESULT(a0)
6b3a287e DD	238	bltz v1, 4f
	239	sd t0, OCTEON_CP2_GFM_RESULT+8(a0)
	240	/* OCTEON III things*/
	241	dmfc2 t0, 0x024F
	242	dmfc2 t1, 0x0050
	243	sd t0, OCTEON_CP2_SHA3(a0)
	244	sd t1, OCTEON_CP2_SHA3+8(a0)
	245	4:
5b3b1688	246	jr ra
6b3a287e	247	nop
5b3b1688	248
70342287	249	2: /* pass 1 special stuff when !CvmCtl[NOCRYPTO] */
5b3b1688 DD	250	dmfc2 t3, 0x0040
	251	dmfc2 t0, 0x0041
	252	dmfc2 t1, 0x0042
	253	dmfc2 t2, 0x0043
	254	sd t3, OCTEON_CP2_HSH_DATW(a0)
	255	dmfc2 t3, 0x0044
	256	sd t0, OCTEON_CP2_HSH_DATW+8(a0)
	257	dmfc2 t0, 0x0045
	258	sd t1, OCTEON_CP2_HSH_DATW+16(a0)
	259	dmfc2 t1, 0x0046
	260	sd t2, OCTEON_CP2_HSH_DATW+24(a0)
	261	dmfc2 t2, 0x0048
	262	sd t3, OCTEON_CP2_HSH_DATW+32(a0)
	263	dmfc2 t3, 0x0049
	264	sd t0, OCTEON_CP2_HSH_DATW+40(a0)
	265	dmfc2 t0, 0x004A
	266	sd t1, OCTEON_CP2_HSH_DATW+48(a0)
	267	sd t2, OCTEON_CP2_HSH_IVW(a0)
	268	sd t3, OCTEON_CP2_HSH_IVW+8(a0)
	269	sd t0, OCTEON_CP2_HSH_IVW+16(a0)
	270
70342287	271	3: /* pass 1 or CvmCtl[NOCRYPTO] set */
5b3b1688	272	jr ra
6b3a287e	273	nop
5b3b1688	274	END(octeon_cop2_save)
6b3a287e	275	.set pop
5b3b1688 DD	276
	277	/*
	278	* void octeon_cop2_restore(struct octeon_cop2_state *a0)
	279	*/
	280	.align 7
	281	.set push
	282	.set noreorder
	283	LEAF(octeon_cop2_restore)
70342287 RB	284	/* First cache line was prefetched before the call */
70342287 RB	285	pref 4, 128(a0)
5b3b1688 DD	286	dmfc0 t9, $9,7 /* CvmCtl register. */
5b3b1688 DD	287
70342287	288	pref 4, 256(a0)
5b3b1688	289	ld t0, OCTEON_CP2_CRC_IV(a0)
70342287	290	pref 4, 384(a0)
5b3b1688 DD	291	ld t1, OCTEON_CP2_CRC_LENGTH(a0)
	292	ld t2, OCTEON_CP2_CRC_POLY(a0)
	293
	294	/* Restore the COP2 CRC state */
	295	dmtc2 t0, 0x0201
70342287	296	dmtc2 t1, 0x1202
5b3b1688 DD	297	bbit1 t9, 28, 2f /* Skip LLM if CvmCtl[NODFA_CP2] is set */
	298	dmtc2 t2, 0x4200
	299
	300	/* Restore the LLM state */
	301	ld t0, OCTEON_CP2_LLM_DAT(a0)
	302	ld t1, OCTEON_CP2_LLM_DAT+8(a0)
	303	dmtc2 t0, 0x0402
	304	dmtc2 t1, 0x040A
	305
	306	2:
	307	bbit1 t9, 26, done_restore /* done if CvmCtl[NOCRYPTO] set */
	308	nop
	309
	310	/* Restore the COP2 crypto state common to pass 1 and pass 2 */
	311	ld t0, OCTEON_CP2_3DES_IV(a0)
	312	ld t1, OCTEON_CP2_3DES_KEY(a0)
	313	ld t2, OCTEON_CP2_3DES_KEY+8(a0)
70342287	314	dmtc2 t0, 0x0084
5b3b1688	315	ld t0, OCTEON_CP2_3DES_KEY+16(a0)
70342287	316	dmtc2 t1, 0x0080
5b3b1688	317	ld t1, OCTEON_CP2_3DES_RESULT(a0)
70342287	318	dmtc2 t2, 0x0081
5b3b1688 DD	319	ld t2, OCTEON_CP2_AES_INP0(a0) /* only really needed for pass 1 */
	320	dmtc2 t0, 0x0082
	321	ld t0, OCTEON_CP2_AES_IV(a0)
70342287	322	dmtc2 t1, 0x0098
5b3b1688	323	ld t1, OCTEON_CP2_AES_IV+8(a0)
70342287	324	dmtc2 t2, 0x010A /* only really needed for pass 1 */
5b3b1688	325	ld t2, OCTEON_CP2_AES_KEY(a0)
70342287	326	dmtc2 t0, 0x0102
5b3b1688 DD	327	ld t0, OCTEON_CP2_AES_KEY+8(a0)
	328	dmtc2 t1, 0x0103
	329	ld t1, OCTEON_CP2_AES_KEY+16(a0)
	330	dmtc2 t2, 0x0104
	331	ld t2, OCTEON_CP2_AES_KEY+24(a0)
	332	dmtc2 t0, 0x0105
	333	ld t0, OCTEON_CP2_AES_KEYLEN(a0)
	334	dmtc2 t1, 0x0106
	335	ld t1, OCTEON_CP2_AES_RESULT(a0)
	336	dmtc2 t2, 0x0107
	337	ld t2, OCTEON_CP2_AES_RESULT+8(a0)
70342287	338	mfc0 t3, $15,0 /* Get the processor ID register */
5b3b1688	339	dmtc2 t0, 0x0110
6b3a287e	340	li v0, 0x000d0000 /* This is the processor ID of Octeon Pass1 */
5b3b1688	341	dmtc2 t1, 0x0100
6b3a287e	342	bne v0, t3, 3f /* Skip the next stuff for non-pass1 */
5b3b1688 DD	343	dmtc2 t2, 0x0101
5b3b1688 DD	344
70342287	345	/* this code is specific for pass 1 */
5b3b1688 DD	346	ld t0, OCTEON_CP2_HSH_DATW(a0)
	347	ld t1, OCTEON_CP2_HSH_DATW+8(a0)
	348	ld t2, OCTEON_CP2_HSH_DATW+16(a0)
	349	dmtc2 t0, 0x0040
	350	ld t0, OCTEON_CP2_HSH_DATW+24(a0)
	351	dmtc2 t1, 0x0041
	352	ld t1, OCTEON_CP2_HSH_DATW+32(a0)
	353	dmtc2 t2, 0x0042
	354	ld t2, OCTEON_CP2_HSH_DATW+40(a0)
	355	dmtc2 t0, 0x0043
	356	ld t0, OCTEON_CP2_HSH_DATW+48(a0)
	357	dmtc2 t1, 0x0044
	358	ld t1, OCTEON_CP2_HSH_IVW(a0)
	359	dmtc2 t2, 0x0045
	360	ld t2, OCTEON_CP2_HSH_IVW+8(a0)
	361	dmtc2 t0, 0x0046
	362	ld t0, OCTEON_CP2_HSH_IVW+16(a0)
	363	dmtc2 t1, 0x0048
	364	dmtc2 t2, 0x0049
70342287	365	b done_restore /* unconditional branch */
5b3b1688 DD	366	dmtc2 t0, 0x004A
5b3b1688 DD	367
70342287	368	3: /* this is post-pass1 code */
5b3b1688	369	ld t2, OCTEON_CP2_HSH_DATW(a0)
6b3a287e	370	ori v0, v0, 0x9500 /* lowest OCTEON III PrId*/
5b3b1688 DD	371	ld t0, OCTEON_CP2_HSH_DATW+8(a0)
	372	ld t1, OCTEON_CP2_HSH_DATW+16(a0)
	373	dmtc2 t2, 0x0240
	374	ld t2, OCTEON_CP2_HSH_DATW+24(a0)
	375	dmtc2 t0, 0x0241
	376	ld t0, OCTEON_CP2_HSH_DATW+32(a0)
	377	dmtc2 t1, 0x0242
	378	ld t1, OCTEON_CP2_HSH_DATW+40(a0)
	379	dmtc2 t2, 0x0243
	380	ld t2, OCTEON_CP2_HSH_DATW+48(a0)
	381	dmtc2 t0, 0x0244
	382	ld t0, OCTEON_CP2_HSH_DATW+56(a0)
	383	dmtc2 t1, 0x0245
	384	ld t1, OCTEON_CP2_HSH_DATW+64(a0)
	385	dmtc2 t2, 0x0246
	386	ld t2, OCTEON_CP2_HSH_DATW+72(a0)
	387	dmtc2 t0, 0x0247
	388	ld t0, OCTEON_CP2_HSH_DATW+80(a0)
	389	dmtc2 t1, 0x0248
	390	ld t1, OCTEON_CP2_HSH_DATW+88(a0)
	391	dmtc2 t2, 0x0249
	392	ld t2, OCTEON_CP2_HSH_DATW+96(a0)
	393	dmtc2 t0, 0x024A
	394	ld t0, OCTEON_CP2_HSH_DATW+104(a0)
	395	dmtc2 t1, 0x024B
	396	ld t1, OCTEON_CP2_HSH_DATW+112(a0)
	397	dmtc2 t2, 0x024C
	398	ld t2, OCTEON_CP2_HSH_IVW(a0)
	399	dmtc2 t0, 0x024D
	400	ld t0, OCTEON_CP2_HSH_IVW+8(a0)
	401	dmtc2 t1, 0x024E
	402	ld t1, OCTEON_CP2_HSH_IVW+16(a0)
	403	dmtc2 t2, 0x0250
	404	ld t2, OCTEON_CP2_HSH_IVW+24(a0)
	405	dmtc2 t0, 0x0251
	406	ld t0, OCTEON_CP2_HSH_IVW+32(a0)
	407	dmtc2 t1, 0x0252
	408	ld t1, OCTEON_CP2_HSH_IVW+40(a0)
	409	dmtc2 t2, 0x0253
	410	ld t2, OCTEON_CP2_HSH_IVW+48(a0)
	411	dmtc2 t0, 0x0254
	412	ld t0, OCTEON_CP2_HSH_IVW+56(a0)
	413	dmtc2 t1, 0x0255
	414	ld t1, OCTEON_CP2_GFM_MULT(a0)
	415	dmtc2 t2, 0x0256
	416	ld t2, OCTEON_CP2_GFM_MULT+8(a0)
	417	dmtc2 t0, 0x0257
	418	ld t0, OCTEON_CP2_GFM_POLY(a0)
	419	dmtc2 t1, 0x0258
	420	ld t1, OCTEON_CP2_GFM_RESULT(a0)
	421	dmtc2 t2, 0x0259
	422	ld t2, OCTEON_CP2_GFM_RESULT+8(a0)
	423	dmtc2 t0, 0x025E
6b3a287e	424	subu v0, t3, v0 /* prid - lowest OCTEON III PrId */
5b3b1688	425	dmtc2 t1, 0x025A
6b3a287e DD	426	bltz v0, done_restore
	427	dmtc2 t2, 0x025B
	428	/* OCTEON III things*/
	429	ld t0, OCTEON_CP2_SHA3(a0)
	430	ld t1, OCTEON_CP2_SHA3+8(a0)
	431	dmtc2 t0, 0x0051
	432	dmtc2 t1, 0x0050
5b3b1688 DD	433	done_restore:
	434	jr ra
	435	nop
	436	END(octeon_cop2_restore)
	437	.set pop
	438
	439	/*
	440	* void octeon_mult_save()
	441	* sp is assumed to point to a struct pt_regs
	442	*
ac655fb7 DD	443	* NOTE: This is called in SAVE_TEMP in stackframe.h. It can
	444	* safely modify v1,k0, k1,$10-$15, and $24. It will
	445	* be overwritten with a processor specific version of the code.
5b3b1688	446	*/
ac655fb7	447	.p2align 7
5b3b1688 DD	448	.set push
	449	.set noreorder
	450	LEAF(octeon_mult_save)
ac655fb7	451	jr ra
5b3b1688	452	nop
ac655fb7 DD	453	.space 30 * 4, 0
	454	octeon_mult_save_end:
	455	EXPORT(octeon_mult_save_end)
	456	END(octeon_mult_save)
5b3b1688	457
ac655fb7 DD	458	LEAF(octeon_mult_save2)
ac655fb7 DD	459	/* Save the multiplier state OCTEON II and earlier*/
5b3b1688 DD	460	v3mulu k0, $0, $0
5b3b1688 DD	461	v3mulu k1, $0, $0
70342287	462	sd k0, PT_MTP(sp) /* PT_MTP has P0 */
5b3b1688 DD	463	v3mulu k0, $0, $0
	464	sd k1, PT_MTP+8(sp) /* PT_MTP+8 has P1 */
	465	ori k1, $0, 1
	466	v3mulu k1, k1, $0
	467	sd k0, PT_MTP+16(sp) /* PT_MTP+16 has P2 */
	468	v3mulu k0, $0, $0
70342287	469	sd k1, PT_MPL(sp) /* PT_MPL has MPL0 */
5b3b1688 DD	470	v3mulu k1, $0, $0
	471	sd k0, PT_MPL+8(sp) /* PT_MPL+8 has MPL1 */
	472	jr ra
	473	sd k1, PT_MPL+16(sp) /* PT_MPL+16 has MPL2 */
ac655fb7 DD	474	octeon_mult_save2_end:
	475	EXPORT(octeon_mult_save2_end)
	476	END(octeon_mult_save2)
	477
	478	LEAF(octeon_mult_save3)
	479	/* Save the multiplier state OCTEON III */
	480	v3mulu $10, $0, $0 /* read P0 */
	481	v3mulu $11, $0, $0 /* read P1 */
	482	v3mulu $12, $0, $0 /* read P2 */
	483	sd $10, PT_MTP+(08)(sp) / store P0 */
	484	v3mulu $10, $0, $0 /* read P3 */
	485	sd $11, PT_MTP+(18)(sp) / store P1 */
	486	v3mulu $11, $0, $0 /* read P4 */
	487	sd $12, PT_MTP+(28)(sp) / store P2 */
	488	ori $13, $0, 1
	489	v3mulu $12, $0, $0 /* read P5 */
	490	sd $10, PT_MTP+(38)(sp) / store P3 */
	491	v3mulu $13, $13, $0 /* P4-P0 = MPL5-MPL1, $13 = MPL0 */
	492	sd $11, PT_MTP+(48)(sp) / store P4 */
	493	v3mulu $10, $0, $0 /* read MPL1 */
	494	sd $12, PT_MTP+(58)(sp) / store P5 */
	495	v3mulu $11, $0, $0 /* read MPL2 */
	496	sd $13, PT_MPL+(08)(sp) / store MPL0 */
	497	v3mulu $12, $0, $0 /* read MPL3 */
	498	sd $10, PT_MPL+(18)(sp) / store MPL1 */
	499	v3mulu $10, $0, $0 /* read MPL4 */
	500	sd $11, PT_MPL+(28)(sp) / store MPL2 */
	501	v3mulu $11, $0, $0 /* read MPL5 */
	502	sd $12, PT_MPL+(38)(sp) / store MPL3 */
	503	sd $10, PT_MPL+(48)(sp) / store MPL4 */
5b3b1688	504	jr ra
ac655fb7 DD	505	sd $11, PT_MPL+(58)(sp) / store MPL5 */
	506	octeon_mult_save3_end:
	507	EXPORT(octeon_mult_save3_end)
	508	END(octeon_mult_save3)
5b3b1688 DD	509	.set pop
	510
	511	/*
	512	* void octeon_mult_restore()
	513	* sp is assumed to point to a struct pt_regs
	514	*
ac655fb7	515	* NOTE: This is called in RESTORE_TEMP in stackframe.h.
5b3b1688	516	*/
ac655fb7	517	.p2align 7
5b3b1688 DD	518	.set push
	519	.set noreorder
	520	LEAF(octeon_mult_restore)
ac655fb7 DD	521	jr ra
	522	nop
	523	.space 30 * 4, 0
	524	octeon_mult_restore_end:
	525	EXPORT(octeon_mult_restore_end)
	526	END(octeon_mult_restore)
5b3b1688	527
ac655fb7 DD	528	LEAF(octeon_mult_restore2)
	529	ld v0, PT_MPL(sp) /* MPL0 */
	530	ld v1, PT_MPL+8(sp) /* MPL1 */
	531	ld k0, PT_MPL+16(sp) /* MPL2 */
5b3b1688	532	/* Restore the multiplier state */
ac655fb7 DD	533	ld k1, PT_MTP+16(sp) /* P2 */
ac655fb7 DD	534	mtm0 v0 /* MPL0 */
5b3b1688	535	ld v0, PT_MTP+8(sp) /* P1 */
ac655fb7 DD	536	mtm1 v1 /* MPL1 */
	537	ld v1, PT_MTP(sp) /* P0 */
	538	mtm2 k0 /* MPL2 */
	539	mtp2 k1 /* P2 */
	540	mtp1 v0 /* P1 */
5b3b1688	541	jr ra
ac655fb7 DD	542	mtp0 v1 /* P0 */
	543	octeon_mult_restore2_end:
	544	EXPORT(octeon_mult_restore2_end)
	545	END(octeon_mult_restore2)
	546
	547	LEAF(octeon_mult_restore3)
	548	ld $12, PT_MPL+(08)(sp) / read MPL0 */
	549	ld $13, PT_MPL+(38)(sp) / read MPL3 */
	550	ld $10, PT_MPL+(18)(sp) / read MPL1 */
	551	ld $11, PT_MPL+(48)(sp) / read MPL4 */
	552	.word 0x718d0008
	553	/* mtm0 $12, $13 restore MPL0 and MPL3 */
	554	ld $12, PT_MPL+(28)(sp) / read MPL2 */
	555	.word 0x714b000c
	556	/* mtm1 $10, $11 restore MPL1 and MPL4 */
	557	ld $13, PT_MPL+(58)(sp) / read MPL5 */
	558	ld $10, PT_MTP+(08)(sp) / read P0 */
	559	ld $11, PT_MTP+(38)(sp) / read P3 */
	560	.word 0x718d000d
	561	/* mtm2 $12, $13 restore MPL2 and MPL5 */
	562	ld $12, PT_MTP+(18)(sp) / read P1 */
	563	.word 0x714b0009
	564	/* mtp0 $10, $11 restore P0 and P3 */
	565	ld $13, PT_MTP+(48)(sp) / read P4 */
	566	ld $10, PT_MTP+(28)(sp) / read P2 */
	567	ld $11, PT_MTP+(58)(sp) / read P5 */
	568	.word 0x718d000a
	569	/* mtp1 $12, $13 restore P1 and P4 */
5b3b1688	570	jr ra
ac655fb7 DD	571	.word 0x714b000b
	572	/* mtp2 $10, $11 restore P2 and P5 */
	573
	574	octeon_mult_restore3_end:
	575	EXPORT(octeon_mult_restore3_end)
	576	END(octeon_mult_restore3)
5b3b1688	577	.set pop