Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * Copyright (C) 1992 Ross Biro | |
7 | * Copyright (C) Linus Torvalds | |
8 | * Copyright (C) 1994, 95, 96, 97, 98, 2000 Ralf Baechle | |
9 | * Copyright (C) 1996 David S. Miller | |
10 | * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com | |
11 | * Copyright (C) 1999 MIPS Technologies, Inc. | |
12 | * Copyright (C) 2000 Ulf Carlsson | |
13 | * | |
14 | * At this time Linux/MIPS64 only supports syscall tracing, even for 32-bit | |
15 | * binaries. | |
16 | */ | |
17 | #include <linux/config.h> | |
18 | #include <linux/compiler.h> | |
19 | #include <linux/kernel.h> | |
20 | #include <linux/sched.h> | |
21 | #include <linux/mm.h> | |
22 | #include <linux/errno.h> | |
23 | #include <linux/ptrace.h> | |
24 | #include <linux/audit.h> | |
25 | #include <linux/smp.h> | |
26 | #include <linux/smp_lock.h> | |
27 | #include <linux/user.h> | |
28 | #include <linux/security.h> | |
7ed20e1a | 29 | #include <linux/signal.h> |
1da177e4 | 30 | |
f8280c8d | 31 | #include <asm/byteorder.h> |
1da177e4 | 32 | #include <asm/cpu.h> |
e50c0a8f | 33 | #include <asm/dsp.h> |
1da177e4 LT |
34 | #include <asm/fpu.h> |
35 | #include <asm/mipsregs.h> | |
101b3531 | 36 | #include <asm/mipsmtregs.h> |
1da177e4 LT |
37 | #include <asm/pgtable.h> |
38 | #include <asm/page.h> | |
39 | #include <asm/system.h> | |
40 | #include <asm/uaccess.h> | |
41 | #include <asm/bootinfo.h> | |
ea3d710f | 42 | #include <asm/reg.h> |
1da177e4 LT |
43 | |
44 | /* | |
45 | * Called by kernel/ptrace.c when detaching.. | |
46 | * | |
47 | * Make sure single step bits etc are not set. | |
48 | */ | |
49 | void ptrace_disable(struct task_struct *child) | |
50 | { | |
51 | /* Nothing to do.. */ | |
52 | } | |
53 | ||
ea3d710f DJ |
54 | /* |
55 | * Read a general register set. We always use the 64-bit format, even | |
56 | * for 32-bit kernels and for 32-bit processes on a 64-bit kernel. | |
57 | * Registers are sign extended to fill the available space. | |
58 | */ | |
59 | int ptrace_getregs (struct task_struct *child, __s64 __user *data) | |
60 | { | |
61 | struct pt_regs *regs; | |
62 | int i; | |
63 | ||
64 | if (!access_ok(VERIFY_WRITE, data, 38 * 8)) | |
65 | return -EIO; | |
66 | ||
40bc9c67 | 67 | regs = task_pt_regs(child); |
ea3d710f DJ |
68 | |
69 | for (i = 0; i < 32; i++) | |
70 | __put_user (regs->regs[i], data + i); | |
71 | __put_user (regs->lo, data + EF_LO - EF_R0); | |
72 | __put_user (regs->hi, data + EF_HI - EF_R0); | |
73 | __put_user (regs->cp0_epc, data + EF_CP0_EPC - EF_R0); | |
74 | __put_user (regs->cp0_badvaddr, data + EF_CP0_BADVADDR - EF_R0); | |
75 | __put_user (regs->cp0_status, data + EF_CP0_STATUS - EF_R0); | |
76 | __put_user (regs->cp0_cause, data + EF_CP0_CAUSE - EF_R0); | |
77 | ||
78 | return 0; | |
79 | } | |
80 | ||
81 | /* | |
82 | * Write a general register set. As for PTRACE_GETREGS, we always use | |
83 | * the 64-bit format. On a 32-bit kernel only the lower order half | |
84 | * (according to endianness) will be used. | |
85 | */ | |
86 | int ptrace_setregs (struct task_struct *child, __s64 __user *data) | |
87 | { | |
88 | struct pt_regs *regs; | |
89 | int i; | |
90 | ||
91 | if (!access_ok(VERIFY_READ, data, 38 * 8)) | |
92 | return -EIO; | |
93 | ||
40bc9c67 | 94 | regs = task_pt_regs(child); |
ea3d710f DJ |
95 | |
96 | for (i = 0; i < 32; i++) | |
97 | __get_user (regs->regs[i], data + i); | |
98 | __get_user (regs->lo, data + EF_LO - EF_R0); | |
99 | __get_user (regs->hi, data + EF_HI - EF_R0); | |
100 | __get_user (regs->cp0_epc, data + EF_CP0_EPC - EF_R0); | |
101 | ||
102 | /* badvaddr, status, and cause may not be written. */ | |
103 | ||
104 | return 0; | |
105 | } | |
106 | ||
107 | int ptrace_getfpregs (struct task_struct *child, __u32 __user *data) | |
108 | { | |
109 | int i; | |
110 | ||
111 | if (!access_ok(VERIFY_WRITE, data, 33 * 8)) | |
112 | return -EIO; | |
113 | ||
114 | if (tsk_used_math(child)) { | |
115 | fpureg_t *fregs = get_fpu_regs(child); | |
116 | for (i = 0; i < 32; i++) | |
117 | __put_user (fregs[i], i + (__u64 __user *) data); | |
118 | } else { | |
119 | for (i = 0; i < 32; i++) | |
120 | __put_user ((__u64) -1, i + (__u64 __user *) data); | |
121 | } | |
122 | ||
123 | if (cpu_has_fpu) { | |
124 | unsigned int flags, tmp; | |
125 | ||
126 | __put_user (child->thread.fpu.hard.fcr31, data + 64); | |
127 | ||
101b3531 RB |
128 | preempt_disable(); |
129 | if (cpu_has_mipsmt) { | |
130 | unsigned int vpflags = dvpe(); | |
131 | flags = read_c0_status(); | |
132 | __enable_fpu(); | |
133 | __asm__ __volatile__("cfc1\t%0,$0" : "=r" (tmp)); | |
134 | write_c0_status(flags); | |
135 | evpe(vpflags); | |
136 | } else { | |
137 | flags = read_c0_status(); | |
138 | __enable_fpu(); | |
139 | __asm__ __volatile__("cfc1\t%0,$0" : "=r" (tmp)); | |
140 | write_c0_status(flags); | |
141 | } | |
142 | preempt_enable(); | |
ea3d710f DJ |
143 | __put_user (tmp, data + 65); |
144 | } else { | |
145 | __put_user (child->thread.fpu.soft.fcr31, data + 64); | |
146 | __put_user ((__u32) 0, data + 65); | |
147 | } | |
148 | ||
149 | return 0; | |
150 | } | |
151 | ||
152 | int ptrace_setfpregs (struct task_struct *child, __u32 __user *data) | |
153 | { | |
154 | fpureg_t *fregs; | |
155 | int i; | |
156 | ||
157 | if (!access_ok(VERIFY_READ, data, 33 * 8)) | |
158 | return -EIO; | |
159 | ||
160 | fregs = get_fpu_regs(child); | |
161 | ||
162 | for (i = 0; i < 32; i++) | |
163 | __get_user (fregs[i], i + (__u64 __user *) data); | |
164 | ||
165 | if (cpu_has_fpu) | |
166 | __get_user (child->thread.fpu.hard.fcr31, data + 64); | |
167 | else | |
168 | __get_user (child->thread.fpu.soft.fcr31, data + 64); | |
169 | ||
170 | /* FIR may not be written. */ | |
171 | ||
172 | return 0; | |
173 | } | |
174 | ||
481bed45 | 175 | long arch_ptrace(struct task_struct *child, long request, long addr, long data) |
1da177e4 | 176 | { |
1da177e4 LT |
177 | int ret; |
178 | ||
1da177e4 LT |
179 | switch (request) { |
180 | /* when I and D space are separate, these will need to be fixed. */ | |
181 | case PTRACE_PEEKTEXT: /* read word at location addr. */ | |
182 | case PTRACE_PEEKDATA: { | |
183 | unsigned long tmp; | |
184 | int copied; | |
185 | ||
186 | copied = access_process_vm(child, addr, &tmp, sizeof(tmp), 0); | |
187 | ret = -EIO; | |
188 | if (copied != sizeof(tmp)) | |
189 | break; | |
fe00f943 | 190 | ret = put_user(tmp,(unsigned long __user *) data); |
1da177e4 LT |
191 | break; |
192 | } | |
193 | ||
194 | /* Read the word at location addr in the USER area. */ | |
195 | case PTRACE_PEEKUSR: { | |
196 | struct pt_regs *regs; | |
197 | unsigned long tmp = 0; | |
198 | ||
40bc9c67 | 199 | regs = task_pt_regs(child); |
1da177e4 LT |
200 | ret = 0; /* Default return value. */ |
201 | ||
202 | switch (addr) { | |
203 | case 0 ... 31: | |
204 | tmp = regs->regs[addr]; | |
205 | break; | |
206 | case FPR_BASE ... FPR_BASE + 31: | |
207 | if (tsk_used_math(child)) { | |
208 | fpureg_t *fregs = get_fpu_regs(child); | |
209 | ||
875d43e7 | 210 | #ifdef CONFIG_32BIT |
1da177e4 LT |
211 | /* |
212 | * The odd registers are actually the high | |
213 | * order bits of the values stored in the even | |
214 | * registers - unless we're using r2k_switch.S. | |
215 | */ | |
216 | if (addr & 1) | |
217 | tmp = (unsigned long) (fregs[((addr & ~1) - 32)] >> 32); | |
218 | else | |
219 | tmp = (unsigned long) (fregs[(addr - 32)] & 0xffffffff); | |
220 | #endif | |
875d43e7 | 221 | #ifdef CONFIG_64BIT |
1da177e4 LT |
222 | tmp = fregs[addr - FPR_BASE]; |
223 | #endif | |
224 | } else { | |
225 | tmp = -1; /* FP not yet used */ | |
226 | } | |
227 | break; | |
228 | case PC: | |
229 | tmp = regs->cp0_epc; | |
230 | break; | |
231 | case CAUSE: | |
232 | tmp = regs->cp0_cause; | |
233 | break; | |
234 | case BADVADDR: | |
235 | tmp = regs->cp0_badvaddr; | |
236 | break; | |
237 | case MMHI: | |
238 | tmp = regs->hi; | |
239 | break; | |
240 | case MMLO: | |
241 | tmp = regs->lo; | |
242 | break; | |
243 | case FPC_CSR: | |
244 | if (cpu_has_fpu) | |
245 | tmp = child->thread.fpu.hard.fcr31; | |
246 | else | |
247 | tmp = child->thread.fpu.soft.fcr31; | |
248 | break; | |
249 | case FPC_EIR: { /* implementation / version register */ | |
250 | unsigned int flags; | |
251 | ||
252 | if (!cpu_has_fpu) | |
253 | break; | |
254 | ||
101b3531 RB |
255 | preempt_disable(); |
256 | if (cpu_has_mipsmt) { | |
257 | unsigned int vpflags = dvpe(); | |
258 | flags = read_c0_status(); | |
259 | __enable_fpu(); | |
260 | __asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp)); | |
261 | write_c0_status(flags); | |
262 | evpe(vpflags); | |
263 | } else { | |
264 | flags = read_c0_status(); | |
265 | __enable_fpu(); | |
266 | __asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp)); | |
267 | write_c0_status(flags); | |
268 | } | |
269 | preempt_enable(); | |
1da177e4 LT |
270 | break; |
271 | } | |
c134a5ec RB |
272 | case DSP_BASE ... DSP_BASE + 5: { |
273 | dspreg_t *dregs; | |
274 | ||
e50c0a8f RB |
275 | if (!cpu_has_dsp) { |
276 | tmp = 0; | |
277 | ret = -EIO; | |
481bed45 | 278 | goto out; |
e50c0a8f | 279 | } |
6c355852 RB |
280 | dregs = __get_dsp_regs(child); |
281 | tmp = (unsigned long) (dregs[addr - DSP_BASE]); | |
e50c0a8f | 282 | break; |
c134a5ec | 283 | } |
e50c0a8f RB |
284 | case DSP_CONTROL: |
285 | if (!cpu_has_dsp) { | |
286 | tmp = 0; | |
287 | ret = -EIO; | |
481bed45 | 288 | goto out; |
e50c0a8f RB |
289 | } |
290 | tmp = child->thread.dsp.dspcontrol; | |
291 | break; | |
1da177e4 LT |
292 | default: |
293 | tmp = 0; | |
294 | ret = -EIO; | |
481bed45 | 295 | goto out; |
1da177e4 | 296 | } |
fe00f943 | 297 | ret = put_user(tmp, (unsigned long __user *) data); |
1da177e4 LT |
298 | break; |
299 | } | |
300 | ||
301 | /* when I and D space are separate, this will have to be fixed. */ | |
302 | case PTRACE_POKETEXT: /* write the word at location addr. */ | |
303 | case PTRACE_POKEDATA: | |
304 | ret = 0; | |
305 | if (access_process_vm(child, addr, &data, sizeof(data), 1) | |
306 | == sizeof(data)) | |
307 | break; | |
308 | ret = -EIO; | |
309 | break; | |
310 | ||
311 | case PTRACE_POKEUSR: { | |
312 | struct pt_regs *regs; | |
313 | ret = 0; | |
40bc9c67 | 314 | regs = task_pt_regs(child); |
1da177e4 LT |
315 | |
316 | switch (addr) { | |
317 | case 0 ... 31: | |
318 | regs->regs[addr] = data; | |
319 | break; | |
320 | case FPR_BASE ... FPR_BASE + 31: { | |
321 | fpureg_t *fregs = get_fpu_regs(child); | |
322 | ||
323 | if (!tsk_used_math(child)) { | |
324 | /* FP not yet used */ | |
325 | memset(&child->thread.fpu.hard, ~0, | |
326 | sizeof(child->thread.fpu.hard)); | |
327 | child->thread.fpu.hard.fcr31 = 0; | |
328 | } | |
875d43e7 | 329 | #ifdef CONFIG_32BIT |
1da177e4 LT |
330 | /* |
331 | * The odd registers are actually the high order bits | |
332 | * of the values stored in the even registers - unless | |
333 | * we're using r2k_switch.S. | |
334 | */ | |
335 | if (addr & 1) { | |
336 | fregs[(addr & ~1) - FPR_BASE] &= 0xffffffff; | |
337 | fregs[(addr & ~1) - FPR_BASE] |= ((unsigned long long) data) << 32; | |
338 | } else { | |
339 | fregs[addr - FPR_BASE] &= ~0xffffffffLL; | |
340 | fregs[addr - FPR_BASE] |= data; | |
341 | } | |
342 | #endif | |
875d43e7 | 343 | #ifdef CONFIG_64BIT |
1da177e4 LT |
344 | fregs[addr - FPR_BASE] = data; |
345 | #endif | |
346 | break; | |
347 | } | |
348 | case PC: | |
349 | regs->cp0_epc = data; | |
350 | break; | |
351 | case MMHI: | |
352 | regs->hi = data; | |
353 | break; | |
354 | case MMLO: | |
355 | regs->lo = data; | |
356 | break; | |
357 | case FPC_CSR: | |
358 | if (cpu_has_fpu) | |
359 | child->thread.fpu.hard.fcr31 = data; | |
360 | else | |
361 | child->thread.fpu.soft.fcr31 = data; | |
362 | break; | |
c134a5ec RB |
363 | case DSP_BASE ... DSP_BASE + 5: { |
364 | dspreg_t *dregs; | |
365 | ||
e50c0a8f RB |
366 | if (!cpu_has_dsp) { |
367 | ret = -EIO; | |
368 | break; | |
369 | } | |
370 | ||
c134a5ec | 371 | dregs = __get_dsp_regs(child); |
e50c0a8f RB |
372 | dregs[addr - DSP_BASE] = data; |
373 | break; | |
c134a5ec | 374 | } |
e50c0a8f RB |
375 | case DSP_CONTROL: |
376 | if (!cpu_has_dsp) { | |
377 | ret = -EIO; | |
378 | break; | |
379 | } | |
380 | child->thread.dsp.dspcontrol = data; | |
381 | break; | |
1da177e4 LT |
382 | default: |
383 | /* The rest are not allowed. */ | |
384 | ret = -EIO; | |
385 | break; | |
386 | } | |
387 | break; | |
388 | } | |
389 | ||
ea3d710f DJ |
390 | case PTRACE_GETREGS: |
391 | ret = ptrace_getregs (child, (__u64 __user *) data); | |
392 | break; | |
393 | ||
394 | case PTRACE_SETREGS: | |
395 | ret = ptrace_setregs (child, (__u64 __user *) data); | |
396 | break; | |
397 | ||
398 | case PTRACE_GETFPREGS: | |
399 | ret = ptrace_getfpregs (child, (__u32 __user *) data); | |
400 | break; | |
401 | ||
402 | case PTRACE_SETFPREGS: | |
403 | ret = ptrace_setfpregs (child, (__u32 __user *) data); | |
404 | break; | |
405 | ||
1da177e4 LT |
406 | case PTRACE_SYSCALL: /* continue and stop at next (return from) syscall */ |
407 | case PTRACE_CONT: { /* restart after signal. */ | |
408 | ret = -EIO; | |
7ed20e1a | 409 | if (!valid_signal(data)) |
1da177e4 LT |
410 | break; |
411 | if (request == PTRACE_SYSCALL) { | |
412 | set_tsk_thread_flag(child, TIF_SYSCALL_TRACE); | |
413 | } | |
414 | else { | |
415 | clear_tsk_thread_flag(child, TIF_SYSCALL_TRACE); | |
416 | } | |
417 | child->exit_code = data; | |
418 | wake_up_process(child); | |
419 | ret = 0; | |
420 | break; | |
421 | } | |
422 | ||
423 | /* | |
424 | * make the child exit. Best I can do is send it a sigkill. | |
425 | * perhaps it should be put in the status that it wants to | |
426 | * exit. | |
427 | */ | |
428 | case PTRACE_KILL: | |
429 | ret = 0; | |
430 | if (child->exit_state == EXIT_ZOMBIE) /* already dead */ | |
431 | break; | |
432 | child->exit_code = SIGKILL; | |
433 | wake_up_process(child); | |
434 | break; | |
435 | ||
436 | case PTRACE_DETACH: /* detach a process that was attached. */ | |
437 | ret = ptrace_detach(child, data); | |
438 | break; | |
439 | ||
3c37026d | 440 | case PTRACE_GET_THREAD_AREA: |
dc8f6029 | 441 | ret = put_user(task_thread_info(child)->tp_value, |
3c37026d RB |
442 | (unsigned long __user *) data); |
443 | break; | |
444 | ||
1da177e4 LT |
445 | default: |
446 | ret = ptrace_request(child, request, addr, data); | |
447 | break; | |
448 | } | |
481bed45 | 449 | out: |
1da177e4 LT |
450 | return ret; |
451 | } | |
452 | ||
67eb81e1 | 453 | static inline int audit_arch(void) |
2fd6f58b | 454 | { |
f8280c8d | 455 | int arch = EM_MIPS; |
875d43e7 | 456 | #ifdef CONFIG_64BIT |
f8280c8d RB |
457 | arch |= __AUDIT_ARCH_64BIT; |
458 | #endif | |
459 | #if defined(__LITTLE_ENDIAN) | |
460 | arch |= __AUDIT_ARCH_LE; | |
461 | #endif | |
462 | return arch; | |
2fd6f58b | 463 | } |
464 | ||
1da177e4 LT |
465 | /* |
466 | * Notification of system call entry/exit | |
467 | * - triggered by current->work.syscall_trace | |
468 | */ | |
469 | asmlinkage void do_syscall_trace(struct pt_regs *regs, int entryexit) | |
470 | { | |
2fd6f58b | 471 | if (unlikely(current->audit_context) && entryexit) |
f8280c8d RB |
472 | audit_syscall_exit(current, AUDITSC_RESULT(regs->regs[2]), |
473 | regs->regs[2]); | |
1da177e4 | 474 | |
1da177e4 | 475 | if (!(current->ptrace & PT_PTRACED)) |
2fd6f58b | 476 | goto out; |
f8280c8d RB |
477 | if (!test_thread_flag(TIF_SYSCALL_TRACE)) |
478 | goto out; | |
1da177e4 LT |
479 | |
480 | /* The 0x80 provides a way for the tracing parent to distinguish | |
481 | between a syscall stop and SIGTRAP delivery */ | |
482 | ptrace_notify(SIGTRAP | ((current->ptrace & PT_TRACESYSGOOD) ? | |
483 | 0x80 : 0)); | |
484 | ||
485 | /* | |
486 | * this isn't the same as continuing with a signal, but it will do | |
487 | * for normal use. strace only continues with a signal if the | |
488 | * stopping signal is not SIGTRAP. -brl | |
489 | */ | |
490 | if (current->exit_code) { | |
491 | send_sig(current->exit_code, current, 1); | |
492 | current->exit_code = 0; | |
493 | } | |
2fd6f58b | 494 | out: |
495 | if (unlikely(current->audit_context) && !entryexit) | |
496 | audit_syscall_entry(current, audit_arch(), regs->regs[2], | |
497 | regs->regs[4], regs->regs[5], | |
498 | regs->regs[6], regs->regs[7]); | |
1da177e4 | 499 | } |