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1da177e4 LT |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * Copyright (C) 1996, 98, 99, 2000, 01 Ralf Baechle | |
7 | * | |
8 | * Multi-arch abstraction and asm macros for easier reading: | |
79add627 | 9 | * Copyright (C) 1996 David S. Miller (davem@davemloft.net) |
1da177e4 LT |
10 | * |
11 | * Carsten Langgaard, carstenl@mips.com | |
12 | * Copyright (C) 2000 MIPS Technologies, Inc. | |
13 | * Copyright (C) 1999, 2001 Silicon Graphics, Inc. | |
14 | */ | |
1da177e4 LT |
15 | #include <asm/asm.h> |
16 | #include <asm/errno.h> | |
17 | #include <asm/fpregdef.h> | |
18 | #include <asm/mipsregs.h> | |
048eb582 | 19 | #include <asm/asm-offsets.h> |
1da177e4 LT |
20 | #include <asm/regdef.h> |
21 | ||
22 | .macro EX insn, reg, src | |
23 | .set push | |
24 | .set nomacro | |
25 | .ex\@: \insn \reg, \src | |
26 | .set pop | |
27 | .section __ex_table,"a" | |
28 | PTR .ex\@, fault | |
29 | .previous | |
30 | .endm | |
31 | ||
32 | .set noreorder | |
33 | .set mips3 | |
e50c0a8f | 34 | |
1da177e4 LT |
35 | LEAF(_save_fp_context) |
36 | cfc1 t1, fcr31 | |
37 | ||
597ce172 PB |
38 | #if defined(CONFIG_64BIT) || defined(CONFIG_MIPS32_R2) |
39 | .set push | |
40 | #ifdef CONFIG_MIPS32_R2 | |
41 | .set mips64r2 | |
42 | mfc0 t0, CP0_STATUS | |
43 | sll t0, t0, 5 | |
44 | bgez t0, 1f # skip storing odd if FR=0 | |
45 | nop | |
46 | #endif | |
1da177e4 LT |
47 | /* Store the 16 odd double precision registers */ |
48 | EX sdc1 $f1, SC_FPREGS+8(a0) | |
49 | EX sdc1 $f3, SC_FPREGS+24(a0) | |
50 | EX sdc1 $f5, SC_FPREGS+40(a0) | |
51 | EX sdc1 $f7, SC_FPREGS+56(a0) | |
52 | EX sdc1 $f9, SC_FPREGS+72(a0) | |
53 | EX sdc1 $f11, SC_FPREGS+88(a0) | |
54 | EX sdc1 $f13, SC_FPREGS+104(a0) | |
55 | EX sdc1 $f15, SC_FPREGS+120(a0) | |
56 | EX sdc1 $f17, SC_FPREGS+136(a0) | |
57 | EX sdc1 $f19, SC_FPREGS+152(a0) | |
58 | EX sdc1 $f21, SC_FPREGS+168(a0) | |
59 | EX sdc1 $f23, SC_FPREGS+184(a0) | |
60 | EX sdc1 $f25, SC_FPREGS+200(a0) | |
61 | EX sdc1 $f27, SC_FPREGS+216(a0) | |
62 | EX sdc1 $f29, SC_FPREGS+232(a0) | |
63 | EX sdc1 $f31, SC_FPREGS+248(a0) | |
597ce172 | 64 | 1: .set pop |
1da177e4 LT |
65 | #endif |
66 | ||
67 | /* Store the 16 even double precision registers */ | |
68 | EX sdc1 $f0, SC_FPREGS+0(a0) | |
69 | EX sdc1 $f2, SC_FPREGS+16(a0) | |
70 | EX sdc1 $f4, SC_FPREGS+32(a0) | |
71 | EX sdc1 $f6, SC_FPREGS+48(a0) | |
72 | EX sdc1 $f8, SC_FPREGS+64(a0) | |
73 | EX sdc1 $f10, SC_FPREGS+80(a0) | |
74 | EX sdc1 $f12, SC_FPREGS+96(a0) | |
75 | EX sdc1 $f14, SC_FPREGS+112(a0) | |
76 | EX sdc1 $f16, SC_FPREGS+128(a0) | |
77 | EX sdc1 $f18, SC_FPREGS+144(a0) | |
78 | EX sdc1 $f20, SC_FPREGS+160(a0) | |
79 | EX sdc1 $f22, SC_FPREGS+176(a0) | |
80 | EX sdc1 $f24, SC_FPREGS+192(a0) | |
81 | EX sdc1 $f26, SC_FPREGS+208(a0) | |
82 | EX sdc1 $f28, SC_FPREGS+224(a0) | |
83 | EX sdc1 $f30, SC_FPREGS+240(a0) | |
84 | EX sw t1, SC_FPC_CSR(a0) | |
1da177e4 LT |
85 | jr ra |
86 | li v0, 0 # success | |
87 | END(_save_fp_context) | |
88 | ||
89 | #ifdef CONFIG_MIPS32_COMPAT | |
90 | /* Save 32-bit process floating point context */ | |
91 | LEAF(_save_fp_context32) | |
92 | cfc1 t1, fcr31 | |
93 | ||
597ce172 PB |
94 | mfc0 t0, CP0_STATUS |
95 | sll t0, t0, 5 | |
96 | bgez t0, 1f # skip storing odd if FR=0 | |
97 | nop | |
98 | ||
99 | /* Store the 16 odd double precision registers */ | |
100 | EX sdc1 $f1, SC32_FPREGS+8(a0) | |
101 | EX sdc1 $f3, SC32_FPREGS+24(a0) | |
102 | EX sdc1 $f5, SC32_FPREGS+40(a0) | |
103 | EX sdc1 $f7, SC32_FPREGS+56(a0) | |
104 | EX sdc1 $f9, SC32_FPREGS+72(a0) | |
105 | EX sdc1 $f11, SC32_FPREGS+88(a0) | |
106 | EX sdc1 $f13, SC32_FPREGS+104(a0) | |
107 | EX sdc1 $f15, SC32_FPREGS+120(a0) | |
108 | EX sdc1 $f17, SC32_FPREGS+136(a0) | |
109 | EX sdc1 $f19, SC32_FPREGS+152(a0) | |
110 | EX sdc1 $f21, SC32_FPREGS+168(a0) | |
111 | EX sdc1 $f23, SC32_FPREGS+184(a0) | |
112 | EX sdc1 $f25, SC32_FPREGS+200(a0) | |
113 | EX sdc1 $f27, SC32_FPREGS+216(a0) | |
114 | EX sdc1 $f29, SC32_FPREGS+232(a0) | |
115 | EX sdc1 $f31, SC32_FPREGS+248(a0) | |
116 | ||
117 | /* Store the 16 even double precision registers */ | |
118 | 1: EX sdc1 $f0, SC32_FPREGS+0(a0) | |
1da177e4 LT |
119 | EX sdc1 $f2, SC32_FPREGS+16(a0) |
120 | EX sdc1 $f4, SC32_FPREGS+32(a0) | |
121 | EX sdc1 $f6, SC32_FPREGS+48(a0) | |
122 | EX sdc1 $f8, SC32_FPREGS+64(a0) | |
123 | EX sdc1 $f10, SC32_FPREGS+80(a0) | |
124 | EX sdc1 $f12, SC32_FPREGS+96(a0) | |
125 | EX sdc1 $f14, SC32_FPREGS+112(a0) | |
126 | EX sdc1 $f16, SC32_FPREGS+128(a0) | |
127 | EX sdc1 $f18, SC32_FPREGS+144(a0) | |
128 | EX sdc1 $f20, SC32_FPREGS+160(a0) | |
129 | EX sdc1 $f22, SC32_FPREGS+176(a0) | |
130 | EX sdc1 $f24, SC32_FPREGS+192(a0) | |
131 | EX sdc1 $f26, SC32_FPREGS+208(a0) | |
132 | EX sdc1 $f28, SC32_FPREGS+224(a0) | |
133 | EX sdc1 $f30, SC32_FPREGS+240(a0) | |
134 | EX sw t1, SC32_FPC_CSR(a0) | |
135 | cfc1 t0, $0 # implementation/version | |
136 | EX sw t0, SC32_FPC_EIR(a0) | |
137 | ||
138 | jr ra | |
139 | li v0, 0 # success | |
140 | END(_save_fp_context32) | |
141 | #endif | |
142 | ||
143 | /* | |
144 | * Restore FPU state: | |
145 | * - fp gp registers | |
146 | * - cp1 status/control register | |
147 | */ | |
148 | LEAF(_restore_fp_context) | |
149 | EX lw t0, SC_FPC_CSR(a0) | |
597ce172 PB |
150 | |
151 | #if defined(CONFIG_64BIT) || defined(CONFIG_MIPS32_R2) | |
152 | .set push | |
153 | #ifdef CONFIG_MIPS32_R2 | |
154 | .set mips64r2 | |
155 | mfc0 t0, CP0_STATUS | |
156 | sll t0, t0, 5 | |
157 | bgez t0, 1f # skip loading odd if FR=0 | |
158 | nop | |
159 | #endif | |
1da177e4 LT |
160 | EX ldc1 $f1, SC_FPREGS+8(a0) |
161 | EX ldc1 $f3, SC_FPREGS+24(a0) | |
162 | EX ldc1 $f5, SC_FPREGS+40(a0) | |
163 | EX ldc1 $f7, SC_FPREGS+56(a0) | |
164 | EX ldc1 $f9, SC_FPREGS+72(a0) | |
165 | EX ldc1 $f11, SC_FPREGS+88(a0) | |
166 | EX ldc1 $f13, SC_FPREGS+104(a0) | |
167 | EX ldc1 $f15, SC_FPREGS+120(a0) | |
168 | EX ldc1 $f17, SC_FPREGS+136(a0) | |
169 | EX ldc1 $f19, SC_FPREGS+152(a0) | |
170 | EX ldc1 $f21, SC_FPREGS+168(a0) | |
171 | EX ldc1 $f23, SC_FPREGS+184(a0) | |
172 | EX ldc1 $f25, SC_FPREGS+200(a0) | |
173 | EX ldc1 $f27, SC_FPREGS+216(a0) | |
174 | EX ldc1 $f29, SC_FPREGS+232(a0) | |
175 | EX ldc1 $f31, SC_FPREGS+248(a0) | |
597ce172 | 176 | 1: .set pop |
1da177e4 LT |
177 | #endif |
178 | EX ldc1 $f0, SC_FPREGS+0(a0) | |
179 | EX ldc1 $f2, SC_FPREGS+16(a0) | |
180 | EX ldc1 $f4, SC_FPREGS+32(a0) | |
181 | EX ldc1 $f6, SC_FPREGS+48(a0) | |
182 | EX ldc1 $f8, SC_FPREGS+64(a0) | |
183 | EX ldc1 $f10, SC_FPREGS+80(a0) | |
184 | EX ldc1 $f12, SC_FPREGS+96(a0) | |
185 | EX ldc1 $f14, SC_FPREGS+112(a0) | |
186 | EX ldc1 $f16, SC_FPREGS+128(a0) | |
187 | EX ldc1 $f18, SC_FPREGS+144(a0) | |
188 | EX ldc1 $f20, SC_FPREGS+160(a0) | |
189 | EX ldc1 $f22, SC_FPREGS+176(a0) | |
190 | EX ldc1 $f24, SC_FPREGS+192(a0) | |
191 | EX ldc1 $f26, SC_FPREGS+208(a0) | |
192 | EX ldc1 $f28, SC_FPREGS+224(a0) | |
193 | EX ldc1 $f30, SC_FPREGS+240(a0) | |
194 | ctc1 t0, fcr31 | |
195 | jr ra | |
196 | li v0, 0 # success | |
197 | END(_restore_fp_context) | |
198 | ||
199 | #ifdef CONFIG_MIPS32_COMPAT | |
200 | LEAF(_restore_fp_context32) | |
201 | /* Restore an o32 sigcontext. */ | |
202 | EX lw t0, SC32_FPC_CSR(a0) | |
597ce172 PB |
203 | |
204 | mfc0 t0, CP0_STATUS | |
205 | sll t0, t0, 5 | |
206 | bgez t0, 1f # skip loading odd if FR=0 | |
207 | nop | |
208 | ||
209 | EX ldc1 $f1, SC32_FPREGS+8(a0) | |
210 | EX ldc1 $f3, SC32_FPREGS+24(a0) | |
211 | EX ldc1 $f5, SC32_FPREGS+40(a0) | |
212 | EX ldc1 $f7, SC32_FPREGS+56(a0) | |
213 | EX ldc1 $f9, SC32_FPREGS+72(a0) | |
214 | EX ldc1 $f11, SC32_FPREGS+88(a0) | |
215 | EX ldc1 $f13, SC32_FPREGS+104(a0) | |
216 | EX ldc1 $f15, SC32_FPREGS+120(a0) | |
217 | EX ldc1 $f17, SC32_FPREGS+136(a0) | |
218 | EX ldc1 $f19, SC32_FPREGS+152(a0) | |
219 | EX ldc1 $f21, SC32_FPREGS+168(a0) | |
220 | EX ldc1 $f23, SC32_FPREGS+184(a0) | |
221 | EX ldc1 $f25, SC32_FPREGS+200(a0) | |
222 | EX ldc1 $f27, SC32_FPREGS+216(a0) | |
223 | EX ldc1 $f29, SC32_FPREGS+232(a0) | |
224 | EX ldc1 $f31, SC32_FPREGS+248(a0) | |
225 | ||
226 | 1: EX ldc1 $f0, SC32_FPREGS+0(a0) | |
1da177e4 LT |
227 | EX ldc1 $f2, SC32_FPREGS+16(a0) |
228 | EX ldc1 $f4, SC32_FPREGS+32(a0) | |
229 | EX ldc1 $f6, SC32_FPREGS+48(a0) | |
230 | EX ldc1 $f8, SC32_FPREGS+64(a0) | |
231 | EX ldc1 $f10, SC32_FPREGS+80(a0) | |
232 | EX ldc1 $f12, SC32_FPREGS+96(a0) | |
233 | EX ldc1 $f14, SC32_FPREGS+112(a0) | |
234 | EX ldc1 $f16, SC32_FPREGS+128(a0) | |
235 | EX ldc1 $f18, SC32_FPREGS+144(a0) | |
236 | EX ldc1 $f20, SC32_FPREGS+160(a0) | |
237 | EX ldc1 $f22, SC32_FPREGS+176(a0) | |
238 | EX ldc1 $f24, SC32_FPREGS+192(a0) | |
239 | EX ldc1 $f26, SC32_FPREGS+208(a0) | |
240 | EX ldc1 $f28, SC32_FPREGS+224(a0) | |
241 | EX ldc1 $f30, SC32_FPREGS+240(a0) | |
242 | ctc1 t0, fcr31 | |
243 | jr ra | |
244 | li v0, 0 # success | |
245 | END(_restore_fp_context32) | |
1da177e4 LT |
246 | #endif |
247 | ||
37f26742 CD |
248 | .set reorder |
249 | ||
1da177e4 LT |
250 | .type fault@function |
251 | .ent fault | |
252 | fault: li v0, -EFAULT # failure | |
253 | jr ra | |
254 | .end fault |