tree-wide: replace config_enabled() with IS_ENABLED()
[deliverable/linux.git] / arch / mips / kernel / r6000_fpu.S
CommitLineData
1da177e4
LT
1/*
2 * r6000_fpu.S: Save/restore floating point context for signal handlers.
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 1996 by Ralf Baechle
9 *
10 * Multi-arch abstraction and asm macros for easier reading:
79add627 11 * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
1da177e4
LT
12 */
13#include <asm/asm.h>
14#include <asm/fpregdef.h>
15#include <asm/mipsregs.h>
048eb582 16#include <asm/asm-offsets.h>
1da177e4
LT
17#include <asm/regdef.h>
18
19 .set noreorder
20 .set mips2
842dfc11
ML
21 .set push
22 SET_HARDFLOAT
23
1da177e4
LT
24 /* Save floating point context */
25 LEAF(_save_fp_context)
26 mfc0 t0,CP0_STATUS
27 sll t0,t0,2
28 bgez t0,1f
29 nop
30
31 cfc1 t1,fcr31
32 /* Store the 16 double precision registers */
33 sdc1 $f0,(SC_FPREGS+0)(a0)
34 sdc1 $f2,(SC_FPREGS+16)(a0)
35 sdc1 $f4,(SC_FPREGS+32)(a0)
36 sdc1 $f6,(SC_FPREGS+48)(a0)
37 sdc1 $f8,(SC_FPREGS+64)(a0)
38 sdc1 $f10,(SC_FPREGS+80)(a0)
39 sdc1 $f12,(SC_FPREGS+96)(a0)
40 sdc1 $f14,(SC_FPREGS+112)(a0)
41 sdc1 $f16,(SC_FPREGS+128)(a0)
42 sdc1 $f18,(SC_FPREGS+144)(a0)
43 sdc1 $f20,(SC_FPREGS+160)(a0)
44 sdc1 $f22,(SC_FPREGS+176)(a0)
45 sdc1 $f24,(SC_FPREGS+192)(a0)
46 sdc1 $f26,(SC_FPREGS+208)(a0)
47 sdc1 $f28,(SC_FPREGS+224)(a0)
48 sdc1 $f30,(SC_FPREGS+240)(a0)
49 jr ra
50 sw t0,SC_FPC_CSR(a0)
511: jr ra
52 nop
53 END(_save_fp_context)
54
55/* Restore FPU state:
56 * - fp gp registers
57 * - cp1 status/control register
58 *
59 * We base the decision which registers to restore from the signal stack
60 * frame on the current content of c0_status, not on the content of the
61 * stack frame which might have been changed by the user.
62 */
63 LEAF(_restore_fp_context)
64 mfc0 t0,CP0_STATUS
65 sll t0,t0,2
66
67 bgez t0,1f
68 lw t0,SC_FPC_CSR(a0)
69 /* Restore the 16 double precision registers */
70 ldc1 $f0,(SC_FPREGS+0)(a0)
71 ldc1 $f2,(SC_FPREGS+16)(a0)
72 ldc1 $f4,(SC_FPREGS+32)(a0)
73 ldc1 $f6,(SC_FPREGS+48)(a0)
74 ldc1 $f8,(SC_FPREGS+64)(a0)
75 ldc1 $f10,(SC_FPREGS+80)(a0)
76 ldc1 $f12,(SC_FPREGS+96)(a0)
77 ldc1 $f14,(SC_FPREGS+112)(a0)
78 ldc1 $f16,(SC_FPREGS+128)(a0)
79 ldc1 $f18,(SC_FPREGS+144)(a0)
80 ldc1 $f20,(SC_FPREGS+160)(a0)
81 ldc1 $f22,(SC_FPREGS+176)(a0)
82 ldc1 $f24,(SC_FPREGS+192)(a0)
83 ldc1 $f26,(SC_FPREGS+208)(a0)
84 ldc1 $f28,(SC_FPREGS+224)(a0)
85 ldc1 $f30,(SC_FPREGS+240)(a0)
86 jr ra
87 ctc1 t0,fcr31
881: jr ra
89 nop
90 END(_restore_fp_context)
842dfc11
ML
91
92 .set pop /* SET_HARDFLOAT */
This page took 0.73733 seconds and 5 git commands to generate.