Commit | Line | Data |
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340ee4b9 | 1 | /* |
340ee4b9 RB |
2 | * This program is free software; you can distribute it and/or modify it |
3 | * under the terms of the GNU General Public License (Version 2) as | |
4 | * published by the Free Software Foundation. | |
5 | * | |
6 | * This program is distributed in the hope it will be useful, but WITHOUT | |
7 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
8 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
9 | * for more details. | |
10 | * | |
11 | * You should have received a copy of the GNU General Public License along | |
12 | * with this program; if not, write to the Free Software Foundation, Inc., | |
13 | * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. | |
14 | * | |
41c594ab RB |
15 | * Copyright (C) 2004, 05, 06 MIPS Technologies, Inc. |
16 | * Elizabeth Clarke (beth@mips.com) | |
17 | * Ralf Baechle (ralf@linux-mips.org) | |
18 | * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org) | |
340ee4b9 RB |
19 | */ |
20 | #include <linux/kernel.h> | |
21 | #include <linux/sched.h> | |
22 | #include <linux/cpumask.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/compiler.h> | |
0ab7aefc | 25 | #include <linux/smp.h> |
340ee4b9 | 26 | |
60063497 | 27 | #include <linux/atomic.h> |
41c594ab | 28 | #include <asm/cacheflush.h> |
340ee4b9 RB |
29 | #include <asm/cpu.h> |
30 | #include <asm/processor.h> | |
340ee4b9 RB |
31 | #include <asm/hardirq.h> |
32 | #include <asm/mmu_context.h> | |
340ee4b9 RB |
33 | #include <asm/time.h> |
34 | #include <asm/mipsregs.h> | |
35 | #include <asm/mipsmtregs.h> | |
41c594ab | 36 | #include <asm/mips_mt.h> |
340ee4b9 | 37 | |
39b8d525 | 38 | static void __init smvp_copy_vpe_config(void) |
781b0f8d RB |
39 | { |
40 | write_vpe_c0_status( | |
41 | (read_c0_status() & ~(ST0_IM | ST0_IE | ST0_KSU)) | ST0_CU0); | |
42 | ||
43 | /* set config to be the same as vpe0, particularly kseg0 coherency alg */ | |
44 | write_vpe_c0_config( read_c0_config()); | |
45 | ||
46 | /* make sure there are no software interrupts pending */ | |
47 | write_vpe_c0_cause(0); | |
48 | ||
49 | /* Propagate Config7 */ | |
50 | write_vpe_c0_config7(read_c0_config7()); | |
70e46f48 RB |
51 | |
52 | write_vpe_c0_count(read_c0_count()); | |
781b0f8d RB |
53 | } |
54 | ||
39b8d525 | 55 | static unsigned int __init smvp_vpe_init(unsigned int tc, unsigned int mvpconf0, |
781b0f8d RB |
56 | unsigned int ncpu) |
57 | { | |
58 | if (tc > ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT)) | |
59 | return ncpu; | |
60 | ||
61 | /* Deactivate all but VPE 0 */ | |
62 | if (tc != 0) { | |
63 | unsigned long tmp = read_vpe_c0_vpeconf0(); | |
64 | ||
65 | tmp &= ~VPECONF0_VPA; | |
66 | ||
67 | /* master VPE */ | |
68 | tmp |= VPECONF0_MVP; | |
69 | write_vpe_c0_vpeconf0(tmp); | |
70 | ||
71 | /* Record this as available CPU */ | |
4037ac6e | 72 | set_cpu_possible(tc, true); |
781b0f8d RB |
73 | __cpu_number_map[tc] = ++ncpu; |
74 | __cpu_logical_map[ncpu] = tc; | |
75 | } | |
76 | ||
77 | /* Disable multi-threading with TC's */ | |
78 | write_vpe_c0_vpecontrol(read_vpe_c0_vpecontrol() & ~VPECONTROL_TE); | |
79 | ||
80 | if (tc != 0) | |
39b8d525 | 81 | smvp_copy_vpe_config(); |
781b0f8d RB |
82 | |
83 | return ncpu; | |
84 | } | |
85 | ||
39b8d525 | 86 | static void __init smvp_tc_init(unsigned int tc, unsigned int mvpconf0) |
781b0f8d RB |
87 | { |
88 | unsigned long tmp; | |
89 | ||
90 | if (!tc) | |
91 | return; | |
92 | ||
93 | /* bind a TC to each VPE, May as well put all excess TC's | |
94 | on the last VPE */ | |
95 | if (tc >= (((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT)+1)) | |
96 | write_tc_c0_tcbind(read_tc_c0_tcbind() | ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT)); | |
97 | else { | |
98 | write_tc_c0_tcbind(read_tc_c0_tcbind() | tc); | |
99 | ||
100 | /* and set XTC */ | |
101 | write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() | (tc << VPECONF0_XTC_SHIFT)); | |
102 | } | |
103 | ||
104 | tmp = read_tc_c0_tcstatus(); | |
105 | ||
106 | /* mark not allocated and not dynamically allocatable */ | |
107 | tmp &= ~(TCSTATUS_A | TCSTATUS_DA); | |
108 | tmp |= TCSTATUS_IXMT; /* interrupt exempt */ | |
109 | write_tc_c0_tcstatus(tmp); | |
110 | ||
111 | write_tc_c0_tchalt(TCHALT_H); | |
112 | } | |
113 | ||
87353d8a | 114 | static void vsmp_send_ipi_single(int cpu, unsigned int action) |
340ee4b9 | 115 | { |
87353d8a RB |
116 | int i; |
117 | unsigned long flags; | |
118 | int vpflags; | |
340ee4b9 | 119 | |
87353d8a | 120 | local_irq_save(flags); |
340ee4b9 | 121 | |
25985edc | 122 | vpflags = dvpe(); /* can't access the other CPU's registers whilst MVPE enabled */ |
340ee4b9 | 123 | |
87353d8a RB |
124 | switch (action) { |
125 | case SMP_CALL_FUNCTION: | |
126 | i = C_SW1; | |
127 | break; | |
340ee4b9 | 128 | |
87353d8a RB |
129 | case SMP_RESCHEDULE_YOURSELF: |
130 | default: | |
131 | i = C_SW0; | |
132 | break; | |
133 | } | |
340ee4b9 | 134 | |
87353d8a RB |
135 | /* 1:1 mapping of vpe and tc... */ |
136 | settc(cpu); | |
137 | write_vpe_c0_cause(read_vpe_c0_cause() | i); | |
138 | evpe(vpflags); | |
0ab7aefc | 139 | |
87353d8a RB |
140 | local_irq_restore(flags); |
141 | } | |
340ee4b9 | 142 | |
48a048fe | 143 | static void vsmp_send_ipi_mask(const struct cpumask *mask, unsigned int action) |
87353d8a RB |
144 | { |
145 | unsigned int i; | |
340ee4b9 | 146 | |
48a048fe | 147 | for_each_cpu(i, mask) |
87353d8a RB |
148 | vsmp_send_ipi_single(i, action); |
149 | } | |
340ee4b9 | 150 | |
87353d8a RB |
151 | static void __cpuinit vsmp_init_secondary(void) |
152 | { | |
1c599242 | 153 | #ifdef CONFIG_IRQ_GIC |
39b8d525 | 154 | extern int gic_present; |
340ee4b9 | 155 | |
d002aaad | 156 | /* This is Malta specific: IPI,performance and timer interrupts */ |
39b8d525 RB |
157 | if (gic_present) |
158 | change_c0_status(ST0_IM, STATUSF_IP3 | STATUSF_IP4 | | |
159 | STATUSF_IP6 | STATUSF_IP7); | |
160 | else | |
1c599242 | 161 | #endif |
39b8d525 RB |
162 | change_c0_status(ST0_IM, STATUSF_IP0 | STATUSF_IP1 | |
163 | STATUSF_IP6 | STATUSF_IP7); | |
41c594ab | 164 | } |
340ee4b9 | 165 | |
87353d8a | 166 | static void __cpuinit vsmp_smp_finish(void) |
41c594ab | 167 | { |
39b8d525 | 168 | /* CDFIXME: remove this? */ |
87353d8a | 169 | write_c0_compare(read_c0_count() + (8* mips_hpt_frequency/HZ)); |
340ee4b9 | 170 | |
87353d8a RB |
171 | #ifdef CONFIG_MIPS_MT_FPAFF |
172 | /* If we have an FPU, enroll ourselves in the FPU-full mask */ | |
173 | if (cpu_has_fpu) | |
174 | cpu_set(smp_processor_id(), mt_fpu_cpumask); | |
175 | #endif /* CONFIG_MIPS_MT_FPAFF */ | |
340ee4b9 | 176 | |
87353d8a RB |
177 | local_irq_enable(); |
178 | } | |
340ee4b9 | 179 | |
87353d8a RB |
180 | static void vsmp_cpus_done(void) |
181 | { | |
340ee4b9 RB |
182 | } |
183 | ||
184 | /* | |
185 | * Setup the PC, SP, and GP of a secondary processor and start it | |
186 | * running! | |
187 | * smp_bootstrap is the place to resume from | |
188 | * __KSTK_TOS(idle) is apparently the stack pointer | |
189 | * (unsigned long)idle->thread_info the gp | |
190 | * assumes a 1:1 mapping of TC => VPE | |
191 | */ | |
87353d8a | 192 | static void __cpuinit vsmp_boot_secondary(int cpu, struct task_struct *idle) |
340ee4b9 | 193 | { |
dc8f6029 | 194 | struct thread_info *gp = task_thread_info(idle); |
340ee4b9 RB |
195 | dvpe(); |
196 | set_c0_mvpcontrol(MVPCONTROL_VPC); | |
197 | ||
198 | settc(cpu); | |
199 | ||
200 | /* restart */ | |
201 | write_tc_c0_tcrestart((unsigned long)&smp_bootstrap); | |
202 | ||
203 | /* enable the tc this vpe/cpu will be running */ | |
204 | write_tc_c0_tcstatus((read_tc_c0_tcstatus() & ~TCSTATUS_IXMT) | TCSTATUS_A); | |
205 | ||
206 | write_tc_c0_tchalt(0); | |
207 | ||
208 | /* enable the VPE */ | |
209 | write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() | VPECONF0_VPA); | |
210 | ||
211 | /* stack pointer */ | |
212 | write_tc_gpr_sp( __KSTK_TOS(idle)); | |
213 | ||
214 | /* global pointer */ | |
dc8f6029 | 215 | write_tc_gpr_gp((unsigned long)gp); |
340ee4b9 | 216 | |
41c594ab RB |
217 | flush_icache_range((unsigned long)gp, |
218 | (unsigned long)(gp + sizeof(struct thread_info))); | |
340ee4b9 RB |
219 | |
220 | /* finally out of configuration and into chaos */ | |
221 | clear_c0_mvpcontrol(MVPCONTROL_VPC); | |
222 | ||
223 | evpe(EVPE_ENABLE); | |
224 | } | |
225 | ||
87353d8a RB |
226 | /* |
227 | * Common setup before any secondaries are started | |
228 | * Make sure all CPU's are in a sensible state before we boot any of the | |
39b8d525 | 229 | * secondaries |
87353d8a RB |
230 | */ |
231 | static void __init vsmp_smp_setup(void) | |
340ee4b9 | 232 | { |
87353d8a RB |
233 | unsigned int mvpconf0, ntc, tc, ncpu = 0; |
234 | unsigned int nvpe; | |
340ee4b9 | 235 | |
f088fc84 RB |
236 | #ifdef CONFIG_MIPS_MT_FPAFF |
237 | /* If we have an FPU, enroll ourselves in the FPU-full mask */ | |
238 | if (cpu_has_fpu) | |
87353d8a | 239 | cpu_set(0, mt_fpu_cpumask); |
f088fc84 | 240 | #endif /* CONFIG_MIPS_MT_FPAFF */ |
87353d8a RB |
241 | if (!cpu_has_mipsmt) |
242 | return; | |
f088fc84 | 243 | |
87353d8a RB |
244 | /* disable MT so we can configure */ |
245 | dvpe(); | |
246 | dmt(); | |
340ee4b9 | 247 | |
87353d8a RB |
248 | /* Put MVPE's into 'configuration state' */ |
249 | set_c0_mvpcontrol(MVPCONTROL_VPC); | |
340ee4b9 | 250 | |
87353d8a RB |
251 | mvpconf0 = read_c0_mvpconf0(); |
252 | ntc = (mvpconf0 & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT; | |
340ee4b9 | 253 | |
87353d8a RB |
254 | nvpe = ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1; |
255 | smp_num_siblings = nvpe; | |
340ee4b9 | 256 | |
87353d8a RB |
257 | /* we'll always have more TC's than VPE's, so loop setting everything |
258 | to a sensible state */ | |
259 | for (tc = 0; tc <= ntc; tc++) { | |
260 | settc(tc); | |
340ee4b9 | 261 | |
39b8d525 RB |
262 | smvp_tc_init(tc, mvpconf0); |
263 | ncpu = smvp_vpe_init(tc, mvpconf0, ncpu); | |
87353d8a | 264 | } |
340ee4b9 | 265 | |
87353d8a RB |
266 | /* Release config state */ |
267 | clear_c0_mvpcontrol(MVPCONTROL_VPC); | |
268 | ||
269 | /* We'll wait until starting the secondaries before starting MVPE */ | |
270 | ||
271 | printk(KERN_INFO "Detected %i available secondary CPU(s)\n", ncpu); | |
272 | } | |
273 | ||
274 | static void __init vsmp_prepare_cpus(unsigned int max_cpus) | |
275 | { | |
276 | mips_mt_set_cpuoptions(); | |
340ee4b9 | 277 | } |
87353d8a RB |
278 | |
279 | struct plat_smp_ops vsmp_smp_ops = { | |
280 | .send_ipi_single = vsmp_send_ipi_single, | |
281 | .send_ipi_mask = vsmp_send_ipi_mask, | |
282 | .init_secondary = vsmp_init_secondary, | |
283 | .smp_finish = vsmp_smp_finish, | |
284 | .cpus_done = vsmp_cpus_done, | |
285 | .boot_secondary = vsmp_boot_secondary, | |
286 | .smp_setup = vsmp_smp_setup, | |
287 | .prepare_cpus = vsmp_prepare_cpus, | |
288 | }; |