Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * This program is free software; you can redistribute it and/or | |
3 | * modify it under the terms of the GNU General Public License | |
4 | * as published by the Free Software Foundation; either version 2 | |
5 | * of the License, or (at your option) any later version. | |
6 | * | |
7 | * This program is distributed in the hope that it will be useful, | |
8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
10 | * GNU General Public License for more details. | |
11 | * | |
12 | * You should have received a copy of the GNU General Public License | |
13 | * along with this program; if not, write to the Free Software | |
14 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
15 | * | |
16 | * Copyright (C) 2000, 2001 Kanoj Sarcar | |
17 | * Copyright (C) 2000, 2001 Ralf Baechle | |
18 | * Copyright (C) 2000, 2001 Silicon Graphics, Inc. | |
19 | * Copyright (C) 2000, 2001, 2003 Broadcom Corporation | |
20 | */ | |
21 | #include <linux/cache.h> | |
22 | #include <linux/delay.h> | |
23 | #include <linux/init.h> | |
24 | #include <linux/interrupt.h> | |
631330f5 | 25 | #include <linux/smp.h> |
1da177e4 LT |
26 | #include <linux/spinlock.h> |
27 | #include <linux/threads.h> | |
28 | #include <linux/module.h> | |
29 | #include <linux/time.h> | |
30 | #include <linux/timex.h> | |
31 | #include <linux/sched.h> | |
32 | #include <linux/cpumask.h> | |
1e35aaba | 33 | #include <linux/cpu.h> |
4e950f6f | 34 | #include <linux/err.h> |
8f99a162 | 35 | #include <linux/ftrace.h> |
1da177e4 | 36 | |
60063497 | 37 | #include <linux/atomic.h> |
1da177e4 LT |
38 | #include <asm/cpu.h> |
39 | #include <asm/processor.h> | |
39b8d525 | 40 | #include <asm/r4k-timer.h> |
1da177e4 | 41 | #include <asm/mmu_context.h> |
7bcf7717 | 42 | #include <asm/time.h> |
b81947c6 | 43 | #include <asm/setup.h> |
1da177e4 | 44 | |
41c594ab RB |
45 | #ifdef CONFIG_MIPS_MT_SMTC |
46 | #include <asm/mipsmtregs.h> | |
47 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
48 | ||
1b2bc75c | 49 | volatile cpumask_t cpu_callin_map; /* Bitmask of started secondaries */ |
2dc2ae34 | 50 | |
1da177e4 | 51 | int __cpu_number_map[NR_CPUS]; /* Map physical to logical */ |
2dc2ae34 DD |
52 | EXPORT_SYMBOL(__cpu_number_map); |
53 | ||
1da177e4 | 54 | int __cpu_logical_map[NR_CPUS]; /* Map logical to physical */ |
2dc2ae34 | 55 | EXPORT_SYMBOL(__cpu_logical_map); |
1da177e4 | 56 | |
0ab7aefc RB |
57 | /* Number of TCs (or siblings in Intel speak) per CPU core */ |
58 | int smp_num_siblings = 1; | |
59 | EXPORT_SYMBOL(smp_num_siblings); | |
60 | ||
61 | /* representing the TCs (or siblings in Intel speak) of each logical CPU */ | |
62 | cpumask_t cpu_sibling_map[NR_CPUS] __read_mostly; | |
63 | EXPORT_SYMBOL(cpu_sibling_map); | |
64 | ||
65 | /* representing cpus for which sibling maps can be computed */ | |
66 | static cpumask_t cpu_sibling_setup_map; | |
67 | ||
68 | static inline void set_cpu_sibling_map(int cpu) | |
69 | { | |
70 | int i; | |
71 | ||
72 | cpu_set(cpu, cpu_sibling_setup_map); | |
73 | ||
74 | if (smp_num_siblings > 1) { | |
75 | for_each_cpu_mask(i, cpu_sibling_setup_map) { | |
76 | if (cpu_data[cpu].core == cpu_data[i].core) { | |
77 | cpu_set(i, cpu_sibling_map[cpu]); | |
78 | cpu_set(cpu, cpu_sibling_map[i]); | |
79 | } | |
80 | } | |
81 | } else | |
82 | cpu_set(cpu, cpu_sibling_map[cpu]); | |
83 | } | |
84 | ||
87353d8a RB |
85 | struct plat_smp_ops *mp_ops; |
86 | ||
87 | __cpuinit void register_smp_ops(struct plat_smp_ops *ops) | |
88 | { | |
83738e30 TS |
89 | if (mp_ops) |
90 | printk(KERN_WARNING "Overriding previously set SMP ops\n"); | |
87353d8a RB |
91 | |
92 | mp_ops = ops; | |
93 | } | |
94 | ||
1da177e4 LT |
95 | /* |
96 | * First C code run on the secondary CPUs after being started up by | |
97 | * the master. | |
98 | */ | |
4ebd5233 | 99 | asmlinkage __cpuinit void start_secondary(void) |
1da177e4 | 100 | { |
5bfb5d69 | 101 | unsigned int cpu; |
1da177e4 | 102 | |
41c594ab RB |
103 | #ifdef CONFIG_MIPS_MT_SMTC |
104 | /* Only do cpu_probe for first TC of CPU */ | |
105 | if ((read_c0_tcbind() & TCBIND_CURTC) == 0) | |
106 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
1da177e4 LT |
107 | cpu_probe(); |
108 | cpu_report(); | |
109 | per_cpu_trap_init(); | |
7bcf7717 | 110 | mips_clockevent_init(); |
87353d8a | 111 | mp_ops->init_secondary(); |
1da177e4 LT |
112 | |
113 | /* | |
114 | * XXX parity protection should be folded in here when it's converted | |
115 | * to an option instead of something based on .cputype | |
116 | */ | |
117 | ||
118 | calibrate_delay(); | |
5bfb5d69 NP |
119 | preempt_disable(); |
120 | cpu = smp_processor_id(); | |
1da177e4 LT |
121 | cpu_data[cpu].udelay_val = loops_per_jiffy; |
122 | ||
e545a614 MS |
123 | notify_cpu_starting(cpu); |
124 | ||
87353d8a | 125 | mp_ops->smp_finish(); |
0ab7aefc | 126 | set_cpu_sibling_map(cpu); |
1da177e4 LT |
127 | |
128 | cpu_set(cpu, cpu_callin_map); | |
129 | ||
39b8d525 RB |
130 | synchronise_count_slave(); |
131 | ||
1da177e4 LT |
132 | cpu_idle(); |
133 | } | |
134 | ||
2f304c0a JA |
135 | /* |
136 | * Call into both interrupt handlers, as we share the IPI for them | |
137 | */ | |
8f99a162 | 138 | void __irq_entry smp_call_function_interrupt(void) |
1da177e4 | 139 | { |
1da177e4 | 140 | irq_enter(); |
2f304c0a JA |
141 | generic_smp_call_function_single_interrupt(); |
142 | generic_smp_call_function_interrupt(); | |
1da177e4 | 143 | irq_exit(); |
b4b2917c PW |
144 | } |
145 | ||
1da177e4 LT |
146 | static void stop_this_cpu(void *dummy) |
147 | { | |
148 | /* | |
149 | * Remove this CPU: | |
150 | */ | |
0b5f9c00 | 151 | set_cpu_online(smp_processor_id(), false); |
7920c4d6 RB |
152 | for (;;) { |
153 | if (cpu_wait) | |
154 | (*cpu_wait)(); /* Wait if available. */ | |
155 | } | |
1da177e4 LT |
156 | } |
157 | ||
158 | void smp_send_stop(void) | |
159 | { | |
8691e5a8 | 160 | smp_call_function(stop_this_cpu, NULL, 0); |
1da177e4 LT |
161 | } |
162 | ||
163 | void __init smp_cpus_done(unsigned int max_cpus) | |
164 | { | |
87353d8a | 165 | mp_ops->cpus_done(); |
39b8d525 | 166 | synchronise_count_master(); |
1da177e4 LT |
167 | } |
168 | ||
169 | /* called from main before smp_init() */ | |
170 | void __init smp_prepare_cpus(unsigned int max_cpus) | |
171 | { | |
1da177e4 LT |
172 | init_new_context(current, &init_mm); |
173 | current_thread_info()->cpu = 0; | |
87353d8a | 174 | mp_ops->prepare_cpus(max_cpus); |
0ab7aefc | 175 | set_cpu_sibling_map(0); |
320e6aba | 176 | #ifndef CONFIG_HOTPLUG_CPU |
0b5f9c00 | 177 | init_cpu_present(cpu_possible_mask); |
320e6aba | 178 | #endif |
1da177e4 LT |
179 | } |
180 | ||
181 | /* preload SMP state for boot cpu */ | |
182 | void __devinit smp_prepare_boot_cpu(void) | |
183 | { | |
4037ac6e RR |
184 | set_cpu_possible(0, true); |
185 | set_cpu_online(0, true); | |
1da177e4 LT |
186 | cpu_set(0, cpu_callin_map); |
187 | } | |
188 | ||
189 | /* | |
b727a602 RB |
190 | * Called once for each "cpu_possible(cpu)". Needs to spin up the cpu |
191 | * and keep control until "cpu_online(cpu)" is set. Note: cpu is | |
192 | * physical, not logical. | |
1da177e4 | 193 | */ |
1b2bc75c RB |
194 | static struct task_struct *cpu_idle_thread[NR_CPUS]; |
195 | ||
6667deb6 MR |
196 | struct create_idle { |
197 | struct work_struct work; | |
198 | struct task_struct *idle; | |
199 | struct completion done; | |
200 | int cpu; | |
201 | }; | |
202 | ||
203 | static void __cpuinit do_fork_idle(struct work_struct *work) | |
204 | { | |
205 | struct create_idle *c_idle = | |
206 | container_of(work, struct create_idle, work); | |
207 | ||
208 | c_idle->idle = fork_idle(c_idle->cpu); | |
209 | complete(&c_idle->done); | |
210 | } | |
211 | ||
8239c25f | 212 | int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *tidle) |
1da177e4 LT |
213 | { |
214 | struct task_struct *idle; | |
215 | ||
216 | /* | |
b727a602 | 217 | * Processor goes to start_secondary(), sets online flag |
1da177e4 LT |
218 | * The following code is purely to make sure |
219 | * Linux can schedule processes on this slave. | |
220 | */ | |
1b2bc75c | 221 | if (!cpu_idle_thread[cpu]) { |
6667deb6 MR |
222 | /* |
223 | * Schedule work item to avoid forking user task | |
224 | * Ported from arch/x86/kernel/smpboot.c | |
225 | */ | |
226 | struct create_idle c_idle = { | |
227 | .cpu = cpu, | |
228 | .done = COMPLETION_INITIALIZER_ONSTACK(c_idle.done), | |
229 | }; | |
230 | ||
231 | INIT_WORK_ONSTACK(&c_idle.work, do_fork_idle); | |
232 | schedule_work(&c_idle.work); | |
233 | wait_for_completion(&c_idle.done); | |
234 | idle = cpu_idle_thread[cpu] = c_idle.idle; | |
1b2bc75c RB |
235 | |
236 | if (IS_ERR(idle)) | |
237 | panic(KERN_ERR "Fork failed for CPU %d", cpu); | |
238 | } else { | |
239 | idle = cpu_idle_thread[cpu]; | |
240 | init_idle(idle, cpu); | |
241 | } | |
1da177e4 | 242 | |
87353d8a | 243 | mp_ops->boot_secondary(cpu, idle); |
1da177e4 | 244 | |
b727a602 RB |
245 | /* |
246 | * Trust is futile. We should really have timeouts ... | |
247 | */ | |
1da177e4 LT |
248 | while (!cpu_isset(cpu, cpu_callin_map)) |
249 | udelay(100); | |
250 | ||
0b5f9c00 | 251 | set_cpu_online(cpu, true); |
1da177e4 LT |
252 | |
253 | return 0; | |
254 | } | |
255 | ||
1da177e4 LT |
256 | /* Not really SMP stuff ... */ |
257 | int setup_profiling_timer(unsigned int multiplier) | |
258 | { | |
259 | return 0; | |
260 | } | |
261 | ||
262 | static void flush_tlb_all_ipi(void *info) | |
263 | { | |
264 | local_flush_tlb_all(); | |
265 | } | |
266 | ||
267 | void flush_tlb_all(void) | |
268 | { | |
15c8b6c1 | 269 | on_each_cpu(flush_tlb_all_ipi, NULL, 1); |
1da177e4 LT |
270 | } |
271 | ||
272 | static void flush_tlb_mm_ipi(void *mm) | |
273 | { | |
274 | local_flush_tlb_mm((struct mm_struct *)mm); | |
275 | } | |
276 | ||
25969354 RB |
277 | /* |
278 | * Special Variant of smp_call_function for use by TLB functions: | |
279 | * | |
280 | * o No return value | |
281 | * o collapses to normal function call on UP kernels | |
282 | * o collapses to normal function call on systems with a single shared | |
283 | * primary cache. | |
284 | * o CONFIG_MIPS_MT_SMTC currently implies there is only one physical core. | |
285 | */ | |
286 | static inline void smp_on_other_tlbs(void (*func) (void *info), void *info) | |
287 | { | |
288 | #ifndef CONFIG_MIPS_MT_SMTC | |
8691e5a8 | 289 | smp_call_function(func, info, 1); |
25969354 RB |
290 | #endif |
291 | } | |
292 | ||
293 | static inline void smp_on_each_tlb(void (*func) (void *info), void *info) | |
294 | { | |
295 | preempt_disable(); | |
296 | ||
297 | smp_on_other_tlbs(func, info); | |
298 | func(info); | |
299 | ||
300 | preempt_enable(); | |
301 | } | |
302 | ||
1da177e4 LT |
303 | /* |
304 | * The following tlb flush calls are invoked when old translations are | |
305 | * being torn down, or pte attributes are changing. For single threaded | |
306 | * address spaces, a new context is obtained on the current cpu, and tlb | |
307 | * context on other cpus are invalidated to force a new context allocation | |
308 | * at switch_mm time, should the mm ever be used on other cpus. For | |
309 | * multithreaded address spaces, intercpu interrupts have to be sent. | |
310 | * Another case where intercpu interrupts are required is when the target | |
311 | * mm might be active on another cpu (eg debuggers doing the flushes on | |
312 | * behalf of debugees, kswapd stealing pages from another process etc). | |
313 | * Kanoj 07/00. | |
314 | */ | |
315 | ||
316 | void flush_tlb_mm(struct mm_struct *mm) | |
317 | { | |
318 | preempt_disable(); | |
319 | ||
320 | if ((atomic_read(&mm->mm_users) != 1) || (current->mm != mm)) { | |
c50cade9 | 321 | smp_on_other_tlbs(flush_tlb_mm_ipi, mm); |
1da177e4 | 322 | } else { |
b5eb5511 RB |
323 | unsigned int cpu; |
324 | ||
0b5f9c00 RR |
325 | for_each_online_cpu(cpu) { |
326 | if (cpu != smp_processor_id() && cpu_context(cpu, mm)) | |
b5eb5511 | 327 | cpu_context(cpu, mm) = 0; |
0b5f9c00 | 328 | } |
1da177e4 LT |
329 | } |
330 | local_flush_tlb_mm(mm); | |
331 | ||
332 | preempt_enable(); | |
333 | } | |
334 | ||
335 | struct flush_tlb_data { | |
336 | struct vm_area_struct *vma; | |
337 | unsigned long addr1; | |
338 | unsigned long addr2; | |
339 | }; | |
340 | ||
341 | static void flush_tlb_range_ipi(void *info) | |
342 | { | |
c50cade9 | 343 | struct flush_tlb_data *fd = info; |
1da177e4 LT |
344 | |
345 | local_flush_tlb_range(fd->vma, fd->addr1, fd->addr2); | |
346 | } | |
347 | ||
348 | void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end) | |
349 | { | |
350 | struct mm_struct *mm = vma->vm_mm; | |
351 | ||
352 | preempt_disable(); | |
353 | if ((atomic_read(&mm->mm_users) != 1) || (current->mm != mm)) { | |
89a8a5a6 RB |
354 | struct flush_tlb_data fd = { |
355 | .vma = vma, | |
356 | .addr1 = start, | |
357 | .addr2 = end, | |
358 | }; | |
1da177e4 | 359 | |
c50cade9 | 360 | smp_on_other_tlbs(flush_tlb_range_ipi, &fd); |
1da177e4 | 361 | } else { |
b5eb5511 RB |
362 | unsigned int cpu; |
363 | ||
0b5f9c00 RR |
364 | for_each_online_cpu(cpu) { |
365 | if (cpu != smp_processor_id() && cpu_context(cpu, mm)) | |
b5eb5511 | 366 | cpu_context(cpu, mm) = 0; |
0b5f9c00 | 367 | } |
1da177e4 LT |
368 | } |
369 | local_flush_tlb_range(vma, start, end); | |
370 | preempt_enable(); | |
371 | } | |
372 | ||
373 | static void flush_tlb_kernel_range_ipi(void *info) | |
374 | { | |
c50cade9 | 375 | struct flush_tlb_data *fd = info; |
1da177e4 LT |
376 | |
377 | local_flush_tlb_kernel_range(fd->addr1, fd->addr2); | |
378 | } | |
379 | ||
380 | void flush_tlb_kernel_range(unsigned long start, unsigned long end) | |
381 | { | |
89a8a5a6 RB |
382 | struct flush_tlb_data fd = { |
383 | .addr1 = start, | |
384 | .addr2 = end, | |
385 | }; | |
1da177e4 | 386 | |
15c8b6c1 | 387 | on_each_cpu(flush_tlb_kernel_range_ipi, &fd, 1); |
1da177e4 LT |
388 | } |
389 | ||
390 | static void flush_tlb_page_ipi(void *info) | |
391 | { | |
c50cade9 | 392 | struct flush_tlb_data *fd = info; |
1da177e4 LT |
393 | |
394 | local_flush_tlb_page(fd->vma, fd->addr1); | |
395 | } | |
396 | ||
397 | void flush_tlb_page(struct vm_area_struct *vma, unsigned long page) | |
398 | { | |
399 | preempt_disable(); | |
400 | if ((atomic_read(&vma->vm_mm->mm_users) != 1) || (current->mm != vma->vm_mm)) { | |
89a8a5a6 RB |
401 | struct flush_tlb_data fd = { |
402 | .vma = vma, | |
403 | .addr1 = page, | |
404 | }; | |
1da177e4 | 405 | |
c50cade9 | 406 | smp_on_other_tlbs(flush_tlb_page_ipi, &fd); |
1da177e4 | 407 | } else { |
b5eb5511 RB |
408 | unsigned int cpu; |
409 | ||
0b5f9c00 RR |
410 | for_each_online_cpu(cpu) { |
411 | if (cpu != smp_processor_id() && cpu_context(cpu, vma->vm_mm)) | |
b5eb5511 | 412 | cpu_context(cpu, vma->vm_mm) = 0; |
0b5f9c00 | 413 | } |
1da177e4 LT |
414 | } |
415 | local_flush_tlb_page(vma, page); | |
416 | preempt_enable(); | |
417 | } | |
418 | ||
419 | static void flush_tlb_one_ipi(void *info) | |
420 | { | |
421 | unsigned long vaddr = (unsigned long) info; | |
422 | ||
423 | local_flush_tlb_one(vaddr); | |
424 | } | |
425 | ||
426 | void flush_tlb_one(unsigned long vaddr) | |
427 | { | |
25969354 | 428 | smp_on_each_tlb(flush_tlb_one_ipi, (void *) vaddr); |
1da177e4 LT |
429 | } |
430 | ||
431 | EXPORT_SYMBOL(flush_tlb_page); | |
432 | EXPORT_SYMBOL(flush_tlb_one); |