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1da177e4 LT |
1 | /* |
2 | * This program is free software; you can redistribute it and/or | |
3 | * modify it under the terms of the GNU General Public License | |
4 | * as published by the Free Software Foundation; either version 2 | |
5 | * of the License, or (at your option) any later version. | |
6 | * | |
7 | * This program is distributed in the hope that it will be useful, | |
8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
10 | * GNU General Public License for more details. | |
11 | * | |
12 | * You should have received a copy of the GNU General Public License | |
13 | * along with this program; if not, write to the Free Software | |
14 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
15 | * | |
16 | * Copyright (C) 2000, 2001 Kanoj Sarcar | |
17 | * Copyright (C) 2000, 2001 Ralf Baechle | |
18 | * Copyright (C) 2000, 2001 Silicon Graphics, Inc. | |
19 | * Copyright (C) 2000, 2001, 2003 Broadcom Corporation | |
20 | */ | |
21 | #include <linux/cache.h> | |
22 | #include <linux/delay.h> | |
23 | #include <linux/init.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/spinlock.h> | |
26 | #include <linux/threads.h> | |
27 | #include <linux/module.h> | |
28 | #include <linux/time.h> | |
29 | #include <linux/timex.h> | |
30 | #include <linux/sched.h> | |
31 | #include <linux/cpumask.h> | |
1e35aaba | 32 | #include <linux/cpu.h> |
4e950f6f | 33 | #include <linux/err.h> |
1da177e4 LT |
34 | |
35 | #include <asm/atomic.h> | |
36 | #include <asm/cpu.h> | |
37 | #include <asm/processor.h> | |
39b8d525 | 38 | #include <asm/r4k-timer.h> |
1da177e4 LT |
39 | #include <asm/system.h> |
40 | #include <asm/mmu_context.h> | |
7bcf7717 | 41 | #include <asm/time.h> |
1da177e4 | 42 | |
41c594ab RB |
43 | #ifdef CONFIG_MIPS_MT_SMTC |
44 | #include <asm/mipsmtregs.h> | |
45 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
46 | ||
1da177e4 LT |
47 | cpumask_t phys_cpu_present_map; /* Bitmask of available CPUs */ |
48 | volatile cpumask_t cpu_callin_map; /* Bitmask of started secondaries */ | |
49 | cpumask_t cpu_online_map; /* Bitmask of currently online CPUs */ | |
50 | int __cpu_number_map[NR_CPUS]; /* Map physical to logical */ | |
51 | int __cpu_logical_map[NR_CPUS]; /* Map logical to physical */ | |
52 | ||
53 | EXPORT_SYMBOL(phys_cpu_present_map); | |
54 | EXPORT_SYMBOL(cpu_online_map); | |
55 | ||
b3f6df9f | 56 | extern void cpu_idle(void); |
1da177e4 | 57 | |
0ab7aefc RB |
58 | /* Number of TCs (or siblings in Intel speak) per CPU core */ |
59 | int smp_num_siblings = 1; | |
60 | EXPORT_SYMBOL(smp_num_siblings); | |
61 | ||
62 | /* representing the TCs (or siblings in Intel speak) of each logical CPU */ | |
63 | cpumask_t cpu_sibling_map[NR_CPUS] __read_mostly; | |
64 | EXPORT_SYMBOL(cpu_sibling_map); | |
65 | ||
66 | /* representing cpus for which sibling maps can be computed */ | |
67 | static cpumask_t cpu_sibling_setup_map; | |
68 | ||
69 | static inline void set_cpu_sibling_map(int cpu) | |
70 | { | |
71 | int i; | |
72 | ||
73 | cpu_set(cpu, cpu_sibling_setup_map); | |
74 | ||
75 | if (smp_num_siblings > 1) { | |
76 | for_each_cpu_mask(i, cpu_sibling_setup_map) { | |
77 | if (cpu_data[cpu].core == cpu_data[i].core) { | |
78 | cpu_set(i, cpu_sibling_map[cpu]); | |
79 | cpu_set(cpu, cpu_sibling_map[i]); | |
80 | } | |
81 | } | |
82 | } else | |
83 | cpu_set(cpu, cpu_sibling_map[cpu]); | |
84 | } | |
85 | ||
87353d8a RB |
86 | struct plat_smp_ops *mp_ops; |
87 | ||
88 | __cpuinit void register_smp_ops(struct plat_smp_ops *ops) | |
89 | { | |
83738e30 TS |
90 | if (mp_ops) |
91 | printk(KERN_WARNING "Overriding previously set SMP ops\n"); | |
87353d8a RB |
92 | |
93 | mp_ops = ops; | |
94 | } | |
95 | ||
1da177e4 LT |
96 | /* |
97 | * First C code run on the secondary CPUs after being started up by | |
98 | * the master. | |
99 | */ | |
4ebd5233 | 100 | asmlinkage __cpuinit void start_secondary(void) |
1da177e4 | 101 | { |
5bfb5d69 | 102 | unsigned int cpu; |
1da177e4 | 103 | |
41c594ab RB |
104 | #ifdef CONFIG_MIPS_MT_SMTC |
105 | /* Only do cpu_probe for first TC of CPU */ | |
106 | if ((read_c0_tcbind() & TCBIND_CURTC) == 0) | |
107 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
1da177e4 LT |
108 | cpu_probe(); |
109 | cpu_report(); | |
110 | per_cpu_trap_init(); | |
7bcf7717 | 111 | mips_clockevent_init(); |
87353d8a | 112 | mp_ops->init_secondary(); |
1da177e4 LT |
113 | |
114 | /* | |
115 | * XXX parity protection should be folded in here when it's converted | |
116 | * to an option instead of something based on .cputype | |
117 | */ | |
118 | ||
119 | calibrate_delay(); | |
5bfb5d69 NP |
120 | preempt_disable(); |
121 | cpu = smp_processor_id(); | |
1da177e4 LT |
122 | cpu_data[cpu].udelay_val = loops_per_jiffy; |
123 | ||
e545a614 MS |
124 | notify_cpu_starting(cpu); |
125 | ||
87353d8a | 126 | mp_ops->smp_finish(); |
0ab7aefc | 127 | set_cpu_sibling_map(cpu); |
1da177e4 LT |
128 | |
129 | cpu_set(cpu, cpu_callin_map); | |
130 | ||
39b8d525 RB |
131 | synchronise_count_slave(); |
132 | ||
1da177e4 LT |
133 | cpu_idle(); |
134 | } | |
135 | ||
2f304c0a | 136 | void arch_send_call_function_ipi(cpumask_t mask) |
1da177e4 | 137 | { |
87353d8a | 138 | mp_ops->send_ipi_mask(mask, SMP_CALL_FUNCTION); |
1da177e4 LT |
139 | } |
140 | ||
2f304c0a JA |
141 | /* |
142 | * We reuse the same vector for the single IPI | |
143 | */ | |
144 | void arch_send_call_function_single_ipi(int cpu) | |
bd6aeeff | 145 | { |
2f304c0a | 146 | mp_ops->send_ipi_mask(cpumask_of_cpu(cpu), SMP_CALL_FUNCTION); |
bd6aeeff | 147 | } |
41c594ab | 148 | |
2f304c0a JA |
149 | /* |
150 | * Call into both interrupt handlers, as we share the IPI for them | |
151 | */ | |
1da177e4 LT |
152 | void smp_call_function_interrupt(void) |
153 | { | |
1da177e4 | 154 | irq_enter(); |
2f304c0a JA |
155 | generic_smp_call_function_single_interrupt(); |
156 | generic_smp_call_function_interrupt(); | |
1da177e4 | 157 | irq_exit(); |
b4b2917c PW |
158 | } |
159 | ||
1da177e4 LT |
160 | static void stop_this_cpu(void *dummy) |
161 | { | |
162 | /* | |
163 | * Remove this CPU: | |
164 | */ | |
165 | cpu_clear(smp_processor_id(), cpu_online_map); | |
166 | local_irq_enable(); /* May need to service _machine_restart IPI */ | |
167 | for (;;); /* Wait if available. */ | |
168 | } | |
169 | ||
170 | void smp_send_stop(void) | |
171 | { | |
8691e5a8 | 172 | smp_call_function(stop_this_cpu, NULL, 0); |
1da177e4 LT |
173 | } |
174 | ||
175 | void __init smp_cpus_done(unsigned int max_cpus) | |
176 | { | |
87353d8a | 177 | mp_ops->cpus_done(); |
39b8d525 | 178 | synchronise_count_master(); |
1da177e4 LT |
179 | } |
180 | ||
181 | /* called from main before smp_init() */ | |
182 | void __init smp_prepare_cpus(unsigned int max_cpus) | |
183 | { | |
1da177e4 LT |
184 | init_new_context(current, &init_mm); |
185 | current_thread_info()->cpu = 0; | |
87353d8a | 186 | mp_ops->prepare_cpus(max_cpus); |
0ab7aefc | 187 | set_cpu_sibling_map(0); |
320e6aba RB |
188 | #ifndef CONFIG_HOTPLUG_CPU |
189 | cpu_present_map = cpu_possible_map; | |
190 | #endif | |
1da177e4 LT |
191 | } |
192 | ||
193 | /* preload SMP state for boot cpu */ | |
194 | void __devinit smp_prepare_boot_cpu(void) | |
195 | { | |
196 | /* | |
197 | * This assumes that bootup is always handled by the processor | |
198 | * with the logic and physical number 0. | |
199 | */ | |
200 | __cpu_number_map[0] = 0; | |
201 | __cpu_logical_map[0] = 0; | |
202 | cpu_set(0, phys_cpu_present_map); | |
203 | cpu_set(0, cpu_online_map); | |
204 | cpu_set(0, cpu_callin_map); | |
205 | } | |
206 | ||
207 | /* | |
b727a602 RB |
208 | * Called once for each "cpu_possible(cpu)". Needs to spin up the cpu |
209 | * and keep control until "cpu_online(cpu)" is set. Note: cpu is | |
210 | * physical, not logical. | |
1da177e4 | 211 | */ |
b282b6f8 | 212 | int __cpuinit __cpu_up(unsigned int cpu) |
1da177e4 LT |
213 | { |
214 | struct task_struct *idle; | |
215 | ||
216 | /* | |
b727a602 | 217 | * Processor goes to start_secondary(), sets online flag |
1da177e4 LT |
218 | * The following code is purely to make sure |
219 | * Linux can schedule processes on this slave. | |
220 | */ | |
221 | idle = fork_idle(cpu); | |
222 | if (IS_ERR(idle)) | |
b727a602 | 223 | panic(KERN_ERR "Fork failed for CPU %d", cpu); |
1da177e4 | 224 | |
87353d8a | 225 | mp_ops->boot_secondary(cpu, idle); |
1da177e4 | 226 | |
b727a602 RB |
227 | /* |
228 | * Trust is futile. We should really have timeouts ... | |
229 | */ | |
1da177e4 LT |
230 | while (!cpu_isset(cpu, cpu_callin_map)) |
231 | udelay(100); | |
232 | ||
233 | cpu_set(cpu, cpu_online_map); | |
234 | ||
235 | return 0; | |
236 | } | |
237 | ||
1da177e4 LT |
238 | /* Not really SMP stuff ... */ |
239 | int setup_profiling_timer(unsigned int multiplier) | |
240 | { | |
241 | return 0; | |
242 | } | |
243 | ||
244 | static void flush_tlb_all_ipi(void *info) | |
245 | { | |
246 | local_flush_tlb_all(); | |
247 | } | |
248 | ||
249 | void flush_tlb_all(void) | |
250 | { | |
15c8b6c1 | 251 | on_each_cpu(flush_tlb_all_ipi, NULL, 1); |
1da177e4 LT |
252 | } |
253 | ||
254 | static void flush_tlb_mm_ipi(void *mm) | |
255 | { | |
256 | local_flush_tlb_mm((struct mm_struct *)mm); | |
257 | } | |
258 | ||
25969354 RB |
259 | /* |
260 | * Special Variant of smp_call_function for use by TLB functions: | |
261 | * | |
262 | * o No return value | |
263 | * o collapses to normal function call on UP kernels | |
264 | * o collapses to normal function call on systems with a single shared | |
265 | * primary cache. | |
266 | * o CONFIG_MIPS_MT_SMTC currently implies there is only one physical core. | |
267 | */ | |
268 | static inline void smp_on_other_tlbs(void (*func) (void *info), void *info) | |
269 | { | |
270 | #ifndef CONFIG_MIPS_MT_SMTC | |
8691e5a8 | 271 | smp_call_function(func, info, 1); |
25969354 RB |
272 | #endif |
273 | } | |
274 | ||
275 | static inline void smp_on_each_tlb(void (*func) (void *info), void *info) | |
276 | { | |
277 | preempt_disable(); | |
278 | ||
279 | smp_on_other_tlbs(func, info); | |
280 | func(info); | |
281 | ||
282 | preempt_enable(); | |
283 | } | |
284 | ||
1da177e4 LT |
285 | /* |
286 | * The following tlb flush calls are invoked when old translations are | |
287 | * being torn down, or pte attributes are changing. For single threaded | |
288 | * address spaces, a new context is obtained on the current cpu, and tlb | |
289 | * context on other cpus are invalidated to force a new context allocation | |
290 | * at switch_mm time, should the mm ever be used on other cpus. For | |
291 | * multithreaded address spaces, intercpu interrupts have to be sent. | |
292 | * Another case where intercpu interrupts are required is when the target | |
293 | * mm might be active on another cpu (eg debuggers doing the flushes on | |
294 | * behalf of debugees, kswapd stealing pages from another process etc). | |
295 | * Kanoj 07/00. | |
296 | */ | |
297 | ||
298 | void flush_tlb_mm(struct mm_struct *mm) | |
299 | { | |
300 | preempt_disable(); | |
301 | ||
302 | if ((atomic_read(&mm->mm_users) != 1) || (current->mm != mm)) { | |
c50cade9 | 303 | smp_on_other_tlbs(flush_tlb_mm_ipi, mm); |
1da177e4 | 304 | } else { |
b5eb5511 RB |
305 | cpumask_t mask = cpu_online_map; |
306 | unsigned int cpu; | |
307 | ||
308 | cpu_clear(smp_processor_id(), mask); | |
ece8a9e4 | 309 | for_each_cpu_mask(cpu, mask) |
b5eb5511 RB |
310 | if (cpu_context(cpu, mm)) |
311 | cpu_context(cpu, mm) = 0; | |
1da177e4 LT |
312 | } |
313 | local_flush_tlb_mm(mm); | |
314 | ||
315 | preempt_enable(); | |
316 | } | |
317 | ||
318 | struct flush_tlb_data { | |
319 | struct vm_area_struct *vma; | |
320 | unsigned long addr1; | |
321 | unsigned long addr2; | |
322 | }; | |
323 | ||
324 | static void flush_tlb_range_ipi(void *info) | |
325 | { | |
c50cade9 | 326 | struct flush_tlb_data *fd = info; |
1da177e4 LT |
327 | |
328 | local_flush_tlb_range(fd->vma, fd->addr1, fd->addr2); | |
329 | } | |
330 | ||
331 | void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end) | |
332 | { | |
333 | struct mm_struct *mm = vma->vm_mm; | |
334 | ||
335 | preempt_disable(); | |
336 | if ((atomic_read(&mm->mm_users) != 1) || (current->mm != mm)) { | |
89a8a5a6 RB |
337 | struct flush_tlb_data fd = { |
338 | .vma = vma, | |
339 | .addr1 = start, | |
340 | .addr2 = end, | |
341 | }; | |
1da177e4 | 342 | |
c50cade9 | 343 | smp_on_other_tlbs(flush_tlb_range_ipi, &fd); |
1da177e4 | 344 | } else { |
b5eb5511 RB |
345 | cpumask_t mask = cpu_online_map; |
346 | unsigned int cpu; | |
347 | ||
348 | cpu_clear(smp_processor_id(), mask); | |
ece8a9e4 | 349 | for_each_cpu_mask(cpu, mask) |
b5eb5511 RB |
350 | if (cpu_context(cpu, mm)) |
351 | cpu_context(cpu, mm) = 0; | |
1da177e4 LT |
352 | } |
353 | local_flush_tlb_range(vma, start, end); | |
354 | preempt_enable(); | |
355 | } | |
356 | ||
357 | static void flush_tlb_kernel_range_ipi(void *info) | |
358 | { | |
c50cade9 | 359 | struct flush_tlb_data *fd = info; |
1da177e4 LT |
360 | |
361 | local_flush_tlb_kernel_range(fd->addr1, fd->addr2); | |
362 | } | |
363 | ||
364 | void flush_tlb_kernel_range(unsigned long start, unsigned long end) | |
365 | { | |
89a8a5a6 RB |
366 | struct flush_tlb_data fd = { |
367 | .addr1 = start, | |
368 | .addr2 = end, | |
369 | }; | |
1da177e4 | 370 | |
15c8b6c1 | 371 | on_each_cpu(flush_tlb_kernel_range_ipi, &fd, 1); |
1da177e4 LT |
372 | } |
373 | ||
374 | static void flush_tlb_page_ipi(void *info) | |
375 | { | |
c50cade9 | 376 | struct flush_tlb_data *fd = info; |
1da177e4 LT |
377 | |
378 | local_flush_tlb_page(fd->vma, fd->addr1); | |
379 | } | |
380 | ||
381 | void flush_tlb_page(struct vm_area_struct *vma, unsigned long page) | |
382 | { | |
383 | preempt_disable(); | |
384 | if ((atomic_read(&vma->vm_mm->mm_users) != 1) || (current->mm != vma->vm_mm)) { | |
89a8a5a6 RB |
385 | struct flush_tlb_data fd = { |
386 | .vma = vma, | |
387 | .addr1 = page, | |
388 | }; | |
1da177e4 | 389 | |
c50cade9 | 390 | smp_on_other_tlbs(flush_tlb_page_ipi, &fd); |
1da177e4 | 391 | } else { |
b5eb5511 RB |
392 | cpumask_t mask = cpu_online_map; |
393 | unsigned int cpu; | |
394 | ||
395 | cpu_clear(smp_processor_id(), mask); | |
ece8a9e4 | 396 | for_each_cpu_mask(cpu, mask) |
b5eb5511 RB |
397 | if (cpu_context(cpu, vma->vm_mm)) |
398 | cpu_context(cpu, vma->vm_mm) = 0; | |
1da177e4 LT |
399 | } |
400 | local_flush_tlb_page(vma, page); | |
401 | preempt_enable(); | |
402 | } | |
403 | ||
404 | static void flush_tlb_one_ipi(void *info) | |
405 | { | |
406 | unsigned long vaddr = (unsigned long) info; | |
407 | ||
408 | local_flush_tlb_one(vaddr); | |
409 | } | |
410 | ||
411 | void flush_tlb_one(unsigned long vaddr) | |
412 | { | |
25969354 | 413 | smp_on_each_tlb(flush_tlb_one_ipi, (void *) vaddr); |
1da177e4 LT |
414 | } |
415 | ||
416 | EXPORT_SYMBOL(flush_tlb_page); | |
417 | EXPORT_SYMBOL(flush_tlb_one); |