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41c594ab RB |
1 | /* Copyright (C) 2004 Mips Technologies, Inc */ |
2 | ||
3 | #include <linux/kernel.h> | |
4 | #include <linux/sched.h> | |
5 | #include <linux/cpumask.h> | |
6 | #include <linux/interrupt.h> | |
7 | ||
8 | #include <asm/cpu.h> | |
9 | #include <asm/processor.h> | |
10 | #include <asm/atomic.h> | |
11 | #include <asm/system.h> | |
12 | #include <asm/hardirq.h> | |
13 | #include <asm/hazards.h> | |
14 | #include <asm/mmu_context.h> | |
15 | #include <asm/smp.h> | |
16 | #include <asm/mipsregs.h> | |
17 | #include <asm/cacheflush.h> | |
18 | #include <asm/time.h> | |
19 | #include <asm/addrspace.h> | |
20 | #include <asm/smtc.h> | |
21 | #include <asm/smtc_ipi.h> | |
22 | #include <asm/smtc_proc.h> | |
23 | ||
24 | /* | |
25 | * This file should be built into the kernel only if CONFIG_MIPS_MT_SMTC is set. | |
26 | */ | |
27 | ||
28 | /* | |
29 | * MIPSCPU_INT_BASE is identically defined in both | |
30 | * asm-mips/mips-boards/maltaint.h and asm-mips/mips-boards/simint.h, | |
31 | * but as yet there's no properly organized include structure that | |
32 | * will ensure that the right *int.h file will be included for a | |
33 | * given platform build. | |
34 | */ | |
35 | ||
36 | #define MIPSCPU_INT_BASE 16 | |
37 | ||
38 | #define MIPS_CPU_IPI_IRQ 1 | |
39 | ||
40 | #define LOCK_MT_PRA() \ | |
41 | local_irq_save(flags); \ | |
42 | mtflags = dmt() | |
43 | ||
44 | #define UNLOCK_MT_PRA() \ | |
45 | emt(mtflags); \ | |
46 | local_irq_restore(flags) | |
47 | ||
48 | #define LOCK_CORE_PRA() \ | |
49 | local_irq_save(flags); \ | |
50 | mtflags = dvpe() | |
51 | ||
52 | #define UNLOCK_CORE_PRA() \ | |
53 | evpe(mtflags); \ | |
54 | local_irq_restore(flags) | |
55 | ||
56 | /* | |
57 | * Data structures purely associated with SMTC parallelism | |
58 | */ | |
59 | ||
60 | ||
61 | /* | |
62 | * Table for tracking ASIDs whose lifetime is prolonged. | |
63 | */ | |
64 | ||
65 | asiduse smtc_live_asid[MAX_SMTC_TLBS][MAX_SMTC_ASIDS]; | |
66 | ||
67 | /* | |
68 | * Clock interrupt "latch" buffers, per "CPU" | |
69 | */ | |
70 | ||
71 | unsigned int ipi_timer_latch[NR_CPUS]; | |
72 | ||
73 | /* | |
74 | * Number of InterProcessor Interupt (IPI) message buffers to allocate | |
75 | */ | |
76 | ||
77 | #define IPIBUF_PER_CPU 4 | |
78 | ||
79 | struct smtc_ipi_q IPIQ[NR_CPUS]; | |
80 | struct smtc_ipi_q freeIPIq; | |
81 | ||
82 | ||
83 | /* Forward declarations */ | |
84 | ||
937a8015 | 85 | void ipi_decode(struct smtc_ipi *); |
41c594ab RB |
86 | void post_direct_ipi(int cpu, struct smtc_ipi *pipi); |
87 | void setup_cross_vpe_interrupts(void); | |
88 | void init_smtc_stats(void); | |
89 | ||
90 | /* Global SMTC Status */ | |
91 | ||
92 | unsigned int smtc_status = 0; | |
93 | ||
94 | /* Boot command line configuration overrides */ | |
95 | ||
96 | static int vpelimit = 0; | |
97 | static int tclimit = 0; | |
98 | static int ipibuffers = 0; | |
99 | static int nostlb = 0; | |
100 | static int asidmask = 0; | |
101 | unsigned long smtc_asid_mask = 0xff; | |
102 | ||
103 | static int __init maxvpes(char *str) | |
104 | { | |
105 | get_option(&str, &vpelimit); | |
106 | return 1; | |
107 | } | |
108 | ||
109 | static int __init maxtcs(char *str) | |
110 | { | |
111 | get_option(&str, &tclimit); | |
112 | return 1; | |
113 | } | |
114 | ||
115 | static int __init ipibufs(char *str) | |
116 | { | |
117 | get_option(&str, &ipibuffers); | |
118 | return 1; | |
119 | } | |
120 | ||
121 | static int __init stlb_disable(char *s) | |
122 | { | |
123 | nostlb = 1; | |
124 | return 1; | |
125 | } | |
126 | ||
127 | static int __init asidmask_set(char *str) | |
128 | { | |
129 | get_option(&str, &asidmask); | |
4bf42d42 | 130 | switch (asidmask) { |
41c594ab RB |
131 | case 0x1: |
132 | case 0x3: | |
133 | case 0x7: | |
134 | case 0xf: | |
135 | case 0x1f: | |
136 | case 0x3f: | |
137 | case 0x7f: | |
138 | case 0xff: | |
139 | smtc_asid_mask = (unsigned long)asidmask; | |
140 | break; | |
141 | default: | |
142 | printk("ILLEGAL ASID mask 0x%x from command line\n", asidmask); | |
143 | } | |
144 | return 1; | |
145 | } | |
146 | ||
147 | __setup("maxvpes=", maxvpes); | |
148 | __setup("maxtcs=", maxtcs); | |
149 | __setup("ipibufs=", ipibufs); | |
150 | __setup("nostlb", stlb_disable); | |
151 | __setup("asidmask=", asidmask_set); | |
152 | ||
153 | /* Enable additional debug checks before going into CPU idle loop */ | |
154 | #define SMTC_IDLE_HOOK_DEBUG | |
155 | ||
156 | #ifdef SMTC_IDLE_HOOK_DEBUG | |
157 | ||
158 | static int hang_trig = 0; | |
159 | ||
160 | static int __init hangtrig_enable(char *s) | |
161 | { | |
162 | hang_trig = 1; | |
163 | return 1; | |
164 | } | |
165 | ||
166 | ||
167 | __setup("hangtrig", hangtrig_enable); | |
168 | ||
169 | #define DEFAULT_BLOCKED_IPI_LIMIT 32 | |
170 | ||
171 | static int timerq_limit = DEFAULT_BLOCKED_IPI_LIMIT; | |
172 | ||
173 | static int __init tintq(char *str) | |
174 | { | |
175 | get_option(&str, &timerq_limit); | |
176 | return 1; | |
177 | } | |
178 | ||
179 | __setup("tintq=", tintq); | |
180 | ||
181 | int imstuckcount[2][8]; | |
182 | /* vpemask represents IM/IE bits of per-VPE Status registers, low-to-high */ | |
183 | int vpemask[2][8] = {{0,1,1,0,0,0,0,1},{0,1,0,0,0,0,0,1}}; | |
184 | int tcnoprog[NR_CPUS]; | |
185 | static atomic_t idle_hook_initialized = {0}; | |
186 | static int clock_hang_reported[NR_CPUS]; | |
187 | ||
188 | #endif /* SMTC_IDLE_HOOK_DEBUG */ | |
189 | ||
190 | /* Initialize shared TLB - the should probably migrate to smtc_setup_cpus() */ | |
191 | ||
192 | void __init sanitize_tlb_entries(void) | |
193 | { | |
194 | printk("Deprecated sanitize_tlb_entries() invoked\n"); | |
195 | } | |
196 | ||
197 | ||
198 | /* | |
199 | * Configure shared TLB - VPC configuration bit must be set by caller | |
200 | */ | |
201 | ||
202 | void smtc_configure_tlb(void) | |
203 | { | |
204 | int i,tlbsiz,vpes; | |
205 | unsigned long mvpconf0; | |
206 | unsigned long config1val; | |
207 | ||
208 | /* Set up ASID preservation table */ | |
209 | for (vpes=0; vpes<MAX_SMTC_TLBS; vpes++) { | |
210 | for(i = 0; i < MAX_SMTC_ASIDS; i++) { | |
211 | smtc_live_asid[vpes][i] = 0; | |
212 | } | |
213 | } | |
214 | mvpconf0 = read_c0_mvpconf0(); | |
215 | ||
216 | if ((vpes = ((mvpconf0 & MVPCONF0_PVPE) | |
217 | >> MVPCONF0_PVPE_SHIFT) + 1) > 1) { | |
218 | /* If we have multiple VPEs, try to share the TLB */ | |
219 | if ((mvpconf0 & MVPCONF0_TLBS) && !nostlb) { | |
220 | /* | |
221 | * If TLB sizing is programmable, shared TLB | |
222 | * size is the total available complement. | |
223 | * Otherwise, we have to take the sum of all | |
224 | * static VPE TLB entries. | |
225 | */ | |
226 | if ((tlbsiz = ((mvpconf0 & MVPCONF0_PTLBE) | |
227 | >> MVPCONF0_PTLBE_SHIFT)) == 0) { | |
228 | /* | |
229 | * If there's more than one VPE, there had better | |
230 | * be more than one TC, because we need one to bind | |
231 | * to each VPE in turn to be able to read | |
232 | * its configuration state! | |
233 | */ | |
234 | settc(1); | |
235 | /* Stop the TC from doing anything foolish */ | |
236 | write_tc_c0_tchalt(TCHALT_H); | |
237 | mips_ihb(); | |
238 | /* No need to un-Halt - that happens later anyway */ | |
239 | for (i=0; i < vpes; i++) { | |
240 | write_tc_c0_tcbind(i); | |
241 | /* | |
242 | * To be 100% sure we're really getting the right | |
243 | * information, we exit the configuration state | |
244 | * and do an IHB after each rebinding. | |
245 | */ | |
246 | write_c0_mvpcontrol( | |
247 | read_c0_mvpcontrol() & ~ MVPCONTROL_VPC ); | |
248 | mips_ihb(); | |
249 | /* | |
250 | * Only count if the MMU Type indicated is TLB | |
251 | */ | |
4bf42d42 | 252 | if (((read_vpe_c0_config() & MIPS_CONF_MT) >> 7) == 1) { |
41c594ab RB |
253 | config1val = read_vpe_c0_config1(); |
254 | tlbsiz += ((config1val >> 25) & 0x3f) + 1; | |
255 | } | |
256 | ||
257 | /* Put core back in configuration state */ | |
258 | write_c0_mvpcontrol( | |
259 | read_c0_mvpcontrol() | MVPCONTROL_VPC ); | |
260 | mips_ihb(); | |
261 | } | |
262 | } | |
263 | write_c0_mvpcontrol(read_c0_mvpcontrol() | MVPCONTROL_STLB); | |
264 | ||
265 | /* | |
266 | * Setup kernel data structures to use software total, | |
267 | * rather than read the per-VPE Config1 value. The values | |
268 | * for "CPU 0" gets copied to all the other CPUs as part | |
269 | * of their initialization in smtc_cpu_setup(). | |
270 | */ | |
271 | ||
272 | tlbsiz = tlbsiz & 0x3f; /* MIPS32 limits TLB indices to 64 */ | |
273 | cpu_data[0].tlbsize = tlbsiz; | |
274 | smtc_status |= SMTC_TLB_SHARED; | |
275 | ||
276 | printk("TLB of %d entry pairs shared by %d VPEs\n", | |
277 | tlbsiz, vpes); | |
278 | } else { | |
279 | printk("WARNING: TLB Not Sharable on SMTC Boot!\n"); | |
280 | } | |
281 | } | |
282 | } | |
283 | ||
284 | ||
285 | /* | |
286 | * Incrementally build the CPU map out of constituent MIPS MT cores, | |
287 | * using the specified available VPEs and TCs. Plaform code needs | |
288 | * to ensure that each MIPS MT core invokes this routine on reset, | |
289 | * one at a time(!). | |
290 | * | |
291 | * This version of the build_cpu_map and prepare_cpus routines assumes | |
292 | * that *all* TCs of a MIPS MT core will be used for Linux, and that | |
293 | * they will be spread across *all* available VPEs (to minimise the | |
294 | * loss of efficiency due to exception service serialization). | |
295 | * An improved version would pick up configuration information and | |
296 | * possibly leave some TCs/VPEs as "slave" processors. | |
297 | * | |
298 | * Use c0_MVPConf0 to find out how many TCs are available, setting up | |
299 | * phys_cpu_present_map and the logical/physical mappings. | |
300 | */ | |
301 | ||
302 | int __init mipsmt_build_cpu_map(int start_cpu_slot) | |
303 | { | |
304 | int i, ntcs; | |
305 | ||
306 | /* | |
307 | * The CPU map isn't actually used for anything at this point, | |
308 | * so it's not clear what else we should do apart from set | |
309 | * everything up so that "logical" = "physical". | |
310 | */ | |
311 | ntcs = ((read_c0_mvpconf0() & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT) + 1; | |
312 | for (i=start_cpu_slot; i<NR_CPUS && i<ntcs; i++) { | |
313 | cpu_set(i, phys_cpu_present_map); | |
314 | __cpu_number_map[i] = i; | |
315 | __cpu_logical_map[i] = i; | |
316 | } | |
317 | /* Initialize map of CPUs with FPUs */ | |
318 | cpus_clear(mt_fpu_cpumask); | |
319 | ||
320 | /* One of those TC's is the one booting, and not a secondary... */ | |
321 | printk("%i available secondary CPU TC(s)\n", i - 1); | |
322 | ||
323 | return i; | |
324 | } | |
325 | ||
326 | /* | |
327 | * Common setup before any secondaries are started | |
328 | * Make sure all CPU's are in a sensible state before we boot any of the | |
329 | * secondaries. | |
330 | * | |
331 | * For MIPS MT "SMTC" operation, we set up all TCs, spread as evenly | |
332 | * as possible across the available VPEs. | |
333 | */ | |
334 | ||
335 | static void smtc_tc_setup(int vpe, int tc, int cpu) | |
336 | { | |
337 | settc(tc); | |
338 | write_tc_c0_tchalt(TCHALT_H); | |
339 | mips_ihb(); | |
340 | write_tc_c0_tcstatus((read_tc_c0_tcstatus() | |
341 | & ~(TCSTATUS_TKSU | TCSTATUS_DA | TCSTATUS_IXMT)) | |
342 | | TCSTATUS_A); | |
343 | write_tc_c0_tccontext(0); | |
344 | /* Bind tc to vpe */ | |
345 | write_tc_c0_tcbind(vpe); | |
346 | /* In general, all TCs should have the same cpu_data indications */ | |
347 | memcpy(&cpu_data[cpu], &cpu_data[0], sizeof(struct cpuinfo_mips)); | |
348 | /* For 34Kf, start with TC/CPU 0 as sole owner of single FPU context */ | |
349 | if (cpu_data[0].cputype == CPU_34K) | |
350 | cpu_data[cpu].options &= ~MIPS_CPU_FPU; | |
351 | cpu_data[cpu].vpe_id = vpe; | |
352 | cpu_data[cpu].tc_id = tc; | |
353 | } | |
354 | ||
355 | ||
356 | void mipsmt_prepare_cpus(void) | |
357 | { | |
358 | int i, vpe, tc, ntc, nvpe, tcpervpe, slop, cpu; | |
359 | unsigned long flags; | |
360 | unsigned long val; | |
361 | int nipi; | |
362 | struct smtc_ipi *pipi; | |
363 | ||
364 | /* disable interrupts so we can disable MT */ | |
365 | local_irq_save(flags); | |
366 | /* disable MT so we can configure */ | |
367 | dvpe(); | |
368 | dmt(); | |
369 | ||
34af946a | 370 | spin_lock_init(&freeIPIq.lock); |
41c594ab RB |
371 | |
372 | /* | |
373 | * We probably don't have as many VPEs as we do SMP "CPUs", | |
374 | * but it's possible - and in any case we'll never use more! | |
375 | */ | |
376 | for (i=0; i<NR_CPUS; i++) { | |
377 | IPIQ[i].head = IPIQ[i].tail = NULL; | |
34af946a | 378 | spin_lock_init(&IPIQ[i].lock); |
41c594ab RB |
379 | IPIQ[i].depth = 0; |
380 | ipi_timer_latch[i] = 0; | |
381 | } | |
382 | ||
383 | /* cpu_data index starts at zero */ | |
384 | cpu = 0; | |
385 | cpu_data[cpu].vpe_id = 0; | |
386 | cpu_data[cpu].tc_id = 0; | |
387 | cpu++; | |
388 | ||
389 | /* Report on boot-time options */ | |
390 | mips_mt_set_cpuoptions (); | |
391 | if (vpelimit > 0) | |
392 | printk("Limit of %d VPEs set\n", vpelimit); | |
393 | if (tclimit > 0) | |
394 | printk("Limit of %d TCs set\n", tclimit); | |
395 | if (nostlb) { | |
396 | printk("Shared TLB Use Inhibited - UNSAFE for Multi-VPE Operation\n"); | |
397 | } | |
398 | if (asidmask) | |
399 | printk("ASID mask value override to 0x%x\n", asidmask); | |
400 | ||
401 | /* Temporary */ | |
402 | #ifdef SMTC_IDLE_HOOK_DEBUG | |
403 | if (hang_trig) | |
404 | printk("Logic Analyser Trigger on suspected TC hang\n"); | |
405 | #endif /* SMTC_IDLE_HOOK_DEBUG */ | |
406 | ||
407 | /* Put MVPE's into 'configuration state' */ | |
408 | write_c0_mvpcontrol( read_c0_mvpcontrol() | MVPCONTROL_VPC ); | |
409 | ||
410 | val = read_c0_mvpconf0(); | |
411 | nvpe = ((val & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1; | |
412 | if (vpelimit > 0 && nvpe > vpelimit) | |
413 | nvpe = vpelimit; | |
414 | ntc = ((val & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT) + 1; | |
415 | if (ntc > NR_CPUS) | |
416 | ntc = NR_CPUS; | |
417 | if (tclimit > 0 && ntc > tclimit) | |
418 | ntc = tclimit; | |
419 | tcpervpe = ntc / nvpe; | |
420 | slop = ntc % nvpe; /* Residual TCs, < NVPE */ | |
421 | ||
422 | /* Set up shared TLB */ | |
423 | smtc_configure_tlb(); | |
424 | ||
425 | for (tc = 0, vpe = 0 ; (vpe < nvpe) && (tc < ntc) ; vpe++) { | |
426 | /* | |
427 | * Set the MVP bits. | |
428 | */ | |
429 | settc(tc); | |
430 | write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() | VPECONF0_MVP); | |
431 | if (vpe != 0) | |
432 | printk(", "); | |
433 | printk("VPE %d: TC", vpe); | |
434 | for (i = 0; i < tcpervpe; i++) { | |
435 | /* | |
436 | * TC 0 is bound to VPE 0 at reset, | |
437 | * and is presumably executing this | |
438 | * code. Leave it alone! | |
439 | */ | |
440 | if (tc != 0) { | |
441 | smtc_tc_setup(vpe,tc, cpu); | |
442 | cpu++; | |
443 | } | |
444 | printk(" %d", tc); | |
445 | tc++; | |
446 | } | |
447 | if (slop) { | |
448 | if (tc != 0) { | |
449 | smtc_tc_setup(vpe,tc, cpu); | |
450 | cpu++; | |
451 | } | |
452 | printk(" %d", tc); | |
453 | tc++; | |
454 | slop--; | |
455 | } | |
456 | if (vpe != 0) { | |
457 | /* | |
458 | * Clear any stale software interrupts from VPE's Cause | |
459 | */ | |
460 | write_vpe_c0_cause(0); | |
461 | ||
462 | /* | |
463 | * Clear ERL/EXL of VPEs other than 0 | |
464 | * and set restricted interrupt enable/mask. | |
465 | */ | |
466 | write_vpe_c0_status((read_vpe_c0_status() | |
467 | & ~(ST0_BEV | ST0_ERL | ST0_EXL | ST0_IM)) | |
468 | | (STATUSF_IP0 | STATUSF_IP1 | STATUSF_IP7 | |
469 | | ST0_IE)); | |
470 | /* | |
471 | * set config to be the same as vpe0, | |
472 | * particularly kseg0 coherency alg | |
473 | */ | |
474 | write_vpe_c0_config(read_c0_config()); | |
475 | /* Clear any pending timer interrupt */ | |
476 | write_vpe_c0_compare(0); | |
477 | /* Propagate Config7 */ | |
478 | write_vpe_c0_config7(read_c0_config7()); | |
64c590b7 | 479 | write_vpe_c0_count(read_c0_count()); |
41c594ab RB |
480 | } |
481 | /* enable multi-threading within VPE */ | |
482 | write_vpe_c0_vpecontrol(read_vpe_c0_vpecontrol() | VPECONTROL_TE); | |
483 | /* enable the VPE */ | |
484 | write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() | VPECONF0_VPA); | |
485 | } | |
486 | ||
487 | /* | |
488 | * Pull any physically present but unused TCs out of circulation. | |
489 | */ | |
490 | while (tc < (((val & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT) + 1)) { | |
491 | cpu_clear(tc, phys_cpu_present_map); | |
492 | cpu_clear(tc, cpu_present_map); | |
493 | tc++; | |
494 | } | |
495 | ||
496 | /* release config state */ | |
497 | write_c0_mvpcontrol( read_c0_mvpcontrol() & ~ MVPCONTROL_VPC ); | |
498 | ||
499 | printk("\n"); | |
500 | ||
501 | /* Set up coprocessor affinity CPU mask(s) */ | |
502 | ||
503 | for (tc = 0; tc < ntc; tc++) { | |
4bf42d42 | 504 | if (cpu_data[tc].options & MIPS_CPU_FPU) |
41c594ab RB |
505 | cpu_set(tc, mt_fpu_cpumask); |
506 | } | |
507 | ||
508 | /* set up ipi interrupts... */ | |
509 | ||
510 | /* If we have multiple VPEs running, set up the cross-VPE interrupt */ | |
511 | ||
512 | if (nvpe > 1) | |
513 | setup_cross_vpe_interrupts(); | |
514 | ||
515 | /* Set up queue of free IPI "messages". */ | |
516 | nipi = NR_CPUS * IPIBUF_PER_CPU; | |
517 | if (ipibuffers > 0) | |
518 | nipi = ipibuffers; | |
519 | ||
520 | pipi = kmalloc(nipi *sizeof(struct smtc_ipi), GFP_KERNEL); | |
521 | if (pipi == NULL) | |
522 | panic("kmalloc of IPI message buffers failed\n"); | |
523 | else | |
524 | printk("IPI buffer pool of %d buffers\n", nipi); | |
525 | for (i = 0; i < nipi; i++) { | |
526 | smtc_ipi_nq(&freeIPIq, pipi); | |
527 | pipi++; | |
528 | } | |
529 | ||
530 | /* Arm multithreading and enable other VPEs - but all TCs are Halted */ | |
531 | emt(EMT_ENABLE); | |
532 | evpe(EVPE_ENABLE); | |
533 | local_irq_restore(flags); | |
534 | /* Initialize SMTC /proc statistics/diagnostics */ | |
535 | init_smtc_stats(); | |
536 | } | |
537 | ||
538 | ||
539 | /* | |
540 | * Setup the PC, SP, and GP of a secondary processor and start it | |
541 | * running! | |
542 | * smp_bootstrap is the place to resume from | |
543 | * __KSTK_TOS(idle) is apparently the stack pointer | |
544 | * (unsigned long)idle->thread_info the gp | |
545 | * | |
546 | */ | |
547 | void smtc_boot_secondary(int cpu, struct task_struct *idle) | |
548 | { | |
549 | extern u32 kernelsp[NR_CPUS]; | |
550 | long flags; | |
551 | int mtflags; | |
552 | ||
553 | LOCK_MT_PRA(); | |
554 | if (cpu_data[cpu].vpe_id != cpu_data[smp_processor_id()].vpe_id) { | |
555 | dvpe(); | |
556 | } | |
557 | settc(cpu_data[cpu].tc_id); | |
558 | ||
559 | /* pc */ | |
560 | write_tc_c0_tcrestart((unsigned long)&smp_bootstrap); | |
561 | ||
562 | /* stack pointer */ | |
563 | kernelsp[cpu] = __KSTK_TOS(idle); | |
564 | write_tc_gpr_sp(__KSTK_TOS(idle)); | |
565 | ||
566 | /* global pointer */ | |
567 | write_tc_gpr_gp((unsigned long)idle->thread_info); | |
568 | ||
569 | smtc_status |= SMTC_MTC_ACTIVE; | |
570 | write_tc_c0_tchalt(0); | |
571 | if (cpu_data[cpu].vpe_id != cpu_data[smp_processor_id()].vpe_id) { | |
572 | evpe(EVPE_ENABLE); | |
573 | } | |
574 | UNLOCK_MT_PRA(); | |
575 | } | |
576 | ||
577 | void smtc_init_secondary(void) | |
578 | { | |
579 | /* | |
580 | * Start timer on secondary VPEs if necessary. | |
54d0a216 | 581 | * plat_timer_setup has already have been invoked by init/main |
41c594ab RB |
582 | * on "boot" TC. Like per_cpu_trap_init() hack, this assumes that |
583 | * SMTC init code assigns TCs consdecutively and in ascending order | |
584 | * to across available VPEs. | |
585 | */ | |
4bf42d42 RB |
586 | if (((read_c0_tcbind() & TCBIND_CURTC) != 0) && |
587 | ((read_c0_tcbind() & TCBIND_CURVPE) | |
41c594ab RB |
588 | != cpu_data[smp_processor_id() - 1].vpe_id)){ |
589 | write_c0_compare (read_c0_count() + mips_hpt_frequency/HZ); | |
590 | } | |
591 | ||
592 | local_irq_enable(); | |
593 | } | |
594 | ||
595 | void smtc_smp_finish(void) | |
596 | { | |
597 | printk("TC %d going on-line as CPU %d\n", | |
598 | cpu_data[smp_processor_id()].tc_id, smp_processor_id()); | |
599 | } | |
600 | ||
601 | void smtc_cpus_done(void) | |
602 | { | |
603 | } | |
604 | ||
605 | /* | |
606 | * Support for SMTC-optimized driver IRQ registration | |
607 | */ | |
608 | ||
609 | /* | |
610 | * SMTC Kernel needs to manipulate low-level CPU interrupt mask | |
611 | * in do_IRQ. These are passed in setup_irq_smtc() and stored | |
612 | * in this table. | |
613 | */ | |
614 | ||
615 | int setup_irq_smtc(unsigned int irq, struct irqaction * new, | |
616 | unsigned long hwmask) | |
617 | { | |
618 | irq_hwmask[irq] = hwmask; | |
619 | ||
620 | return setup_irq(irq, new); | |
621 | } | |
622 | ||
623 | /* | |
624 | * IPI model for SMTC is tricky, because interrupts aren't TC-specific. | |
625 | * Within a VPE one TC can interrupt another by different approaches. | |
626 | * The easiest to get right would probably be to make all TCs except | |
627 | * the target IXMT and set a software interrupt, but an IXMT-based | |
628 | * scheme requires that a handler must run before a new IPI could | |
629 | * be sent, which would break the "broadcast" loops in MIPS MT. | |
630 | * A more gonzo approach within a VPE is to halt the TC, extract | |
631 | * its Restart, Status, and a couple of GPRs, and program the Restart | |
632 | * address to emulate an interrupt. | |
633 | * | |
634 | * Within a VPE, one can be confident that the target TC isn't in | |
635 | * a critical EXL state when halted, since the write to the Halt | |
636 | * register could not have issued on the writing thread if the | |
637 | * halting thread had EXL set. So k0 and k1 of the target TC | |
638 | * can be used by the injection code. Across VPEs, one can't | |
639 | * be certain that the target TC isn't in a critical exception | |
640 | * state. So we try a two-step process of sending a software | |
641 | * interrupt to the target VPE, which either handles the event | |
642 | * itself (if it was the target) or injects the event within | |
643 | * the VPE. | |
644 | */ | |
645 | ||
646 | void smtc_ipi_qdump(void) | |
647 | { | |
648 | int i; | |
649 | ||
650 | for (i = 0; i < NR_CPUS ;i++) { | |
651 | printk("IPIQ[%d]: head = 0x%x, tail = 0x%x, depth = %d\n", | |
652 | i, (unsigned)IPIQ[i].head, (unsigned)IPIQ[i].tail, | |
653 | IPIQ[i].depth); | |
654 | } | |
655 | } | |
656 | ||
657 | /* | |
658 | * The standard atomic.h primitives don't quite do what we want | |
659 | * here: We need an atomic add-and-return-previous-value (which | |
660 | * could be done with atomic_add_return and a decrement) and an | |
661 | * atomic set/zero-and-return-previous-value (which can't really | |
662 | * be done with the atomic.h primitives). And since this is | |
663 | * MIPS MT, we can assume that we have LL/SC. | |
664 | */ | |
665 | static __inline__ int atomic_postincrement(unsigned int *pv) | |
666 | { | |
667 | unsigned long result; | |
668 | ||
669 | unsigned long temp; | |
670 | ||
671 | __asm__ __volatile__( | |
672 | "1: ll %0, %2 \n" | |
673 | " addu %1, %0, 1 \n" | |
674 | " sc %1, %2 \n" | |
675 | " beqz %1, 1b \n" | |
676 | " sync \n" | |
677 | : "=&r" (result), "=&r" (temp), "=m" (*pv) | |
678 | : "m" (*pv) | |
679 | : "memory"); | |
680 | ||
681 | return result; | |
682 | } | |
683 | ||
684 | /* No longer used in IPI dispatch, but retained for future recycling */ | |
685 | ||
686 | static __inline__ int atomic_postclear(unsigned int *pv) | |
687 | { | |
688 | unsigned long result; | |
689 | ||
690 | unsigned long temp; | |
691 | ||
692 | __asm__ __volatile__( | |
693 | "1: ll %0, %2 \n" | |
694 | " or %1, $0, $0 \n" | |
695 | " sc %1, %2 \n" | |
696 | " beqz %1, 1b \n" | |
697 | " sync \n" | |
698 | : "=&r" (result), "=&r" (temp), "=m" (*pv) | |
699 | : "m" (*pv) | |
700 | : "memory"); | |
701 | ||
702 | return result; | |
703 | } | |
704 | ||
705 | ||
706 | void smtc_send_ipi(int cpu, int type, unsigned int action) | |
707 | { | |
708 | int tcstatus; | |
709 | struct smtc_ipi *pipi; | |
710 | long flags; | |
711 | int mtflags; | |
712 | ||
713 | if (cpu == smp_processor_id()) { | |
714 | printk("Cannot Send IPI to self!\n"); | |
715 | return; | |
716 | } | |
717 | /* Set up a descriptor, to be delivered either promptly or queued */ | |
718 | pipi = smtc_ipi_dq(&freeIPIq); | |
719 | if (pipi == NULL) { | |
720 | bust_spinlocks(1); | |
721 | mips_mt_regdump(dvpe()); | |
722 | panic("IPI Msg. Buffers Depleted\n"); | |
723 | } | |
724 | pipi->type = type; | |
725 | pipi->arg = (void *)action; | |
726 | pipi->dest = cpu; | |
727 | if (cpu_data[cpu].vpe_id != cpu_data[smp_processor_id()].vpe_id) { | |
728 | /* If not on same VPE, enqueue and send cross-VPE interupt */ | |
729 | smtc_ipi_nq(&IPIQ[cpu], pipi); | |
730 | LOCK_CORE_PRA(); | |
731 | settc(cpu_data[cpu].tc_id); | |
732 | write_vpe_c0_cause(read_vpe_c0_cause() | C_SW1); | |
733 | UNLOCK_CORE_PRA(); | |
734 | } else { | |
735 | /* | |
736 | * Not sufficient to do a LOCK_MT_PRA (dmt) here, | |
737 | * since ASID shootdown on the other VPE may | |
738 | * collide with this operation. | |
739 | */ | |
740 | LOCK_CORE_PRA(); | |
741 | settc(cpu_data[cpu].tc_id); | |
742 | /* Halt the targeted TC */ | |
743 | write_tc_c0_tchalt(TCHALT_H); | |
744 | mips_ihb(); | |
745 | ||
746 | /* | |
747 | * Inspect TCStatus - if IXMT is set, we have to queue | |
748 | * a message. Otherwise, we set up the "interrupt" | |
749 | * of the other TC | |
750 | */ | |
751 | tcstatus = read_tc_c0_tcstatus(); | |
752 | ||
753 | if ((tcstatus & TCSTATUS_IXMT) != 0) { | |
754 | /* | |
755 | * Spin-waiting here can deadlock, | |
756 | * so we queue the message for the target TC. | |
757 | */ | |
758 | write_tc_c0_tchalt(0); | |
759 | UNLOCK_CORE_PRA(); | |
760 | /* Try to reduce redundant timer interrupt messages */ | |
4bf42d42 RB |
761 | if (type == SMTC_CLOCK_TICK) { |
762 | if (atomic_postincrement(&ipi_timer_latch[cpu])!=0){ | |
41c594ab RB |
763 | smtc_ipi_nq(&freeIPIq, pipi); |
764 | return; | |
765 | } | |
766 | } | |
767 | smtc_ipi_nq(&IPIQ[cpu], pipi); | |
768 | } else { | |
769 | post_direct_ipi(cpu, pipi); | |
770 | write_tc_c0_tchalt(0); | |
771 | UNLOCK_CORE_PRA(); | |
772 | } | |
773 | } | |
774 | } | |
775 | ||
776 | /* | |
777 | * Send IPI message to Halted TC, TargTC/TargVPE already having been set | |
778 | */ | |
779 | void post_direct_ipi(int cpu, struct smtc_ipi *pipi) | |
780 | { | |
781 | struct pt_regs *kstack; | |
782 | unsigned long tcstatus; | |
783 | unsigned long tcrestart; | |
784 | extern u32 kernelsp[NR_CPUS]; | |
785 | extern void __smtc_ipi_vector(void); | |
786 | ||
787 | /* Extract Status, EPC from halted TC */ | |
788 | tcstatus = read_tc_c0_tcstatus(); | |
789 | tcrestart = read_tc_c0_tcrestart(); | |
790 | /* If TCRestart indicates a WAIT instruction, advance the PC */ | |
791 | if ((tcrestart & 0x80000000) | |
792 | && ((*(unsigned int *)tcrestart & 0xfe00003f) == 0x42000020)) { | |
793 | tcrestart += 4; | |
794 | } | |
795 | /* | |
796 | * Save on TC's future kernel stack | |
797 | * | |
798 | * CU bit of Status is indicator that TC was | |
799 | * already running on a kernel stack... | |
800 | */ | |
4bf42d42 | 801 | if (tcstatus & ST0_CU0) { |
41c594ab RB |
802 | /* Note that this "- 1" is pointer arithmetic */ |
803 | kstack = ((struct pt_regs *)read_tc_gpr_sp()) - 1; | |
804 | } else { | |
805 | kstack = ((struct pt_regs *)kernelsp[cpu]) - 1; | |
806 | } | |
807 | ||
808 | kstack->cp0_epc = (long)tcrestart; | |
809 | /* Save TCStatus */ | |
810 | kstack->cp0_tcstatus = tcstatus; | |
811 | /* Pass token of operation to be performed kernel stack pad area */ | |
812 | kstack->pad0[4] = (unsigned long)pipi; | |
813 | /* Pass address of function to be called likewise */ | |
814 | kstack->pad0[5] = (unsigned long)&ipi_decode; | |
815 | /* Set interrupt exempt and kernel mode */ | |
816 | tcstatus |= TCSTATUS_IXMT; | |
817 | tcstatus &= ~TCSTATUS_TKSU; | |
818 | write_tc_c0_tcstatus(tcstatus); | |
819 | ehb(); | |
820 | /* Set TC Restart address to be SMTC IPI vector */ | |
821 | write_tc_c0_tcrestart(__smtc_ipi_vector); | |
822 | } | |
823 | ||
937a8015 | 824 | static void ipi_resched_interrupt(void) |
41c594ab RB |
825 | { |
826 | /* Return from interrupt should be enough to cause scheduler check */ | |
827 | } | |
828 | ||
829 | ||
937a8015 | 830 | static void ipi_call_interrupt(void) |
41c594ab RB |
831 | { |
832 | /* Invoke generic function invocation code in smp.c */ | |
833 | smp_call_function_interrupt(); | |
834 | } | |
835 | ||
937a8015 | 836 | void ipi_decode(struct smtc_ipi *pipi) |
41c594ab RB |
837 | { |
838 | void *arg_copy = pipi->arg; | |
839 | int type_copy = pipi->type; | |
840 | int dest_copy = pipi->dest; | |
841 | ||
842 | smtc_ipi_nq(&freeIPIq, pipi); | |
843 | switch (type_copy) { | |
4bf42d42 RB |
844 | case SMTC_CLOCK_TICK: |
845 | /* Invoke Clock "Interrupt" */ | |
846 | ipi_timer_latch[dest_copy] = 0; | |
41c594ab | 847 | #ifdef SMTC_IDLE_HOOK_DEBUG |
4bf42d42 | 848 | clock_hang_reported[dest_copy] = 0; |
41c594ab | 849 | #endif /* SMTC_IDLE_HOOK_DEBUG */ |
937a8015 | 850 | local_timer_interrupt(0, NULL); |
4bf42d42 RB |
851 | break; |
852 | case LINUX_SMP_IPI: | |
853 | switch ((int)arg_copy) { | |
854 | case SMP_RESCHEDULE_YOURSELF: | |
937a8015 | 855 | ipi_resched_interrupt(); |
41c594ab | 856 | break; |
4bf42d42 | 857 | case SMP_CALL_FUNCTION: |
937a8015 | 858 | ipi_call_interrupt(); |
41c594ab RB |
859 | break; |
860 | default: | |
4bf42d42 RB |
861 | printk("Impossible SMTC IPI Argument 0x%x\n", |
862 | (int)arg_copy); | |
41c594ab | 863 | break; |
4bf42d42 RB |
864 | } |
865 | break; | |
866 | default: | |
867 | printk("Impossible SMTC IPI Type 0x%x\n", type_copy); | |
868 | break; | |
41c594ab RB |
869 | } |
870 | } | |
871 | ||
937a8015 | 872 | void deferred_smtc_ipi(void) |
41c594ab RB |
873 | { |
874 | struct smtc_ipi *pipi; | |
875 | unsigned long flags; | |
876 | /* DEBUG */ | |
877 | int q = smp_processor_id(); | |
878 | ||
879 | /* | |
880 | * Test is not atomic, but much faster than a dequeue, | |
881 | * and the vast majority of invocations will have a null queue. | |
882 | */ | |
4bf42d42 | 883 | if (IPIQ[q].head != NULL) { |
41c594ab RB |
884 | while((pipi = smtc_ipi_dq(&IPIQ[q])) != NULL) { |
885 | /* ipi_decode() should be called with interrupts off */ | |
886 | local_irq_save(flags); | |
937a8015 | 887 | ipi_decode(pipi); |
41c594ab RB |
888 | local_irq_restore(flags); |
889 | } | |
890 | } | |
891 | } | |
892 | ||
893 | /* | |
894 | * Send clock tick to all TCs except the one executing the funtion | |
895 | */ | |
896 | ||
897 | void smtc_timer_broadcast(int vpe) | |
898 | { | |
899 | int cpu; | |
900 | int myTC = cpu_data[smp_processor_id()].tc_id; | |
901 | int myVPE = cpu_data[smp_processor_id()].vpe_id; | |
902 | ||
903 | smtc_cpu_stats[smp_processor_id()].timerints++; | |
904 | ||
905 | for_each_online_cpu(cpu) { | |
906 | if (cpu_data[cpu].vpe_id == myVPE && | |
907 | cpu_data[cpu].tc_id != myTC) | |
908 | smtc_send_ipi(cpu, SMTC_CLOCK_TICK, 0); | |
909 | } | |
910 | } | |
911 | ||
912 | /* | |
913 | * Cross-VPE interrupts in the SMTC prototype use "software interrupts" | |
914 | * set via cross-VPE MTTR manipulation of the Cause register. It would be | |
915 | * in some regards preferable to have external logic for "doorbell" hardware | |
916 | * interrupts. | |
917 | */ | |
918 | ||
919 | static int cpu_ipi_irq = MIPSCPU_INT_BASE + MIPS_CPU_IPI_IRQ; | |
920 | ||
937a8015 | 921 | static irqreturn_t ipi_interrupt(int irq, void *dev_idm) |
41c594ab RB |
922 | { |
923 | int my_vpe = cpu_data[smp_processor_id()].vpe_id; | |
924 | int my_tc = cpu_data[smp_processor_id()].tc_id; | |
925 | int cpu; | |
926 | struct smtc_ipi *pipi; | |
927 | unsigned long tcstatus; | |
928 | int sent; | |
929 | long flags; | |
930 | unsigned int mtflags; | |
931 | unsigned int vpflags; | |
932 | ||
933 | /* | |
934 | * So long as cross-VPE interrupts are done via | |
935 | * MFTR/MTTR read-modify-writes of Cause, we need | |
936 | * to stop other VPEs whenever the local VPE does | |
937 | * anything similar. | |
938 | */ | |
939 | local_irq_save(flags); | |
940 | vpflags = dvpe(); | |
941 | clear_c0_cause(0x100 << MIPS_CPU_IPI_IRQ); | |
942 | set_c0_status(0x100 << MIPS_CPU_IPI_IRQ); | |
943 | irq_enable_hazard(); | |
944 | evpe(vpflags); | |
945 | local_irq_restore(flags); | |
946 | ||
947 | /* | |
948 | * Cross-VPE Interrupt handler: Try to directly deliver IPIs | |
949 | * queued for TCs on this VPE other than the current one. | |
950 | * Return-from-interrupt should cause us to drain the queue | |
951 | * for the current TC, so we ought not to have to do it explicitly here. | |
952 | */ | |
953 | ||
954 | for_each_online_cpu(cpu) { | |
955 | if (cpu_data[cpu].vpe_id != my_vpe) | |
956 | continue; | |
957 | ||
958 | pipi = smtc_ipi_dq(&IPIQ[cpu]); | |
959 | if (pipi != NULL) { | |
960 | if (cpu_data[cpu].tc_id != my_tc) { | |
961 | sent = 0; | |
962 | LOCK_MT_PRA(); | |
963 | settc(cpu_data[cpu].tc_id); | |
964 | write_tc_c0_tchalt(TCHALT_H); | |
965 | mips_ihb(); | |
966 | tcstatus = read_tc_c0_tcstatus(); | |
967 | if ((tcstatus & TCSTATUS_IXMT) == 0) { | |
968 | post_direct_ipi(cpu, pipi); | |
969 | sent = 1; | |
970 | } | |
971 | write_tc_c0_tchalt(0); | |
972 | UNLOCK_MT_PRA(); | |
973 | if (!sent) { | |
974 | smtc_ipi_req(&IPIQ[cpu], pipi); | |
975 | } | |
976 | } else { | |
977 | /* | |
978 | * ipi_decode() should be called | |
979 | * with interrupts off | |
980 | */ | |
981 | local_irq_save(flags); | |
937a8015 | 982 | ipi_decode(pipi); |
41c594ab RB |
983 | local_irq_restore(flags); |
984 | } | |
985 | } | |
986 | } | |
987 | ||
988 | return IRQ_HANDLED; | |
989 | } | |
990 | ||
937a8015 | 991 | static void ipi_irq_dispatch(void) |
41c594ab | 992 | { |
937a8015 | 993 | do_IRQ(cpu_ipi_irq); |
41c594ab RB |
994 | } |
995 | ||
996 | static struct irqaction irq_ipi; | |
997 | ||
998 | void setup_cross_vpe_interrupts(void) | |
999 | { | |
1000 | if (!cpu_has_vint) | |
1001 | panic("SMTC Kernel requires Vectored Interupt support"); | |
1002 | ||
1003 | set_vi_handler(MIPS_CPU_IPI_IRQ, ipi_irq_dispatch); | |
1004 | ||
1005 | irq_ipi.handler = ipi_interrupt; | |
f40298fd | 1006 | irq_ipi.flags = IRQF_DISABLED; |
41c594ab RB |
1007 | irq_ipi.name = "SMTC_IPI"; |
1008 | ||
1009 | setup_irq_smtc(cpu_ipi_irq, &irq_ipi, (0x100 << MIPS_CPU_IPI_IRQ)); | |
1010 | ||
1011 | irq_desc[cpu_ipi_irq].status |= IRQ_PER_CPU; | |
1012 | } | |
1013 | ||
1014 | /* | |
1015 | * SMTC-specific hacks invoked from elsewhere in the kernel. | |
1016 | */ | |
1017 | ||
1018 | void smtc_idle_loop_hook(void) | |
1019 | { | |
1020 | #ifdef SMTC_IDLE_HOOK_DEBUG | |
1021 | int im; | |
1022 | int flags; | |
1023 | int mtflags; | |
1024 | int bit; | |
1025 | int vpe; | |
1026 | int tc; | |
1027 | int hook_ntcs; | |
1028 | /* | |
1029 | * printk within DMT-protected regions can deadlock, | |
1030 | * so buffer diagnostic messages for later output. | |
1031 | */ | |
1032 | char *pdb_msg; | |
1033 | char id_ho_db_msg[768]; /* worst-case use should be less than 700 */ | |
1034 | ||
1035 | if (atomic_read(&idle_hook_initialized) == 0) { /* fast test */ | |
1036 | if (atomic_add_return(1, &idle_hook_initialized) == 1) { | |
1037 | int mvpconf0; | |
1038 | /* Tedious stuff to just do once */ | |
1039 | mvpconf0 = read_c0_mvpconf0(); | |
1040 | hook_ntcs = ((mvpconf0 & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT) + 1; | |
1041 | if (hook_ntcs > NR_CPUS) | |
1042 | hook_ntcs = NR_CPUS; | |
1043 | for (tc = 0; tc < hook_ntcs; tc++) { | |
1044 | tcnoprog[tc] = 0; | |
1045 | clock_hang_reported[tc] = 0; | |
1046 | } | |
1047 | for (vpe = 0; vpe < 2; vpe++) | |
1048 | for (im = 0; im < 8; im++) | |
1049 | imstuckcount[vpe][im] = 0; | |
1050 | printk("Idle loop test hook initialized for %d TCs\n", hook_ntcs); | |
1051 | atomic_set(&idle_hook_initialized, 1000); | |
1052 | } else { | |
1053 | /* Someone else is initializing in parallel - let 'em finish */ | |
1054 | while (atomic_read(&idle_hook_initialized) < 1000) | |
1055 | ; | |
1056 | } | |
1057 | } | |
1058 | ||
1059 | /* Have we stupidly left IXMT set somewhere? */ | |
1060 | if (read_c0_tcstatus() & 0x400) { | |
1061 | write_c0_tcstatus(read_c0_tcstatus() & ~0x400); | |
1062 | ehb(); | |
1063 | printk("Dangling IXMT in cpu_idle()\n"); | |
1064 | } | |
1065 | ||
1066 | /* Have we stupidly left an IM bit turned off? */ | |
1067 | #define IM_LIMIT 2000 | |
1068 | local_irq_save(flags); | |
1069 | mtflags = dmt(); | |
1070 | pdb_msg = &id_ho_db_msg[0]; | |
1071 | im = read_c0_status(); | |
1072 | vpe = cpu_data[smp_processor_id()].vpe_id; | |
1073 | for (bit = 0; bit < 8; bit++) { | |
1074 | /* | |
1075 | * In current prototype, I/O interrupts | |
1076 | * are masked for VPE > 0 | |
1077 | */ | |
1078 | if (vpemask[vpe][bit]) { | |
1079 | if (!(im & (0x100 << bit))) | |
1080 | imstuckcount[vpe][bit]++; | |
1081 | else | |
1082 | imstuckcount[vpe][bit] = 0; | |
1083 | if (imstuckcount[vpe][bit] > IM_LIMIT) { | |
1084 | set_c0_status(0x100 << bit); | |
1085 | ehb(); | |
1086 | imstuckcount[vpe][bit] = 0; | |
1087 | pdb_msg += sprintf(pdb_msg, | |
1088 | "Dangling IM %d fixed for VPE %d\n", bit, | |
1089 | vpe); | |
1090 | } | |
1091 | } | |
1092 | } | |
1093 | ||
1094 | /* | |
1095 | * Now that we limit outstanding timer IPIs, check for hung TC | |
1096 | */ | |
1097 | for (tc = 0; tc < NR_CPUS; tc++) { | |
1098 | /* Don't check ourself - we'll dequeue IPIs just below */ | |
1099 | if ((tc != smp_processor_id()) && | |
1100 | ipi_timer_latch[tc] > timerq_limit) { | |
1101 | if (clock_hang_reported[tc] == 0) { | |
1102 | pdb_msg += sprintf(pdb_msg, | |
1103 | "TC %d looks hung with timer latch at %d\n", | |
1104 | tc, ipi_timer_latch[tc]); | |
1105 | clock_hang_reported[tc]++; | |
1106 | } | |
1107 | } | |
1108 | } | |
1109 | emt(mtflags); | |
1110 | local_irq_restore(flags); | |
1111 | if (pdb_msg != &id_ho_db_msg[0]) | |
1112 | printk("CPU%d: %s", smp_processor_id(), id_ho_db_msg); | |
1113 | #endif /* SMTC_IDLE_HOOK_DEBUG */ | |
1114 | /* | |
1115 | * To the extent that we've ever turned interrupts off, | |
1116 | * we may have accumulated deferred IPIs. This is subtle. | |
1117 | * If we use the smtc_ipi_qdepth() macro, we'll get an | |
1118 | * exact number - but we'll also disable interrupts | |
1119 | * and create a window of failure where a new IPI gets | |
1120 | * queued after we test the depth but before we re-enable | |
1121 | * interrupts. So long as IXMT never gets set, however, | |
1122 | * we should be OK: If we pick up something and dispatch | |
1123 | * it here, that's great. If we see nothing, but concurrent | |
1124 | * with this operation, another TC sends us an IPI, IXMT | |
1125 | * is clear, and we'll handle it as a real pseudo-interrupt | |
1126 | * and not a pseudo-pseudo interrupt. | |
1127 | */ | |
1128 | if (IPIQ[smp_processor_id()].depth > 0) { | |
1129 | struct smtc_ipi *pipi; | |
1130 | extern void self_ipi(struct smtc_ipi *); | |
1131 | ||
1132 | if ((pipi = smtc_ipi_dq(&IPIQ[smp_processor_id()])) != NULL) { | |
1133 | self_ipi(pipi); | |
1134 | smtc_cpu_stats[smp_processor_id()].selfipis++; | |
1135 | } | |
1136 | } | |
1137 | } | |
1138 | ||
1139 | void smtc_soft_dump(void) | |
1140 | { | |
1141 | int i; | |
1142 | ||
1143 | printk("Counter Interrupts taken per CPU (TC)\n"); | |
1144 | for (i=0; i < NR_CPUS; i++) { | |
1145 | printk("%d: %ld\n", i, smtc_cpu_stats[i].timerints); | |
1146 | } | |
1147 | printk("Self-IPI invocations:\n"); | |
1148 | for (i=0; i < NR_CPUS; i++) { | |
1149 | printk("%d: %ld\n", i, smtc_cpu_stats[i].selfipis); | |
1150 | } | |
1151 | smtc_ipi_qdump(); | |
1152 | printk("Timer IPI Backlogs:\n"); | |
1153 | for (i=0; i < NR_CPUS; i++) { | |
1154 | printk("%d: %d\n", i, ipi_timer_latch[i]); | |
1155 | } | |
1156 | printk("%d Recoveries of \"stolen\" FPU\n", | |
1157 | atomic_read(&smtc_fpu_recoveries)); | |
1158 | } | |
1159 | ||
1160 | ||
1161 | /* | |
1162 | * TLB management routines special to SMTC | |
1163 | */ | |
1164 | ||
1165 | void smtc_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu) | |
1166 | { | |
1167 | unsigned long flags, mtflags, tcstat, prevhalt, asid; | |
1168 | int tlb, i; | |
1169 | ||
1170 | /* | |
1171 | * It would be nice to be able to use a spinlock here, | |
1172 | * but this is invoked from within TLB flush routines | |
1173 | * that protect themselves with DVPE, so if a lock is | |
1174 | * held by another TC, it'll never be freed. | |
1175 | * | |
1176 | * DVPE/DMT must not be done with interrupts enabled, | |
1177 | * so even so most callers will already have disabled | |
1178 | * them, let's be really careful... | |
1179 | */ | |
1180 | ||
1181 | local_irq_save(flags); | |
1182 | if (smtc_status & SMTC_TLB_SHARED) { | |
1183 | mtflags = dvpe(); | |
1184 | tlb = 0; | |
1185 | } else { | |
1186 | mtflags = dmt(); | |
1187 | tlb = cpu_data[cpu].vpe_id; | |
1188 | } | |
1189 | asid = asid_cache(cpu); | |
1190 | ||
1191 | do { | |
1192 | if (!((asid += ASID_INC) & ASID_MASK) ) { | |
1193 | if (cpu_has_vtag_icache) | |
1194 | flush_icache_all(); | |
1195 | /* Traverse all online CPUs (hack requires contigous range) */ | |
1196 | for (i = 0; i < num_online_cpus(); i++) { | |
1197 | /* | |
1198 | * We don't need to worry about our own CPU, nor those of | |
1199 | * CPUs who don't share our TLB. | |
1200 | */ | |
1201 | if ((i != smp_processor_id()) && | |
1202 | ((smtc_status & SMTC_TLB_SHARED) || | |
1203 | (cpu_data[i].vpe_id == cpu_data[cpu].vpe_id))) { | |
1204 | settc(cpu_data[i].tc_id); | |
1205 | prevhalt = read_tc_c0_tchalt() & TCHALT_H; | |
1206 | if (!prevhalt) { | |
1207 | write_tc_c0_tchalt(TCHALT_H); | |
1208 | mips_ihb(); | |
1209 | } | |
1210 | tcstat = read_tc_c0_tcstatus(); | |
1211 | smtc_live_asid[tlb][(tcstat & ASID_MASK)] |= (asiduse)(0x1 << i); | |
1212 | if (!prevhalt) | |
1213 | write_tc_c0_tchalt(0); | |
1214 | } | |
1215 | } | |
1216 | if (!asid) /* fix version if needed */ | |
1217 | asid = ASID_FIRST_VERSION; | |
1218 | local_flush_tlb_all(); /* start new asid cycle */ | |
1219 | } | |
1220 | } while (smtc_live_asid[tlb][(asid & ASID_MASK)]); | |
1221 | ||
1222 | /* | |
1223 | * SMTC shares the TLB within VPEs and possibly across all VPEs. | |
1224 | */ | |
1225 | for (i = 0; i < num_online_cpus(); i++) { | |
1226 | if ((smtc_status & SMTC_TLB_SHARED) || | |
1227 | (cpu_data[i].vpe_id == cpu_data[cpu].vpe_id)) | |
1228 | cpu_context(i, mm) = asid_cache(i) = asid; | |
1229 | } | |
1230 | ||
1231 | if (smtc_status & SMTC_TLB_SHARED) | |
1232 | evpe(mtflags); | |
1233 | else | |
1234 | emt(mtflags); | |
1235 | local_irq_restore(flags); | |
1236 | } | |
1237 | ||
1238 | /* | |
1239 | * Invoked from macros defined in mmu_context.h | |
1240 | * which must already have disabled interrupts | |
1241 | * and done a DVPE or DMT as appropriate. | |
1242 | */ | |
1243 | ||
1244 | void smtc_flush_tlb_asid(unsigned long asid) | |
1245 | { | |
1246 | int entry; | |
1247 | unsigned long ehi; | |
1248 | ||
1249 | entry = read_c0_wired(); | |
1250 | ||
1251 | /* Traverse all non-wired entries */ | |
1252 | while (entry < current_cpu_data.tlbsize) { | |
1253 | write_c0_index(entry); | |
1254 | ehb(); | |
1255 | tlb_read(); | |
1256 | ehb(); | |
1257 | ehi = read_c0_entryhi(); | |
4bf42d42 | 1258 | if ((ehi & ASID_MASK) == asid) { |
41c594ab RB |
1259 | /* |
1260 | * Invalidate only entries with specified ASID, | |
1261 | * makiing sure all entries differ. | |
1262 | */ | |
1263 | write_c0_entryhi(CKSEG0 + (entry << (PAGE_SHIFT + 1))); | |
1264 | write_c0_entrylo0(0); | |
1265 | write_c0_entrylo1(0); | |
1266 | mtc0_tlbw_hazard(); | |
1267 | tlb_write_indexed(); | |
1268 | } | |
1269 | entry++; | |
1270 | } | |
1271 | write_c0_index(PARKED_INDEX); | |
1272 | tlbw_use_hazard(); | |
1273 | } | |
1274 | ||
1275 | /* | |
1276 | * Support for single-threading cache flush operations. | |
1277 | */ | |
1278 | ||
1279 | int halt_state_save[NR_CPUS]; | |
1280 | ||
1281 | /* | |
1282 | * To really, really be sure that nothing is being done | |
1283 | * by other TCs, halt them all. This code assumes that | |
1284 | * a DVPE has already been done, so while their Halted | |
1285 | * state is theoretically architecturally unstable, in | |
1286 | * practice, it's not going to change while we're looking | |
1287 | * at it. | |
1288 | */ | |
1289 | ||
1290 | void smtc_cflush_lockdown(void) | |
1291 | { | |
1292 | int cpu; | |
1293 | ||
1294 | for_each_online_cpu(cpu) { | |
1295 | if (cpu != smp_processor_id()) { | |
1296 | settc(cpu_data[cpu].tc_id); | |
1297 | halt_state_save[cpu] = read_tc_c0_tchalt(); | |
1298 | write_tc_c0_tchalt(TCHALT_H); | |
1299 | } | |
1300 | } | |
1301 | mips_ihb(); | |
1302 | } | |
1303 | ||
1304 | /* It would be cheating to change the cpu_online states during a flush! */ | |
1305 | ||
1306 | void smtc_cflush_release(void) | |
1307 | { | |
1308 | int cpu; | |
1309 | ||
1310 | /* | |
1311 | * Start with a hazard barrier to ensure | |
1312 | * that all CACHE ops have played through. | |
1313 | */ | |
1314 | mips_ihb(); | |
1315 | ||
1316 | for_each_online_cpu(cpu) { | |
1317 | if (cpu != smp_processor_id()) { | |
1318 | settc(cpu_data[cpu].tc_id); | |
1319 | write_tc_c0_tchalt(halt_state_save[cpu]); | |
1320 | } | |
1321 | } | |
1322 | mips_ihb(); | |
1323 | } |