[deliverable/linux.git] / arch / mips / kernel / sync-r4k.c

/*
 * Count register synchronisation.
 *
 * All CPUs will have their count registers synchronised to the CPU0 next time
 * value. This can cause a small timewarp for CPU0. All other CPU's should
 * not have done anything significant (but they may have had interrupts
 * enabled briefly - prom_smp_finish() should not be responsible for enabling
 * interrupts...)
 *
 * FIXME: broken for SMTC
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/irqflags.h>
#include <linux/cpumask.h>

#include <asm/r4k-timer.h>
#include <linux/atomic.h>
#include <asm/barrier.h>
#include <asm/mipsregs.h>

static atomic_t count_start_flag = ATOMIC_INIT(0);
static atomic_t count_count_start = ATOMIC_INIT(0);
static atomic_t count_count_stop = ATOMIC_INIT(0);
static atomic_t count_reference = ATOMIC_INIT(0);

#define COUNTON 100
#define NR_LOOPS 5

void synchronise_count_master(int cpu)
{
	int i;
	unsigned long flags;
	unsigned int initcount;

#ifdef CONFIG_MIPS_MT_SMTC
	/*
	 * SMTC needs to synchronise per VPE, not per CPU
	 * ignore for now
	 */
	return;
#endif

	printk(KERN_INFO "Synchronize counters for CPU %u: ", cpu);

	local_irq_save(flags);

	/*
	 * Notify the slaves that it's time to start
	 */
	atomic_set(&count_reference, read_c0_count());
	atomic_set(&count_start_flag, cpu);
	smp_wmb();

	/* Count will be initialised to current timer for all CPU's */
	initcount = read_c0_count();

	/*
	 * We loop a few times to get a primed instruction cache,
	 * then the last pass is more or less synchronised and
	 * the master and slaves each set their cycle counters to a known
	 * value all at once. This reduces the chance of having random offsets
	 * between the processors, and guarantees that the maximum
	 * delay between the cycle counters is never bigger than
	 * the latency of information-passing (cachelines) between
	 * two CPUs.
	 */

	for (i = 0; i < NR_LOOPS; i++) {
		/* slaves loop on '!= 2' */
		while (atomic_read(&count_count_start) != 1)
			mb();
		atomic_set(&count_count_stop, 0);
		smp_wmb();

		/* this lets the slaves write their count register */
		atomic_inc(&count_count_start);

		/*
		 * Everyone initialises count in the last loop:
		 */
		if (i == NR_LOOPS-1)
			write_c0_count(initcount);

		/*
		 * Wait for all slaves to leave the synchronization point:
		 */
		while (atomic_read(&count_count_stop) != 1)
			mb();
		atomic_set(&count_count_start, 0);
		smp_wmb();
		atomic_inc(&count_count_stop);
	}
	/* Arrange for an interrupt in a short while */
	write_c0_compare(read_c0_count() + COUNTON);
	atomic_set(&count_start_flag, 0);

	local_irq_restore(flags);

	/*
	 * i386 code reported the skew here, but the
	 * count registers were almost certainly out of sync
	 * so no point in alarming people
	 */
	printk("done.\n");
}

void synchronise_count_slave(int cpu)
{
	int i;
	unsigned int initcount;

#ifdef CONFIG_MIPS_MT_SMTC
	/*
	 * SMTC needs to synchronise per VPE, not per CPU
	 * ignore for now
	 */
	return;
#endif

	/*
	 * Not every cpu is online at the time this gets called,
	 * so we first wait for the master to say everyone is ready
	 */

	while (atomic_read(&count_start_flag) != cpu)
		mb();

	/* Count will be initialised to next expire for all CPU's */
	initcount = atomic_read(&count_reference);

	for (i = 0; i < NR_LOOPS; i++) {
		atomic_inc(&count_count_start);
		while (atomic_read(&count_count_start) != 2)
			mb();

		/*
		 * Everyone initialises count in the last loop:
		 */
		if (i == NR_LOOPS-1)
			write_c0_count(initcount);

		atomic_inc(&count_count_stop);
		while (atomic_read(&count_count_stop) != 2)
			mb();
	}
	/* Arrange for an interrupt in a short while */
	write_c0_compare(read_c0_count() + COUNTON);
}
#undef NR_LOOPS
Commit	Line	Data
39b8d525 RB	1	/*
	2	* Count register synchronisation.
	3	*
eb9b5141	4	* All CPUs will have their count registers synchronised to the CPU0 next time
39b8d525 RB	5	* value. This can cause a small timewarp for CPU0. All other CPU's should
	6	* not have done anything significant (but they may have had interrupts
	7	* enabled briefly - prom_smp_finish() should not be responsible for enabling
	8	* interrupts...)
	9	*
	10	* FIXME: broken for SMTC
	11	*/
	12
	13	#include <linux/kernel.h>
	14	#include <linux/init.h>
	15	#include <linux/irqflags.h>
eb9b5141	16	#include <linux/cpumask.h>
39b8d525	17
eb9b5141	18	#include <asm/r4k-timer.h>
60063497	19	#include <linux/atomic.h>
39b8d525	20	#include <asm/barrier.h>
39b8d525 RB	21	#include <asm/mipsregs.h>
39b8d525 RB	22
078a55fc PG	23	static atomic_t count_start_flag = ATOMIC_INIT(0);
	24	static atomic_t count_count_start = ATOMIC_INIT(0);
	25	static atomic_t count_count_stop = ATOMIC_INIT(0);
	26	static atomic_t count_reference = ATOMIC_INIT(0);
39b8d525	27
70342287	28	#define COUNTON 100
39b8d525 RB	29	#define NR_LOOPS 5
39b8d525 RB	30
078a55fc	31	void synchronise_count_master(int cpu)
39b8d525 RB	32	{
	33	int i;
	34	unsigned long flags;
	35	unsigned int initcount;
39b8d525 RB	36
	37	#ifdef CONFIG_MIPS_MT_SMTC
	38	/*
	39	* SMTC needs to synchronise per VPE, not per CPU
	40	* ignore for now
	41	*/
	42	return;
	43	#endif
	44
cf9bfe55	45	printk(KERN_INFO "Synchronize counters for CPU %u: ", cpu);
39b8d525 RB	46
	47	local_irq_save(flags);
	48
	49	/*
	50	* Notify the slaves that it's time to start
	51	*/
eb9b5141	52	atomic_set(&count_reference, read_c0_count());
cf9bfe55	53	atomic_set(&count_start_flag, cpu);
39b8d525 RB	54	smp_wmb();
39b8d525 RB	55
eb9b5141 TA	56	/* Count will be initialised to current timer for all CPU's */
eb9b5141 TA	57	initcount = read_c0_count();
39b8d525 RB	58
	59	/*
	60	* We loop a few times to get a primed instruction cache,
	61	* then the last pass is more or less synchronised and
	62	* the master and slaves each set their cycle counters to a known
	63	* value all at once. This reduces the chance of having random offsets
	64	* between the processors, and guarantees that the maximum
	65	* delay between the cycle counters is never bigger than
	66	* the latency of information-passing (cachelines) between
	67	* two CPUs.
	68	*/
	69
39b8d525	70	for (i = 0; i < NR_LOOPS; i++) {
cf9bfe55 J	71	/* slaves loop on '!= 2' */
cf9bfe55 J	72	while (atomic_read(&count_count_start) != 1)
39b8d525 RB	73	mb();
	74	atomic_set(&count_count_stop, 0);
	75	smp_wmb();
	76
	77	/* this lets the slaves write their count register */
	78	atomic_inc(&count_count_start);
	79
	80	/*
	81	* Everyone initialises count in the last loop:
	82	*/
	83	if (i == NR_LOOPS-1)
	84	write_c0_count(initcount);
	85
	86	/*
	87	* Wait for all slaves to leave the synchronization point:
	88	*/
cf9bfe55	89	while (atomic_read(&count_count_stop) != 1)
39b8d525 RB	90	mb();
	91	atomic_set(&count_count_start, 0);
	92	smp_wmb();
	93	atomic_inc(&count_count_stop);
	94	}
	95	/* Arrange for an interrupt in a short while */
	96	write_c0_compare(read_c0_count() + COUNTON);
cf9bfe55	97	atomic_set(&count_start_flag, 0);
39b8d525 RB	98
	99	local_irq_restore(flags);
	100
	101	/*
	102	* i386 code reported the skew here, but the
	103	* count registers were almost certainly out of sync
	104	* so no point in alarming people
	105	*/
	106	printk("done.\n");
	107	}
	108
078a55fc	109	void synchronise_count_slave(int cpu)
39b8d525 RB	110	{
39b8d525 RB	111	int i;
39b8d525	112	unsigned int initcount;
39b8d525 RB	113
	114	#ifdef CONFIG_MIPS_MT_SMTC
	115	/*
	116	* SMTC needs to synchronise per VPE, not per CPU
	117	* ignore for now
	118	*/
	119	return;
	120	#endif
	121
39b8d525 RB	122	/*
	123	* Not every cpu is online at the time this gets called,
	124	* so we first wait for the master to say everyone is ready
	125	*/
	126
cf9bfe55	127	while (atomic_read(&count_start_flag) != cpu)
39b8d525 RB	128	mb();
39b8d525 RB	129
eb9b5141 TA	130	/* Count will be initialised to next expire for all CPU's */
eb9b5141 TA	131	initcount = atomic_read(&count_reference);
39b8d525	132
39b8d525 RB	133	for (i = 0; i < NR_LOOPS; i++) {
39b8d525 RB	134	atomic_inc(&count_count_start);
cf9bfe55	135	while (atomic_read(&count_count_start) != 2)
39b8d525 RB	136	mb();
	137
	138	/*
	139	* Everyone initialises count in the last loop:
	140	*/
	141	if (i == NR_LOOPS-1)
	142	write_c0_count(initcount);
	143
	144	atomic_inc(&count_count_stop);
cf9bfe55	145	while (atomic_read(&count_count_stop) != 2)
39b8d525 RB	146	mb();
	147	}
	148	/* Arrange for an interrupt in a short while */
	149	write_c0_compare(read_c0_count() + COUNTON);
39b8d525 RB	150	}
39b8d525 RB	151	#undef NR_LOOPS