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1da177e4 LT |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * Copyright (C) 1994 - 1999, 2000, 01 Ralf Baechle | |
7 | * Copyright (C) 1995, 1996 Paul M. Antoine | |
8 | * Copyright (C) 1998 Ulf Carlsson | |
9 | * Copyright (C) 1999 Silicon Graphics, Inc. | |
10 | * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com | |
11 | * Copyright (C) 2000, 01 MIPS Technologies, Inc. | |
12 | * Copyright (C) 2002, 2003, 2004 Maciej W. Rozycki | |
13 | */ | |
14 | #include <linux/config.h> | |
15 | #include <linux/init.h> | |
16 | #include <linux/mm.h> | |
17 | #include <linux/module.h> | |
18 | #include <linux/sched.h> | |
19 | #include <linux/smp.h> | |
20 | #include <linux/smp_lock.h> | |
21 | #include <linux/spinlock.h> | |
22 | #include <linux/kallsyms.h> | |
23 | ||
24 | #include <asm/bootinfo.h> | |
25 | #include <asm/branch.h> | |
26 | #include <asm/break.h> | |
27 | #include <asm/cpu.h> | |
e50c0a8f | 28 | #include <asm/dsp.h> |
1da177e4 LT |
29 | #include <asm/fpu.h> |
30 | #include <asm/module.h> | |
31 | #include <asm/pgtable.h> | |
32 | #include <asm/ptrace.h> | |
33 | #include <asm/sections.h> | |
34 | #include <asm/system.h> | |
35 | #include <asm/tlbdebug.h> | |
36 | #include <asm/traps.h> | |
37 | #include <asm/uaccess.h> | |
38 | #include <asm/mmu_context.h> | |
39 | #include <asm/watch.h> | |
40 | #include <asm/types.h> | |
41 | ||
42 | extern asmlinkage void handle_tlbm(void); | |
43 | extern asmlinkage void handle_tlbl(void); | |
44 | extern asmlinkage void handle_tlbs(void); | |
45 | extern asmlinkage void handle_adel(void); | |
46 | extern asmlinkage void handle_ades(void); | |
47 | extern asmlinkage void handle_ibe(void); | |
48 | extern asmlinkage void handle_dbe(void); | |
49 | extern asmlinkage void handle_sys(void); | |
50 | extern asmlinkage void handle_bp(void); | |
51 | extern asmlinkage void handle_ri(void); | |
52 | extern asmlinkage void handle_cpu(void); | |
53 | extern asmlinkage void handle_ov(void); | |
54 | extern asmlinkage void handle_tr(void); | |
55 | extern asmlinkage void handle_fpe(void); | |
56 | extern asmlinkage void handle_mdmx(void); | |
57 | extern asmlinkage void handle_watch(void); | |
e50c0a8f | 58 | extern asmlinkage void handle_dsp(void); |
1da177e4 LT |
59 | extern asmlinkage void handle_mcheck(void); |
60 | extern asmlinkage void handle_reserved(void); | |
61 | ||
62 | extern int fpu_emulator_cop1Handler(int xcptno, struct pt_regs *xcp, | |
63 | struct mips_fpu_soft_struct *ctx); | |
64 | ||
65 | void (*board_be_init)(void); | |
66 | int (*board_be_handler)(struct pt_regs *regs, int is_fixup); | |
67 | ||
68 | /* | |
69 | * These constant is for searching for possible module text segments. | |
70 | * MODULE_RANGE is a guess of how much space is likely to be vmalloced. | |
71 | */ | |
72 | #define MODULE_RANGE (8*1024*1024) | |
73 | ||
74 | /* | |
75 | * This routine abuses get_user()/put_user() to reference pointers | |
76 | * with at least a bit of error checking ... | |
77 | */ | |
78 | void show_stack(struct task_struct *task, unsigned long *sp) | |
79 | { | |
80 | const int field = 2 * sizeof(unsigned long); | |
81 | long stackdata; | |
82 | int i; | |
83 | ||
84 | if (!sp) { | |
85 | if (task && task != current) | |
86 | sp = (unsigned long *) task->thread.reg29; | |
87 | else | |
88 | sp = (unsigned long *) &sp; | |
89 | } | |
90 | ||
91 | printk("Stack :"); | |
92 | i = 0; | |
93 | while ((unsigned long) sp & (PAGE_SIZE - 1)) { | |
94 | if (i && ((i % (64 / field)) == 0)) | |
95 | printk("\n "); | |
96 | if (i > 39) { | |
97 | printk(" ..."); | |
98 | break; | |
99 | } | |
100 | ||
101 | if (__get_user(stackdata, sp++)) { | |
102 | printk(" (Bad stack address)"); | |
103 | break; | |
104 | } | |
105 | ||
106 | printk(" %0*lx", field, stackdata); | |
107 | i++; | |
108 | } | |
109 | printk("\n"); | |
110 | } | |
111 | ||
112 | void show_trace(struct task_struct *task, unsigned long *stack) | |
113 | { | |
114 | const int field = 2 * sizeof(unsigned long); | |
115 | unsigned long addr; | |
116 | ||
117 | if (!stack) { | |
118 | if (task && task != current) | |
119 | stack = (unsigned long *) task->thread.reg29; | |
120 | else | |
121 | stack = (unsigned long *) &stack; | |
122 | } | |
123 | ||
124 | printk("Call Trace:"); | |
125 | #ifdef CONFIG_KALLSYMS | |
126 | printk("\n"); | |
127 | #endif | |
128 | while (!kstack_end(stack)) { | |
129 | addr = *stack++; | |
130 | if (__kernel_text_address(addr)) { | |
131 | printk(" [<%0*lx>] ", field, addr); | |
132 | print_symbol("%s\n", addr); | |
133 | } | |
134 | } | |
135 | printk("\n"); | |
136 | } | |
137 | ||
138 | /* | |
139 | * The architecture-independent dump_stack generator | |
140 | */ | |
141 | void dump_stack(void) | |
142 | { | |
143 | unsigned long stack; | |
144 | ||
145 | show_trace(current, &stack); | |
146 | } | |
147 | ||
148 | EXPORT_SYMBOL(dump_stack); | |
149 | ||
150 | void show_code(unsigned int *pc) | |
151 | { | |
152 | long i; | |
153 | ||
154 | printk("\nCode:"); | |
155 | ||
156 | for(i = -3 ; i < 6 ; i++) { | |
157 | unsigned int insn; | |
158 | if (__get_user(insn, pc + i)) { | |
159 | printk(" (Bad address in epc)\n"); | |
160 | break; | |
161 | } | |
162 | printk("%c%08x%c", (i?' ':'<'), insn, (i?' ':'>')); | |
163 | } | |
164 | } | |
165 | ||
166 | void show_regs(struct pt_regs *regs) | |
167 | { | |
168 | const int field = 2 * sizeof(unsigned long); | |
169 | unsigned int cause = regs->cp0_cause; | |
170 | int i; | |
171 | ||
172 | printk("Cpu %d\n", smp_processor_id()); | |
173 | ||
174 | /* | |
175 | * Saved main processor registers | |
176 | */ | |
177 | for (i = 0; i < 32; ) { | |
178 | if ((i % 4) == 0) | |
179 | printk("$%2d :", i); | |
180 | if (i == 0) | |
181 | printk(" %0*lx", field, 0UL); | |
182 | else if (i == 26 || i == 27) | |
183 | printk(" %*s", field, ""); | |
184 | else | |
185 | printk(" %0*lx", field, regs->regs[i]); | |
186 | ||
187 | i++; | |
188 | if ((i % 4) == 0) | |
189 | printk("\n"); | |
190 | } | |
191 | ||
192 | printk("Hi : %0*lx\n", field, regs->hi); | |
193 | printk("Lo : %0*lx\n", field, regs->lo); | |
194 | ||
195 | /* | |
196 | * Saved cp0 registers | |
197 | */ | |
198 | printk("epc : %0*lx ", field, regs->cp0_epc); | |
199 | print_symbol("%s ", regs->cp0_epc); | |
200 | printk(" %s\n", print_tainted()); | |
201 | printk("ra : %0*lx ", field, regs->regs[31]); | |
202 | print_symbol("%s\n", regs->regs[31]); | |
203 | ||
204 | printk("Status: %08x ", (uint32_t) regs->cp0_status); | |
205 | ||
206 | if (regs->cp0_status & ST0_KX) | |
207 | printk("KX "); | |
208 | if (regs->cp0_status & ST0_SX) | |
209 | printk("SX "); | |
210 | if (regs->cp0_status & ST0_UX) | |
211 | printk("UX "); | |
212 | switch (regs->cp0_status & ST0_KSU) { | |
213 | case KSU_USER: | |
214 | printk("USER "); | |
215 | break; | |
216 | case KSU_SUPERVISOR: | |
217 | printk("SUPERVISOR "); | |
218 | break; | |
219 | case KSU_KERNEL: | |
220 | printk("KERNEL "); | |
221 | break; | |
222 | default: | |
223 | printk("BAD_MODE "); | |
224 | break; | |
225 | } | |
226 | if (regs->cp0_status & ST0_ERL) | |
227 | printk("ERL "); | |
228 | if (regs->cp0_status & ST0_EXL) | |
229 | printk("EXL "); | |
230 | if (regs->cp0_status & ST0_IE) | |
231 | printk("IE "); | |
232 | printk("\n"); | |
233 | ||
234 | printk("Cause : %08x\n", cause); | |
235 | ||
236 | cause = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE; | |
237 | if (1 <= cause && cause <= 5) | |
238 | printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr); | |
239 | ||
240 | printk("PrId : %08x\n", read_c0_prid()); | |
241 | } | |
242 | ||
243 | void show_registers(struct pt_regs *regs) | |
244 | { | |
245 | show_regs(regs); | |
246 | print_modules(); | |
247 | printk("Process %s (pid: %d, threadinfo=%p, task=%p)\n", | |
248 | current->comm, current->pid, current_thread_info(), current); | |
249 | show_stack(current, (long *) regs->regs[29]); | |
250 | show_trace(current, (long *) regs->regs[29]); | |
251 | show_code((unsigned int *) regs->cp0_epc); | |
252 | printk("\n"); | |
253 | } | |
254 | ||
255 | static DEFINE_SPINLOCK(die_lock); | |
256 | ||
260c9673 MR |
257 | NORET_TYPE void ATTRIB_NORET __die(const char * str, struct pt_regs * regs, |
258 | const char * file, const char * func, | |
259 | unsigned long line) | |
1da177e4 LT |
260 | { |
261 | static int die_counter; | |
262 | ||
263 | console_verbose(); | |
264 | spin_lock_irq(&die_lock); | |
265 | printk("%s", str); | |
266 | if (file && func) | |
267 | printk(" in %s:%s, line %ld", file, func, line); | |
268 | printk("[#%d]:\n", ++die_counter); | |
269 | show_registers(regs); | |
270 | spin_unlock_irq(&die_lock); | |
271 | do_exit(SIGSEGV); | |
272 | } | |
273 | ||
274 | void __die_if_kernel(const char * str, struct pt_regs * regs, | |
275 | const char * file, const char * func, unsigned long line) | |
276 | { | |
277 | if (!user_mode(regs)) | |
278 | __die(str, regs, file, func, line); | |
279 | } | |
280 | ||
281 | extern const struct exception_table_entry __start___dbe_table[]; | |
282 | extern const struct exception_table_entry __stop___dbe_table[]; | |
283 | ||
284 | void __declare_dbe_table(void) | |
285 | { | |
286 | __asm__ __volatile__( | |
287 | ".section\t__dbe_table,\"a\"\n\t" | |
288 | ".previous" | |
289 | ); | |
290 | } | |
291 | ||
292 | /* Given an address, look for it in the exception tables. */ | |
293 | static const struct exception_table_entry *search_dbe_tables(unsigned long addr) | |
294 | { | |
295 | const struct exception_table_entry *e; | |
296 | ||
297 | e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr); | |
298 | if (!e) | |
299 | e = search_module_dbetables(addr); | |
300 | return e; | |
301 | } | |
302 | ||
303 | asmlinkage void do_be(struct pt_regs *regs) | |
304 | { | |
305 | const int field = 2 * sizeof(unsigned long); | |
306 | const struct exception_table_entry *fixup = NULL; | |
307 | int data = regs->cp0_cause & 4; | |
308 | int action = MIPS_BE_FATAL; | |
309 | ||
310 | /* XXX For now. Fixme, this searches the wrong table ... */ | |
311 | if (data && !user_mode(regs)) | |
312 | fixup = search_dbe_tables(exception_epc(regs)); | |
313 | ||
314 | if (fixup) | |
315 | action = MIPS_BE_FIXUP; | |
316 | ||
317 | if (board_be_handler) | |
318 | action = board_be_handler(regs, fixup != 0); | |
319 | ||
320 | switch (action) { | |
321 | case MIPS_BE_DISCARD: | |
322 | return; | |
323 | case MIPS_BE_FIXUP: | |
324 | if (fixup) { | |
325 | regs->cp0_epc = fixup->nextinsn; | |
326 | return; | |
327 | } | |
328 | break; | |
329 | default: | |
330 | break; | |
331 | } | |
332 | ||
333 | /* | |
334 | * Assume it would be too dangerous to continue ... | |
335 | */ | |
336 | printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n", | |
337 | data ? "Data" : "Instruction", | |
338 | field, regs->cp0_epc, field, regs->regs[31]); | |
339 | die_if_kernel("Oops", regs); | |
340 | force_sig(SIGBUS, current); | |
341 | } | |
342 | ||
343 | static inline int get_insn_opcode(struct pt_regs *regs, unsigned int *opcode) | |
344 | { | |
fe00f943 | 345 | unsigned int __user *epc; |
1da177e4 | 346 | |
fe00f943 | 347 | epc = (unsigned int __user *) regs->cp0_epc + |
1da177e4 LT |
348 | ((regs->cp0_cause & CAUSEF_BD) != 0); |
349 | if (!get_user(*opcode, epc)) | |
350 | return 0; | |
351 | ||
352 | force_sig(SIGSEGV, current); | |
353 | return 1; | |
354 | } | |
355 | ||
356 | /* | |
357 | * ll/sc emulation | |
358 | */ | |
359 | ||
360 | #define OPCODE 0xfc000000 | |
361 | #define BASE 0x03e00000 | |
362 | #define RT 0x001f0000 | |
363 | #define OFFSET 0x0000ffff | |
364 | #define LL 0xc0000000 | |
365 | #define SC 0xe0000000 | |
3c37026d RB |
366 | #define SPEC3 0x7c000000 |
367 | #define RD 0x0000f800 | |
368 | #define FUNC 0x0000003f | |
369 | #define RDHWR 0x0000003b | |
1da177e4 LT |
370 | |
371 | /* | |
372 | * The ll_bit is cleared by r*_switch.S | |
373 | */ | |
374 | ||
375 | unsigned long ll_bit; | |
376 | ||
377 | static struct task_struct *ll_task = NULL; | |
378 | ||
379 | static inline void simulate_ll(struct pt_regs *regs, unsigned int opcode) | |
380 | { | |
fe00f943 | 381 | unsigned long value, __user *vaddr; |
1da177e4 LT |
382 | long offset; |
383 | int signal = 0; | |
384 | ||
385 | /* | |
386 | * analyse the ll instruction that just caused a ri exception | |
387 | * and put the referenced address to addr. | |
388 | */ | |
389 | ||
390 | /* sign extend offset */ | |
391 | offset = opcode & OFFSET; | |
392 | offset <<= 16; | |
393 | offset >>= 16; | |
394 | ||
fe00f943 RB |
395 | vaddr = (unsigned long __user *) |
396 | ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); | |
1da177e4 LT |
397 | |
398 | if ((unsigned long)vaddr & 3) { | |
399 | signal = SIGBUS; | |
400 | goto sig; | |
401 | } | |
402 | if (get_user(value, vaddr)) { | |
403 | signal = SIGSEGV; | |
404 | goto sig; | |
405 | } | |
406 | ||
407 | preempt_disable(); | |
408 | ||
409 | if (ll_task == NULL || ll_task == current) { | |
410 | ll_bit = 1; | |
411 | } else { | |
412 | ll_bit = 0; | |
413 | } | |
414 | ll_task = current; | |
415 | ||
416 | preempt_enable(); | |
417 | ||
6dd04688 RB |
418 | compute_return_epc(regs); |
419 | ||
1da177e4 LT |
420 | regs->regs[(opcode & RT) >> 16] = value; |
421 | ||
1da177e4 LT |
422 | return; |
423 | ||
424 | sig: | |
425 | force_sig(signal, current); | |
426 | } | |
427 | ||
428 | static inline void simulate_sc(struct pt_regs *regs, unsigned int opcode) | |
429 | { | |
fe00f943 RB |
430 | unsigned long __user *vaddr; |
431 | unsigned long reg; | |
1da177e4 LT |
432 | long offset; |
433 | int signal = 0; | |
434 | ||
435 | /* | |
436 | * analyse the sc instruction that just caused a ri exception | |
437 | * and put the referenced address to addr. | |
438 | */ | |
439 | ||
440 | /* sign extend offset */ | |
441 | offset = opcode & OFFSET; | |
442 | offset <<= 16; | |
443 | offset >>= 16; | |
444 | ||
fe00f943 RB |
445 | vaddr = (unsigned long __user *) |
446 | ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); | |
1da177e4 LT |
447 | reg = (opcode & RT) >> 16; |
448 | ||
449 | if ((unsigned long)vaddr & 3) { | |
450 | signal = SIGBUS; | |
451 | goto sig; | |
452 | } | |
453 | ||
454 | preempt_disable(); | |
455 | ||
456 | if (ll_bit == 0 || ll_task != current) { | |
05b8042a | 457 | compute_return_epc(regs); |
1da177e4 LT |
458 | regs->regs[reg] = 0; |
459 | preempt_enable(); | |
1da177e4 LT |
460 | return; |
461 | } | |
462 | ||
463 | preempt_enable(); | |
464 | ||
465 | if (put_user(regs->regs[reg], vaddr)) { | |
466 | signal = SIGSEGV; | |
467 | goto sig; | |
468 | } | |
469 | ||
6dd04688 | 470 | compute_return_epc(regs); |
1da177e4 LT |
471 | regs->regs[reg] = 1; |
472 | ||
1da177e4 LT |
473 | return; |
474 | ||
475 | sig: | |
476 | force_sig(signal, current); | |
477 | } | |
478 | ||
479 | /* | |
480 | * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both | |
481 | * opcodes are supposed to result in coprocessor unusable exceptions if | |
482 | * executed on ll/sc-less processors. That's the theory. In practice a | |
483 | * few processors such as NEC's VR4100 throw reserved instruction exceptions | |
484 | * instead, so we're doing the emulation thing in both exception handlers. | |
485 | */ | |
486 | static inline int simulate_llsc(struct pt_regs *regs) | |
487 | { | |
488 | unsigned int opcode; | |
489 | ||
490 | if (unlikely(get_insn_opcode(regs, &opcode))) | |
491 | return -EFAULT; | |
492 | ||
493 | if ((opcode & OPCODE) == LL) { | |
494 | simulate_ll(regs, opcode); | |
495 | return 0; | |
496 | } | |
497 | if ((opcode & OPCODE) == SC) { | |
498 | simulate_sc(regs, opcode); | |
499 | return 0; | |
500 | } | |
501 | ||
502 | return -EFAULT; /* Strange things going on ... */ | |
503 | } | |
504 | ||
3c37026d RB |
505 | /* |
506 | * Simulate trapping 'rdhwr' instructions to provide user accessible | |
507 | * registers not implemented in hardware. The only current use of this | |
508 | * is the thread area pointer. | |
509 | */ | |
510 | static inline int simulate_rdhwr(struct pt_regs *regs) | |
511 | { | |
512 | struct thread_info *ti = current->thread_info; | |
513 | unsigned int opcode; | |
514 | ||
515 | if (unlikely(get_insn_opcode(regs, &opcode))) | |
516 | return -EFAULT; | |
517 | ||
518 | if (unlikely(compute_return_epc(regs))) | |
519 | return -EFAULT; | |
520 | ||
521 | if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) { | |
522 | int rd = (opcode & RD) >> 11; | |
523 | int rt = (opcode & RT) >> 16; | |
524 | switch (rd) { | |
525 | case 29: | |
526 | regs->regs[rt] = ti->tp_value; | |
527 | break; | |
528 | default: | |
529 | return -EFAULT; | |
530 | } | |
531 | } | |
532 | ||
533 | return 0; | |
534 | } | |
535 | ||
1da177e4 LT |
536 | asmlinkage void do_ov(struct pt_regs *regs) |
537 | { | |
538 | siginfo_t info; | |
539 | ||
540 | info.si_code = FPE_INTOVF; | |
541 | info.si_signo = SIGFPE; | |
542 | info.si_errno = 0; | |
fe00f943 | 543 | info.si_addr = (void __user *) regs->cp0_epc; |
1da177e4 LT |
544 | force_sig_info(SIGFPE, &info, current); |
545 | } | |
546 | ||
547 | /* | |
548 | * XXX Delayed fp exceptions when doing a lazy ctx switch XXX | |
549 | */ | |
550 | asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31) | |
551 | { | |
552 | if (fcr31 & FPU_CSR_UNI_X) { | |
553 | int sig; | |
554 | ||
555 | preempt_disable(); | |
556 | ||
cd21dfcf RB |
557 | #ifdef CONFIG_PREEMPT |
558 | if (!is_fpu_owner()) { | |
559 | /* We might lose fpu before disabling preempt... */ | |
560 | own_fpu(); | |
561 | BUG_ON(!used_math()); | |
562 | restore_fp(current); | |
563 | } | |
564 | #endif | |
1da177e4 LT |
565 | /* |
566 | * Unimplemented operation exception. If we've got the full | |
567 | * software emulator on-board, let's use it... | |
568 | * | |
569 | * Force FPU to dump state into task/thread context. We're | |
570 | * moving a lot of data here for what is probably a single | |
571 | * instruction, but the alternative is to pre-decode the FP | |
572 | * register operands before invoking the emulator, which seems | |
573 | * a bit extreme for what should be an infrequent event. | |
574 | */ | |
575 | save_fp(current); | |
cd21dfcf RB |
576 | /* Ensure 'resume' not overwrite saved fp context again. */ |
577 | lose_fpu(); | |
578 | ||
579 | preempt_enable(); | |
1da177e4 LT |
580 | |
581 | /* Run the emulator */ | |
582 | sig = fpu_emulator_cop1Handler (0, regs, | |
583 | ¤t->thread.fpu.soft); | |
584 | ||
cd21dfcf RB |
585 | preempt_disable(); |
586 | ||
587 | own_fpu(); /* Using the FPU again. */ | |
1da177e4 LT |
588 | /* |
589 | * We can't allow the emulated instruction to leave any of | |
590 | * the cause bit set in $fcr31. | |
591 | */ | |
592 | current->thread.fpu.soft.fcr31 &= ~FPU_CSR_ALL_X; | |
593 | ||
594 | /* Restore the hardware register state */ | |
595 | restore_fp(current); | |
596 | ||
597 | preempt_enable(); | |
598 | ||
599 | /* If something went wrong, signal */ | |
600 | if (sig) | |
601 | force_sig(sig, current); | |
602 | ||
603 | return; | |
604 | } | |
605 | ||
606 | force_sig(SIGFPE, current); | |
607 | } | |
608 | ||
609 | asmlinkage void do_bp(struct pt_regs *regs) | |
610 | { | |
611 | unsigned int opcode, bcode; | |
612 | siginfo_t info; | |
613 | ||
614 | die_if_kernel("Break instruction in kernel code", regs); | |
615 | ||
616 | if (get_insn_opcode(regs, &opcode)) | |
617 | return; | |
618 | ||
619 | /* | |
620 | * There is the ancient bug in the MIPS assemblers that the break | |
621 | * code starts left to bit 16 instead to bit 6 in the opcode. | |
622 | * Gas is bug-compatible, but not always, grrr... | |
623 | * We handle both cases with a simple heuristics. --macro | |
624 | */ | |
625 | bcode = ((opcode >> 6) & ((1 << 20) - 1)); | |
626 | if (bcode < (1 << 10)) | |
627 | bcode <<= 10; | |
628 | ||
629 | /* | |
630 | * (A short test says that IRIX 5.3 sends SIGTRAP for all break | |
631 | * insns, even for break codes that indicate arithmetic failures. | |
632 | * Weird ...) | |
633 | * But should we continue the brokenness??? --macro | |
634 | */ | |
635 | switch (bcode) { | |
636 | case BRK_OVERFLOW << 10: | |
637 | case BRK_DIVZERO << 10: | |
638 | if (bcode == (BRK_DIVZERO << 10)) | |
639 | info.si_code = FPE_INTDIV; | |
640 | else | |
641 | info.si_code = FPE_INTOVF; | |
642 | info.si_signo = SIGFPE; | |
643 | info.si_errno = 0; | |
fe00f943 | 644 | info.si_addr = (void __user *) regs->cp0_epc; |
1da177e4 LT |
645 | force_sig_info(SIGFPE, &info, current); |
646 | break; | |
647 | default: | |
648 | force_sig(SIGTRAP, current); | |
649 | } | |
650 | } | |
651 | ||
652 | asmlinkage void do_tr(struct pt_regs *regs) | |
653 | { | |
654 | unsigned int opcode, tcode = 0; | |
655 | siginfo_t info; | |
656 | ||
657 | die_if_kernel("Trap instruction in kernel code", regs); | |
658 | ||
659 | if (get_insn_opcode(regs, &opcode)) | |
660 | return; | |
661 | ||
662 | /* Immediate versions don't provide a code. */ | |
663 | if (!(opcode & OPCODE)) | |
664 | tcode = ((opcode >> 6) & ((1 << 10) - 1)); | |
665 | ||
666 | /* | |
667 | * (A short test says that IRIX 5.3 sends SIGTRAP for all trap | |
668 | * insns, even for trap codes that indicate arithmetic failures. | |
669 | * Weird ...) | |
670 | * But should we continue the brokenness??? --macro | |
671 | */ | |
672 | switch (tcode) { | |
673 | case BRK_OVERFLOW: | |
674 | case BRK_DIVZERO: | |
675 | if (tcode == BRK_DIVZERO) | |
676 | info.si_code = FPE_INTDIV; | |
677 | else | |
678 | info.si_code = FPE_INTOVF; | |
679 | info.si_signo = SIGFPE; | |
680 | info.si_errno = 0; | |
fe00f943 | 681 | info.si_addr = (void __user *) regs->cp0_epc; |
1da177e4 LT |
682 | force_sig_info(SIGFPE, &info, current); |
683 | break; | |
684 | default: | |
685 | force_sig(SIGTRAP, current); | |
686 | } | |
687 | } | |
688 | ||
689 | asmlinkage void do_ri(struct pt_regs *regs) | |
690 | { | |
691 | die_if_kernel("Reserved instruction in kernel code", regs); | |
692 | ||
693 | if (!cpu_has_llsc) | |
694 | if (!simulate_llsc(regs)) | |
695 | return; | |
696 | ||
3c37026d RB |
697 | if (!simulate_rdhwr(regs)) |
698 | return; | |
699 | ||
1da177e4 LT |
700 | force_sig(SIGILL, current); |
701 | } | |
702 | ||
703 | asmlinkage void do_cpu(struct pt_regs *regs) | |
704 | { | |
705 | unsigned int cpid; | |
706 | ||
707 | die_if_kernel("do_cpu invoked from kernel context!", regs); | |
708 | ||
709 | cpid = (regs->cp0_cause >> CAUSEB_CE) & 3; | |
710 | ||
711 | switch (cpid) { | |
712 | case 0: | |
3c37026d RB |
713 | if (!cpu_has_llsc) |
714 | if (!simulate_llsc(regs)) | |
715 | return; | |
1da177e4 | 716 | |
3c37026d | 717 | if (!simulate_rdhwr(regs)) |
1da177e4 | 718 | return; |
3c37026d | 719 | |
1da177e4 LT |
720 | break; |
721 | ||
722 | case 1: | |
723 | preempt_disable(); | |
724 | ||
725 | own_fpu(); | |
726 | if (used_math()) { /* Using the FPU again. */ | |
727 | restore_fp(current); | |
728 | } else { /* First time FPU user. */ | |
729 | init_fpu(); | |
730 | set_used_math(); | |
731 | } | |
732 | ||
cd21dfcf RB |
733 | preempt_enable(); |
734 | ||
1da177e4 LT |
735 | if (!cpu_has_fpu) { |
736 | int sig = fpu_emulator_cop1Handler(0, regs, | |
737 | ¤t->thread.fpu.soft); | |
738 | if (sig) | |
739 | force_sig(sig, current); | |
740 | } | |
741 | ||
1da177e4 LT |
742 | return; |
743 | ||
744 | case 2: | |
745 | case 3: | |
746 | break; | |
747 | } | |
748 | ||
749 | force_sig(SIGILL, current); | |
750 | } | |
751 | ||
752 | asmlinkage void do_mdmx(struct pt_regs *regs) | |
753 | { | |
754 | force_sig(SIGILL, current); | |
755 | } | |
756 | ||
757 | asmlinkage void do_watch(struct pt_regs *regs) | |
758 | { | |
759 | /* | |
760 | * We use the watch exception where available to detect stack | |
761 | * overflows. | |
762 | */ | |
763 | dump_tlb_all(); | |
764 | show_regs(regs); | |
765 | panic("Caught WATCH exception - probably caused by stack overflow."); | |
766 | } | |
767 | ||
768 | asmlinkage void do_mcheck(struct pt_regs *regs) | |
769 | { | |
770 | show_regs(regs); | |
771 | dump_tlb_all(); | |
772 | /* | |
773 | * Some chips may have other causes of machine check (e.g. SB1 | |
774 | * graduation timer) | |
775 | */ | |
776 | panic("Caught Machine Check exception - %scaused by multiple " | |
777 | "matching entries in the TLB.", | |
778 | (regs->cp0_status & ST0_TS) ? "" : "not "); | |
779 | } | |
780 | ||
e50c0a8f RB |
781 | asmlinkage void do_dsp(struct pt_regs *regs) |
782 | { | |
783 | if (cpu_has_dsp) | |
784 | panic("Unexpected DSP exception\n"); | |
785 | ||
786 | force_sig(SIGILL, current); | |
787 | } | |
788 | ||
1da177e4 LT |
789 | asmlinkage void do_reserved(struct pt_regs *regs) |
790 | { | |
791 | /* | |
792 | * Game over - no way to handle this if it ever occurs. Most probably | |
793 | * caused by a new unknown cpu type or after another deadly | |
794 | * hard/software error. | |
795 | */ | |
796 | show_regs(regs); | |
797 | panic("Caught reserved exception %ld - should not happen.", | |
798 | (regs->cp0_cause & 0x7f) >> 2); | |
799 | } | |
800 | ||
801 | /* | |
802 | * Some MIPS CPUs can enable/disable for cache parity detection, but do | |
803 | * it different ways. | |
804 | */ | |
805 | static inline void parity_protection_init(void) | |
806 | { | |
807 | switch (current_cpu_data.cputype) { | |
808 | case CPU_24K: | |
1da177e4 | 809 | case CPU_5KC: |
14f18b7f RB |
810 | write_c0_ecc(0x80000000); |
811 | back_to_back_c0_hazard(); | |
812 | /* Set the PE bit (bit 31) in the c0_errctl register. */ | |
813 | printk(KERN_INFO "Cache parity protection %sabled\n", | |
814 | (read_c0_ecc() & 0x80000000) ? "en" : "dis"); | |
1da177e4 LT |
815 | break; |
816 | case CPU_20KC: | |
817 | case CPU_25KF: | |
818 | /* Clear the DE bit (bit 16) in the c0_status register. */ | |
819 | printk(KERN_INFO "Enable cache parity protection for " | |
820 | "MIPS 20KC/25KF CPUs.\n"); | |
821 | clear_c0_status(ST0_DE); | |
822 | break; | |
823 | default: | |
824 | break; | |
825 | } | |
826 | } | |
827 | ||
828 | asmlinkage void cache_parity_error(void) | |
829 | { | |
830 | const int field = 2 * sizeof(unsigned long); | |
831 | unsigned int reg_val; | |
832 | ||
833 | /* For the moment, report the problem and hang. */ | |
834 | printk("Cache error exception:\n"); | |
835 | printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc()); | |
836 | reg_val = read_c0_cacheerr(); | |
837 | printk("c0_cacheerr == %08x\n", reg_val); | |
838 | ||
839 | printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n", | |
840 | reg_val & (1<<30) ? "secondary" : "primary", | |
841 | reg_val & (1<<31) ? "data" : "insn"); | |
842 | printk("Error bits: %s%s%s%s%s%s%s\n", | |
843 | reg_val & (1<<29) ? "ED " : "", | |
844 | reg_val & (1<<28) ? "ET " : "", | |
845 | reg_val & (1<<26) ? "EE " : "", | |
846 | reg_val & (1<<25) ? "EB " : "", | |
847 | reg_val & (1<<24) ? "EI " : "", | |
848 | reg_val & (1<<23) ? "E1 " : "", | |
849 | reg_val & (1<<22) ? "E0 " : ""); | |
850 | printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1)); | |
851 | ||
852 | #if defined(CONFIG_CPU_MIPS32) || defined (CONFIG_CPU_MIPS64) | |
853 | if (reg_val & (1<<22)) | |
854 | printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0()); | |
855 | ||
856 | if (reg_val & (1<<23)) | |
857 | printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1()); | |
858 | #endif | |
859 | ||
860 | panic("Can't handle the cache error!"); | |
861 | } | |
862 | ||
863 | /* | |
864 | * SDBBP EJTAG debug exception handler. | |
865 | * We skip the instruction and return to the next instruction. | |
866 | */ | |
867 | void ejtag_exception_handler(struct pt_regs *regs) | |
868 | { | |
869 | const int field = 2 * sizeof(unsigned long); | |
870 | unsigned long depc, old_epc; | |
871 | unsigned int debug; | |
872 | ||
873 | printk("SDBBP EJTAG debug exception - not handled yet, just ignored!\n"); | |
874 | depc = read_c0_depc(); | |
875 | debug = read_c0_debug(); | |
876 | printk("c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug); | |
877 | if (debug & 0x80000000) { | |
878 | /* | |
879 | * In branch delay slot. | |
880 | * We cheat a little bit here and use EPC to calculate the | |
881 | * debug return address (DEPC). EPC is restored after the | |
882 | * calculation. | |
883 | */ | |
884 | old_epc = regs->cp0_epc; | |
885 | regs->cp0_epc = depc; | |
886 | __compute_return_epc(regs); | |
887 | depc = regs->cp0_epc; | |
888 | regs->cp0_epc = old_epc; | |
889 | } else | |
890 | depc += 4; | |
891 | write_c0_depc(depc); | |
892 | ||
893 | #if 0 | |
894 | printk("\n\n----- Enable EJTAG single stepping ----\n\n"); | |
895 | write_c0_debug(debug | 0x100); | |
896 | #endif | |
897 | } | |
898 | ||
899 | /* | |
900 | * NMI exception handler. | |
901 | */ | |
902 | void nmi_exception_handler(struct pt_regs *regs) | |
903 | { | |
904 | printk("NMI taken!!!!\n"); | |
905 | die("NMI", regs); | |
906 | while(1) ; | |
907 | } | |
908 | ||
909 | unsigned long exception_handlers[32]; | |
910 | ||
911 | /* | |
912 | * As a side effect of the way this is implemented we're limited | |
913 | * to interrupt handlers in the address range from | |
914 | * KSEG0 <= x < KSEG0 + 256mb on the Nevada. Oh well ... | |
915 | */ | |
916 | void *set_except_vector(int n, void *addr) | |
917 | { | |
918 | unsigned long handler = (unsigned long) addr; | |
919 | unsigned long old_handler = exception_handlers[n]; | |
920 | ||
921 | exception_handlers[n] = handler; | |
922 | if (n == 0 && cpu_has_divec) { | |
923 | *(volatile u32 *)(CAC_BASE + 0x200) = 0x08000000 | | |
924 | (0x03ffffff & (handler >> 2)); | |
925 | flush_icache_range(CAC_BASE + 0x200, CAC_BASE + 0x204); | |
926 | } | |
927 | return (void *)old_handler; | |
928 | } | |
929 | ||
930 | /* | |
931 | * This is used by native signal handling | |
932 | */ | |
933 | asmlinkage int (*save_fp_context)(struct sigcontext *sc); | |
934 | asmlinkage int (*restore_fp_context)(struct sigcontext *sc); | |
935 | ||
936 | extern asmlinkage int _save_fp_context(struct sigcontext *sc); | |
937 | extern asmlinkage int _restore_fp_context(struct sigcontext *sc); | |
938 | ||
939 | extern asmlinkage int fpu_emulator_save_context(struct sigcontext *sc); | |
940 | extern asmlinkage int fpu_emulator_restore_context(struct sigcontext *sc); | |
941 | ||
942 | static inline void signal_init(void) | |
943 | { | |
944 | if (cpu_has_fpu) { | |
945 | save_fp_context = _save_fp_context; | |
946 | restore_fp_context = _restore_fp_context; | |
947 | } else { | |
948 | save_fp_context = fpu_emulator_save_context; | |
949 | restore_fp_context = fpu_emulator_restore_context; | |
950 | } | |
951 | } | |
952 | ||
953 | #ifdef CONFIG_MIPS32_COMPAT | |
954 | ||
955 | /* | |
956 | * This is used by 32-bit signal stuff on the 64-bit kernel | |
957 | */ | |
958 | asmlinkage int (*save_fp_context32)(struct sigcontext32 *sc); | |
959 | asmlinkage int (*restore_fp_context32)(struct sigcontext32 *sc); | |
960 | ||
961 | extern asmlinkage int _save_fp_context32(struct sigcontext32 *sc); | |
962 | extern asmlinkage int _restore_fp_context32(struct sigcontext32 *sc); | |
963 | ||
964 | extern asmlinkage int fpu_emulator_save_context32(struct sigcontext32 *sc); | |
965 | extern asmlinkage int fpu_emulator_restore_context32(struct sigcontext32 *sc); | |
966 | ||
967 | static inline void signal32_init(void) | |
968 | { | |
969 | if (cpu_has_fpu) { | |
970 | save_fp_context32 = _save_fp_context32; | |
971 | restore_fp_context32 = _restore_fp_context32; | |
972 | } else { | |
973 | save_fp_context32 = fpu_emulator_save_context32; | |
974 | restore_fp_context32 = fpu_emulator_restore_context32; | |
975 | } | |
976 | } | |
977 | #endif | |
978 | ||
979 | extern void cpu_cache_init(void); | |
980 | extern void tlb_init(void); | |
981 | ||
982 | void __init per_cpu_trap_init(void) | |
983 | { | |
984 | unsigned int cpu = smp_processor_id(); | |
985 | unsigned int status_set = ST0_CU0; | |
986 | ||
987 | /* | |
988 | * Disable coprocessors and select 32-bit or 64-bit addressing | |
989 | * and the 16/32 or 32/32 FPR register model. Reset the BEV | |
990 | * flag that some firmware may have left set and the TS bit (for | |
991 | * IP27). Set XX for ISA IV code to work. | |
992 | */ | |
875d43e7 | 993 | #ifdef CONFIG_64BIT |
1da177e4 LT |
994 | status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX; |
995 | #endif | |
996 | if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV) | |
997 | status_set |= ST0_XX; | |
e50c0a8f | 998 | change_c0_status(ST0_CU|ST0_MX|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX, |
1da177e4 LT |
999 | status_set); |
1000 | ||
e50c0a8f RB |
1001 | if (cpu_has_dsp) |
1002 | set_c0_status(ST0_MX); | |
1003 | ||
1da177e4 LT |
1004 | /* |
1005 | * Some MIPS CPUs have a dedicated interrupt vector which reduces the | |
1006 | * interrupt processing overhead. Use it where available. | |
1007 | */ | |
1008 | if (cpu_has_divec) | |
1009 | set_c0_cause(CAUSEF_IV); | |
1010 | ||
1011 | cpu_data[cpu].asid_cache = ASID_FIRST_VERSION; | |
1012 | TLBMISS_HANDLER_SETUP(); | |
1013 | ||
1014 | atomic_inc(&init_mm.mm_count); | |
1015 | current->active_mm = &init_mm; | |
1016 | BUG_ON(current->mm); | |
1017 | enter_lazy_tlb(&init_mm, current); | |
1018 | ||
1019 | cpu_cache_init(); | |
1020 | tlb_init(); | |
1021 | } | |
1022 | ||
1023 | void __init trap_init(void) | |
1024 | { | |
1025 | extern char except_vec3_generic, except_vec3_r4000; | |
1026 | extern char except_vec_ejtag_debug; | |
1027 | extern char except_vec4; | |
1028 | unsigned long i; | |
1029 | ||
1030 | per_cpu_trap_init(); | |
1031 | ||
1032 | /* | |
1033 | * Copy the generic exception handlers to their final destination. | |
1034 | * This will be overriden later as suitable for a particular | |
1035 | * configuration. | |
1036 | */ | |
1037 | memcpy((void *)(CAC_BASE + 0x180), &except_vec3_generic, 0x80); | |
1038 | ||
1039 | /* | |
1040 | * Setup default vectors | |
1041 | */ | |
1042 | for (i = 0; i <= 31; i++) | |
1043 | set_except_vector(i, handle_reserved); | |
1044 | ||
1045 | /* | |
1046 | * Copy the EJTAG debug exception vector handler code to it's final | |
1047 | * destination. | |
1048 | */ | |
1049 | if (cpu_has_ejtag) | |
1050 | memcpy((void *)(CAC_BASE + 0x300), &except_vec_ejtag_debug, 0x80); | |
1051 | ||
1052 | /* | |
1053 | * Only some CPUs have the watch exceptions. | |
1054 | */ | |
1055 | if (cpu_has_watch) | |
1056 | set_except_vector(23, handle_watch); | |
1057 | ||
1058 | /* | |
1059 | * Some MIPS CPUs have a dedicated interrupt vector which reduces the | |
1060 | * interrupt processing overhead. Use it where available. | |
1061 | */ | |
1062 | if (cpu_has_divec) | |
1063 | memcpy((void *)(CAC_BASE + 0x200), &except_vec4, 0x8); | |
1064 | ||
1065 | /* | |
1066 | * Some CPUs can enable/disable for cache parity detection, but does | |
1067 | * it different ways. | |
1068 | */ | |
1069 | parity_protection_init(); | |
1070 | ||
1071 | /* | |
1072 | * The Data Bus Errors / Instruction Bus Errors are signaled | |
1073 | * by external hardware. Therefore these two exceptions | |
1074 | * may have board specific handlers. | |
1075 | */ | |
1076 | if (board_be_init) | |
1077 | board_be_init(); | |
1078 | ||
1079 | set_except_vector(1, handle_tlbm); | |
1080 | set_except_vector(2, handle_tlbl); | |
1081 | set_except_vector(3, handle_tlbs); | |
1082 | ||
1083 | set_except_vector(4, handle_adel); | |
1084 | set_except_vector(5, handle_ades); | |
1085 | ||
1086 | set_except_vector(6, handle_ibe); | |
1087 | set_except_vector(7, handle_dbe); | |
1088 | ||
1089 | set_except_vector(8, handle_sys); | |
1090 | set_except_vector(9, handle_bp); | |
1091 | set_except_vector(10, handle_ri); | |
1092 | set_except_vector(11, handle_cpu); | |
1093 | set_except_vector(12, handle_ov); | |
1094 | set_except_vector(13, handle_tr); | |
1da177e4 LT |
1095 | |
1096 | if (current_cpu_data.cputype == CPU_R6000 || | |
1097 | current_cpu_data.cputype == CPU_R6000A) { | |
1098 | /* | |
1099 | * The R6000 is the only R-series CPU that features a machine | |
1100 | * check exception (similar to the R4000 cache error) and | |
1101 | * unaligned ldc1/sdc1 exception. The handlers have not been | |
1102 | * written yet. Well, anyway there is no R6000 machine on the | |
1103 | * current list of targets for Linux/MIPS. | |
1104 | * (Duh, crap, there is someone with a triple R6k machine) | |
1105 | */ | |
1106 | //set_except_vector(14, handle_mc); | |
1107 | //set_except_vector(15, handle_ndc); | |
1108 | } | |
1109 | ||
e50c0a8f RB |
1110 | if (cpu_has_fpu && !cpu_has_nofpuex) |
1111 | set_except_vector(15, handle_fpe); | |
1112 | ||
1113 | set_except_vector(22, handle_mdmx); | |
1114 | ||
1115 | if (cpu_has_mcheck) | |
1116 | set_except_vector(24, handle_mcheck); | |
1117 | ||
1118 | if (cpu_has_dsp) | |
1119 | set_except_vector(26, handle_dsp); | |
1120 | ||
1121 | if (cpu_has_vce) | |
1122 | /* Special exception: R4[04]00 uses also the divec space. */ | |
1123 | memcpy((void *)(CAC_BASE + 0x180), &except_vec3_r4000, 0x100); | |
1124 | else if (cpu_has_4kex) | |
1125 | memcpy((void *)(CAC_BASE + 0x180), &except_vec3_generic, 0x80); | |
1126 | else | |
1127 | memcpy((void *)(CAC_BASE + 0x080), &except_vec3_generic, 0x80); | |
1128 | ||
1da177e4 LT |
1129 | signal_init(); |
1130 | #ifdef CONFIG_MIPS32_COMPAT | |
1131 | signal32_init(); | |
1132 | #endif | |
1133 | ||
1134 | flush_icache_range(CAC_BASE, CAC_BASE + 0x400); | |
1135 | } |