Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
36ccf1c0 | 6 | * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle |
1da177e4 LT |
7 | * Copyright (C) 1995, 1996 Paul M. Antoine |
8 | * Copyright (C) 1998 Ulf Carlsson | |
9 | * Copyright (C) 1999 Silicon Graphics, Inc. | |
10 | * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com | |
60b0d655 | 11 | * Copyright (C) 2002, 2003, 2004, 2005, 2007 Maciej W. Rozycki |
2a0b24f5 | 12 | * Copyright (C) 2000, 2001, 2012 MIPS Technologies, Inc. All rights reserved. |
b08a9c95 | 13 | * Copyright (C) 2014, Imagination Technologies Ltd. |
1da177e4 | 14 | */ |
ed2d72c1 | 15 | #include <linux/bitops.h> |
8e8a52ed | 16 | #include <linux/bug.h> |
60b0d655 | 17 | #include <linux/compiler.h> |
c3fc5cd5 | 18 | #include <linux/context_tracking.h> |
ae4ce454 | 19 | #include <linux/cpu_pm.h> |
7aa1c8f4 | 20 | #include <linux/kexec.h> |
1da177e4 | 21 | #include <linux/init.h> |
8742cd23 | 22 | #include <linux/kernel.h> |
f9ded569 | 23 | #include <linux/module.h> |
1da177e4 | 24 | #include <linux/mm.h> |
1da177e4 LT |
25 | #include <linux/sched.h> |
26 | #include <linux/smp.h> | |
1da177e4 LT |
27 | #include <linux/spinlock.h> |
28 | #include <linux/kallsyms.h> | |
e01402b1 | 29 | #include <linux/bootmem.h> |
d4fd1989 | 30 | #include <linux/interrupt.h> |
39b8d525 | 31 | #include <linux/ptrace.h> |
88547001 JW |
32 | #include <linux/kgdb.h> |
33 | #include <linux/kdebug.h> | |
c1bf207d | 34 | #include <linux/kprobes.h> |
69f3a7de | 35 | #include <linux/notifier.h> |
5dd11d5d | 36 | #include <linux/kdb.h> |
ca4d3e67 | 37 | #include <linux/irq.h> |
7f788d2d | 38 | #include <linux/perf_event.h> |
1da177e4 LT |
39 | |
40 | #include <asm/bootinfo.h> | |
41 | #include <asm/branch.h> | |
42 | #include <asm/break.h> | |
69f3a7de | 43 | #include <asm/cop2.h> |
1da177e4 | 44 | #include <asm/cpu.h> |
69f24d17 | 45 | #include <asm/cpu-type.h> |
e50c0a8f | 46 | #include <asm/dsp.h> |
1da177e4 | 47 | #include <asm/fpu.h> |
ba3049ed | 48 | #include <asm/fpu_emulator.h> |
bdc92d74 | 49 | #include <asm/idle.h> |
b0a668fb | 50 | #include <asm/mips-r2-to-r6-emul.h> |
340ee4b9 RB |
51 | #include <asm/mipsregs.h> |
52 | #include <asm/mipsmtregs.h> | |
1da177e4 | 53 | #include <asm/module.h> |
1db1af84 | 54 | #include <asm/msa.h> |
1da177e4 LT |
55 | #include <asm/pgtable.h> |
56 | #include <asm/ptrace.h> | |
57 | #include <asm/sections.h> | |
1da177e4 LT |
58 | #include <asm/tlbdebug.h> |
59 | #include <asm/traps.h> | |
60 | #include <asm/uaccess.h> | |
b67b2b70 | 61 | #include <asm/watch.h> |
1da177e4 | 62 | #include <asm/mmu_context.h> |
1da177e4 | 63 | #include <asm/types.h> |
1df0f0ff | 64 | #include <asm/stacktrace.h> |
92bbe1b9 | 65 | #include <asm/uasm.h> |
1da177e4 | 66 | |
c65a5480 | 67 | extern void check_wait(void); |
c65a5480 | 68 | extern asmlinkage void rollback_handle_int(void); |
e4ac58af | 69 | extern asmlinkage void handle_int(void); |
86a1708a RB |
70 | extern u32 handle_tlbl[]; |
71 | extern u32 handle_tlbs[]; | |
72 | extern u32 handle_tlbm[]; | |
1da177e4 LT |
73 | extern asmlinkage void handle_adel(void); |
74 | extern asmlinkage void handle_ades(void); | |
75 | extern asmlinkage void handle_ibe(void); | |
76 | extern asmlinkage void handle_dbe(void); | |
77 | extern asmlinkage void handle_sys(void); | |
78 | extern asmlinkage void handle_bp(void); | |
79 | extern asmlinkage void handle_ri(void); | |
5b10496b AN |
80 | extern asmlinkage void handle_ri_rdhwr_vivt(void); |
81 | extern asmlinkage void handle_ri_rdhwr(void); | |
1da177e4 LT |
82 | extern asmlinkage void handle_cpu(void); |
83 | extern asmlinkage void handle_ov(void); | |
84 | extern asmlinkage void handle_tr(void); | |
2bcb3fbc | 85 | extern asmlinkage void handle_msa_fpe(void); |
1da177e4 | 86 | extern asmlinkage void handle_fpe(void); |
75b5b5e0 | 87 | extern asmlinkage void handle_ftlb(void); |
1db1af84 | 88 | extern asmlinkage void handle_msa(void); |
1da177e4 LT |
89 | extern asmlinkage void handle_mdmx(void); |
90 | extern asmlinkage void handle_watch(void); | |
340ee4b9 | 91 | extern asmlinkage void handle_mt(void); |
e50c0a8f | 92 | extern asmlinkage void handle_dsp(void); |
1da177e4 LT |
93 | extern asmlinkage void handle_mcheck(void); |
94 | extern asmlinkage void handle_reserved(void); | |
5890f70f | 95 | extern void tlb_do_page_fault_0(void); |
1da177e4 | 96 | |
1da177e4 LT |
97 | void (*board_be_init)(void); |
98 | int (*board_be_handler)(struct pt_regs *regs, int is_fixup); | |
e01402b1 RB |
99 | void (*board_nmi_handler_setup)(void); |
100 | void (*board_ejtag_handler_setup)(void); | |
101 | void (*board_bind_eic_interrupt)(int irq, int regset); | |
6fb97eff | 102 | void (*board_ebase_setup)(void); |
078a55fc | 103 | void(*board_cache_error_setup)(void); |
1da177e4 | 104 | |
4d157d5e | 105 | static void show_raw_backtrace(unsigned long reg29) |
e889d78f | 106 | { |
39b8d525 | 107 | unsigned long *sp = (unsigned long *)(reg29 & ~3); |
e889d78f AN |
108 | unsigned long addr; |
109 | ||
110 | printk("Call Trace:"); | |
111 | #ifdef CONFIG_KALLSYMS | |
112 | printk("\n"); | |
113 | #endif | |
10220c88 TB |
114 | while (!kstack_end(sp)) { |
115 | unsigned long __user *p = | |
116 | (unsigned long __user *)(unsigned long)sp++; | |
117 | if (__get_user(addr, p)) { | |
118 | printk(" (Bad stack address)"); | |
119 | break; | |
39b8d525 | 120 | } |
10220c88 TB |
121 | if (__kernel_text_address(addr)) |
122 | print_ip_sym(addr); | |
e889d78f | 123 | } |
10220c88 | 124 | printk("\n"); |
e889d78f AN |
125 | } |
126 | ||
f66686f7 | 127 | #ifdef CONFIG_KALLSYMS |
1df0f0ff | 128 | int raw_show_trace; |
f66686f7 AN |
129 | static int __init set_raw_show_trace(char *str) |
130 | { | |
131 | raw_show_trace = 1; | |
132 | return 1; | |
133 | } | |
134 | __setup("raw_show_trace", set_raw_show_trace); | |
1df0f0ff | 135 | #endif |
4d157d5e | 136 | |
eae23f2c | 137 | static void show_backtrace(struct task_struct *task, const struct pt_regs *regs) |
f66686f7 | 138 | { |
4d157d5e FBH |
139 | unsigned long sp = regs->regs[29]; |
140 | unsigned long ra = regs->regs[31]; | |
f66686f7 | 141 | unsigned long pc = regs->cp0_epc; |
f66686f7 | 142 | |
e909be82 VW |
143 | if (!task) |
144 | task = current; | |
145 | ||
f66686f7 | 146 | if (raw_show_trace || !__kernel_text_address(pc)) { |
87151ae3 | 147 | show_raw_backtrace(sp); |
f66686f7 AN |
148 | return; |
149 | } | |
150 | printk("Call Trace:\n"); | |
4d157d5e | 151 | do { |
87151ae3 | 152 | print_ip_sym(pc); |
1924600c | 153 | pc = unwind_stack(task, &sp, pc, &ra); |
4d157d5e | 154 | } while (pc); |
f66686f7 AN |
155 | printk("\n"); |
156 | } | |
f66686f7 | 157 | |
1da177e4 LT |
158 | /* |
159 | * This routine abuses get_user()/put_user() to reference pointers | |
160 | * with at least a bit of error checking ... | |
161 | */ | |
eae23f2c RB |
162 | static void show_stacktrace(struct task_struct *task, |
163 | const struct pt_regs *regs) | |
1da177e4 LT |
164 | { |
165 | const int field = 2 * sizeof(unsigned long); | |
166 | long stackdata; | |
167 | int i; | |
5e0373b8 | 168 | unsigned long __user *sp = (unsigned long __user *)regs->regs[29]; |
1da177e4 LT |
169 | |
170 | printk("Stack :"); | |
171 | i = 0; | |
172 | while ((unsigned long) sp & (PAGE_SIZE - 1)) { | |
173 | if (i && ((i % (64 / field)) == 0)) | |
70342287 | 174 | printk("\n "); |
1da177e4 LT |
175 | if (i > 39) { |
176 | printk(" ..."); | |
177 | break; | |
178 | } | |
179 | ||
180 | if (__get_user(stackdata, sp++)) { | |
181 | printk(" (Bad stack address)"); | |
182 | break; | |
183 | } | |
184 | ||
185 | printk(" %0*lx", field, stackdata); | |
186 | i++; | |
187 | } | |
188 | printk("\n"); | |
87151ae3 | 189 | show_backtrace(task, regs); |
f66686f7 AN |
190 | } |
191 | ||
f66686f7 AN |
192 | void show_stack(struct task_struct *task, unsigned long *sp) |
193 | { | |
194 | struct pt_regs regs; | |
195 | if (sp) { | |
196 | regs.regs[29] = (unsigned long)sp; | |
197 | regs.regs[31] = 0; | |
198 | regs.cp0_epc = 0; | |
199 | } else { | |
200 | if (task && task != current) { | |
201 | regs.regs[29] = task->thread.reg29; | |
202 | regs.regs[31] = 0; | |
203 | regs.cp0_epc = task->thread.reg31; | |
5dd11d5d JW |
204 | #ifdef CONFIG_KGDB_KDB |
205 | } else if (atomic_read(&kgdb_active) != -1 && | |
206 | kdb_current_regs) { | |
207 | memcpy(®s, kdb_current_regs, sizeof(regs)); | |
208 | #endif /* CONFIG_KGDB_KDB */ | |
f66686f7 AN |
209 | } else { |
210 | prepare_frametrace(®s); | |
211 | } | |
212 | } | |
213 | show_stacktrace(task, ®s); | |
1da177e4 LT |
214 | } |
215 | ||
e1bb8289 | 216 | static void show_code(unsigned int __user *pc) |
1da177e4 LT |
217 | { |
218 | long i; | |
39b8d525 | 219 | unsigned short __user *pc16 = NULL; |
1da177e4 LT |
220 | |
221 | printk("\nCode:"); | |
222 | ||
39b8d525 RB |
223 | if ((unsigned long)pc & 1) |
224 | pc16 = (unsigned short __user *)((unsigned long)pc & ~1); | |
1da177e4 LT |
225 | for(i = -3 ; i < 6 ; i++) { |
226 | unsigned int insn; | |
39b8d525 | 227 | if (pc16 ? __get_user(insn, pc16 + i) : __get_user(insn, pc + i)) { |
1da177e4 LT |
228 | printk(" (Bad address in epc)\n"); |
229 | break; | |
230 | } | |
39b8d525 | 231 | printk("%c%0*x%c", (i?' ':'<'), pc16 ? 4 : 8, insn, (i?' ':'>')); |
1da177e4 LT |
232 | } |
233 | } | |
234 | ||
eae23f2c | 235 | static void __show_regs(const struct pt_regs *regs) |
1da177e4 LT |
236 | { |
237 | const int field = 2 * sizeof(unsigned long); | |
238 | unsigned int cause = regs->cp0_cause; | |
239 | int i; | |
240 | ||
a43cb95d | 241 | show_regs_print_info(KERN_DEFAULT); |
1da177e4 LT |
242 | |
243 | /* | |
244 | * Saved main processor registers | |
245 | */ | |
246 | for (i = 0; i < 32; ) { | |
247 | if ((i % 4) == 0) | |
248 | printk("$%2d :", i); | |
249 | if (i == 0) | |
250 | printk(" %0*lx", field, 0UL); | |
251 | else if (i == 26 || i == 27) | |
252 | printk(" %*s", field, ""); | |
253 | else | |
254 | printk(" %0*lx", field, regs->regs[i]); | |
255 | ||
256 | i++; | |
257 | if ((i % 4) == 0) | |
258 | printk("\n"); | |
259 | } | |
260 | ||
9693a853 FBH |
261 | #ifdef CONFIG_CPU_HAS_SMARTMIPS |
262 | printk("Acx : %0*lx\n", field, regs->acx); | |
263 | #endif | |
1da177e4 LT |
264 | printk("Hi : %0*lx\n", field, regs->hi); |
265 | printk("Lo : %0*lx\n", field, regs->lo); | |
266 | ||
267 | /* | |
268 | * Saved cp0 registers | |
269 | */ | |
b012cffe RB |
270 | printk("epc : %0*lx %pS\n", field, regs->cp0_epc, |
271 | (void *) regs->cp0_epc); | |
1da177e4 | 272 | printk(" %s\n", print_tainted()); |
b012cffe RB |
273 | printk("ra : %0*lx %pS\n", field, regs->regs[31], |
274 | (void *) regs->regs[31]); | |
1da177e4 | 275 | |
70342287 | 276 | printk("Status: %08x ", (uint32_t) regs->cp0_status); |
1da177e4 | 277 | |
1990e542 | 278 | if (cpu_has_3kex) { |
3b2396d9 MR |
279 | if (regs->cp0_status & ST0_KUO) |
280 | printk("KUo "); | |
281 | if (regs->cp0_status & ST0_IEO) | |
282 | printk("IEo "); | |
283 | if (regs->cp0_status & ST0_KUP) | |
284 | printk("KUp "); | |
285 | if (regs->cp0_status & ST0_IEP) | |
286 | printk("IEp "); | |
287 | if (regs->cp0_status & ST0_KUC) | |
288 | printk("KUc "); | |
289 | if (regs->cp0_status & ST0_IEC) | |
290 | printk("IEc "); | |
1990e542 | 291 | } else if (cpu_has_4kex) { |
3b2396d9 MR |
292 | if (regs->cp0_status & ST0_KX) |
293 | printk("KX "); | |
294 | if (regs->cp0_status & ST0_SX) | |
295 | printk("SX "); | |
296 | if (regs->cp0_status & ST0_UX) | |
297 | printk("UX "); | |
298 | switch (regs->cp0_status & ST0_KSU) { | |
299 | case KSU_USER: | |
300 | printk("USER "); | |
301 | break; | |
302 | case KSU_SUPERVISOR: | |
303 | printk("SUPERVISOR "); | |
304 | break; | |
305 | case KSU_KERNEL: | |
306 | printk("KERNEL "); | |
307 | break; | |
308 | default: | |
309 | printk("BAD_MODE "); | |
310 | break; | |
311 | } | |
312 | if (regs->cp0_status & ST0_ERL) | |
313 | printk("ERL "); | |
314 | if (regs->cp0_status & ST0_EXL) | |
315 | printk("EXL "); | |
316 | if (regs->cp0_status & ST0_IE) | |
317 | printk("IE "); | |
1da177e4 | 318 | } |
1da177e4 LT |
319 | printk("\n"); |
320 | ||
321 | printk("Cause : %08x\n", cause); | |
322 | ||
323 | cause = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE; | |
324 | if (1 <= cause && cause <= 5) | |
325 | printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr); | |
326 | ||
9966db25 RB |
327 | printk("PrId : %08x (%s)\n", read_c0_prid(), |
328 | cpu_name_string()); | |
1da177e4 LT |
329 | } |
330 | ||
eae23f2c RB |
331 | /* |
332 | * FIXME: really the generic show_regs should take a const pointer argument. | |
333 | */ | |
334 | void show_regs(struct pt_regs *regs) | |
335 | { | |
336 | __show_regs((struct pt_regs *)regs); | |
337 | } | |
338 | ||
c1bf207d | 339 | void show_registers(struct pt_regs *regs) |
1da177e4 | 340 | { |
39b8d525 | 341 | const int field = 2 * sizeof(unsigned long); |
83e4da1e | 342 | mm_segment_t old_fs = get_fs(); |
39b8d525 | 343 | |
eae23f2c | 344 | __show_regs(regs); |
1da177e4 | 345 | print_modules(); |
39b8d525 RB |
346 | printk("Process %s (pid: %d, threadinfo=%p, task=%p, tls=%0*lx)\n", |
347 | current->comm, current->pid, current_thread_info(), current, | |
348 | field, current_thread_info()->tp_value); | |
349 | if (cpu_has_userlocal) { | |
350 | unsigned long tls; | |
351 | ||
352 | tls = read_c0_userlocal(); | |
353 | if (tls != current_thread_info()->tp_value) | |
354 | printk("*HwTLS: %0*lx\n", field, tls); | |
355 | } | |
356 | ||
83e4da1e LY |
357 | if (!user_mode(regs)) |
358 | /* Necessary for getting the correct stack content */ | |
359 | set_fs(KERNEL_DS); | |
f66686f7 | 360 | show_stacktrace(current, regs); |
e1bb8289 | 361 | show_code((unsigned int __user *) regs->cp0_epc); |
1da177e4 | 362 | printk("\n"); |
83e4da1e | 363 | set_fs(old_fs); |
1da177e4 LT |
364 | } |
365 | ||
70dc6f04 DD |
366 | static int regs_to_trapnr(struct pt_regs *regs) |
367 | { | |
368 | return (regs->cp0_cause >> 2) & 0x1f; | |
369 | } | |
370 | ||
4d85f6af | 371 | static DEFINE_RAW_SPINLOCK(die_lock); |
1da177e4 | 372 | |
70dc6f04 | 373 | void __noreturn die(const char *str, struct pt_regs *regs) |
1da177e4 LT |
374 | { |
375 | static int die_counter; | |
ce384d83 | 376 | int sig = SIGSEGV; |
1da177e4 | 377 | |
8742cd23 NL |
378 | oops_enter(); |
379 | ||
dc73e4c1 RB |
380 | if (notify_die(DIE_OOPS, str, regs, 0, regs_to_trapnr(regs), |
381 | SIGSEGV) == NOTIFY_STOP) | |
10423c91 | 382 | sig = 0; |
5dd11d5d | 383 | |
1da177e4 | 384 | console_verbose(); |
4d85f6af | 385 | raw_spin_lock_irq(&die_lock); |
41c594ab | 386 | bust_spinlocks(1); |
ce384d83 | 387 | |
178086c8 | 388 | printk("%s[#%d]:\n", str, ++die_counter); |
1da177e4 | 389 | show_registers(regs); |
373d4d09 | 390 | add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE); |
4d85f6af | 391 | raw_spin_unlock_irq(&die_lock); |
d4fd1989 | 392 | |
8742cd23 NL |
393 | oops_exit(); |
394 | ||
d4fd1989 MB |
395 | if (in_interrupt()) |
396 | panic("Fatal exception in interrupt"); | |
397 | ||
398 | if (panic_on_oops) { | |
ab75dc02 | 399 | printk(KERN_EMERG "Fatal exception: panic in 5 seconds"); |
d4fd1989 MB |
400 | ssleep(5); |
401 | panic("Fatal exception"); | |
402 | } | |
403 | ||
7aa1c8f4 RB |
404 | if (regs && kexec_should_crash(current)) |
405 | crash_kexec(regs); | |
406 | ||
ce384d83 | 407 | do_exit(sig); |
1da177e4 LT |
408 | } |
409 | ||
0510617b TB |
410 | extern struct exception_table_entry __start___dbe_table[]; |
411 | extern struct exception_table_entry __stop___dbe_table[]; | |
1da177e4 | 412 | |
b6dcec9b RB |
413 | __asm__( |
414 | " .section __dbe_table, \"a\"\n" | |
415 | " .previous \n"); | |
1da177e4 LT |
416 | |
417 | /* Given an address, look for it in the exception tables. */ | |
418 | static const struct exception_table_entry *search_dbe_tables(unsigned long addr) | |
419 | { | |
420 | const struct exception_table_entry *e; | |
421 | ||
422 | e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr); | |
423 | if (!e) | |
424 | e = search_module_dbetables(addr); | |
425 | return e; | |
426 | } | |
427 | ||
428 | asmlinkage void do_be(struct pt_regs *regs) | |
429 | { | |
430 | const int field = 2 * sizeof(unsigned long); | |
431 | const struct exception_table_entry *fixup = NULL; | |
432 | int data = regs->cp0_cause & 4; | |
433 | int action = MIPS_BE_FATAL; | |
c3fc5cd5 | 434 | enum ctx_state prev_state; |
1da177e4 | 435 | |
c3fc5cd5 | 436 | prev_state = exception_enter(); |
70342287 | 437 | /* XXX For now. Fixme, this searches the wrong table ... */ |
1da177e4 LT |
438 | if (data && !user_mode(regs)) |
439 | fixup = search_dbe_tables(exception_epc(regs)); | |
440 | ||
441 | if (fixup) | |
442 | action = MIPS_BE_FIXUP; | |
443 | ||
444 | if (board_be_handler) | |
28fc582c | 445 | action = board_be_handler(regs, fixup != NULL); |
1da177e4 LT |
446 | |
447 | switch (action) { | |
448 | case MIPS_BE_DISCARD: | |
c3fc5cd5 | 449 | goto out; |
1da177e4 LT |
450 | case MIPS_BE_FIXUP: |
451 | if (fixup) { | |
452 | regs->cp0_epc = fixup->nextinsn; | |
c3fc5cd5 | 453 | goto out; |
1da177e4 LT |
454 | } |
455 | break; | |
456 | default: | |
457 | break; | |
458 | } | |
459 | ||
460 | /* | |
461 | * Assume it would be too dangerous to continue ... | |
462 | */ | |
463 | printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n", | |
464 | data ? "Data" : "Instruction", | |
465 | field, regs->cp0_epc, field, regs->regs[31]); | |
dc73e4c1 RB |
466 | if (notify_die(DIE_OOPS, "bus error", regs, 0, regs_to_trapnr(regs), |
467 | SIGBUS) == NOTIFY_STOP) | |
c3fc5cd5 | 468 | goto out; |
88547001 | 469 | |
1da177e4 LT |
470 | die_if_kernel("Oops", regs); |
471 | force_sig(SIGBUS, current); | |
c3fc5cd5 RB |
472 | |
473 | out: | |
474 | exception_exit(prev_state); | |
1da177e4 LT |
475 | } |
476 | ||
1da177e4 | 477 | /* |
60b0d655 | 478 | * ll/sc, rdhwr, sync emulation |
1da177e4 LT |
479 | */ |
480 | ||
481 | #define OPCODE 0xfc000000 | |
482 | #define BASE 0x03e00000 | |
483 | #define RT 0x001f0000 | |
484 | #define OFFSET 0x0000ffff | |
485 | #define LL 0xc0000000 | |
486 | #define SC 0xe0000000 | |
60b0d655 | 487 | #define SPEC0 0x00000000 |
3c37026d RB |
488 | #define SPEC3 0x7c000000 |
489 | #define RD 0x0000f800 | |
490 | #define FUNC 0x0000003f | |
60b0d655 | 491 | #define SYNC 0x0000000f |
3c37026d | 492 | #define RDHWR 0x0000003b |
1da177e4 | 493 | |
2a0b24f5 SH |
494 | /* microMIPS definitions */ |
495 | #define MM_POOL32A_FUNC 0xfc00ffff | |
496 | #define MM_RDHWR 0x00006b3c | |
497 | #define MM_RS 0x001f0000 | |
498 | #define MM_RT 0x03e00000 | |
499 | ||
1da177e4 LT |
500 | /* |
501 | * The ll_bit is cleared by r*_switch.S | |
502 | */ | |
503 | ||
f1e39a4a RB |
504 | unsigned int ll_bit; |
505 | struct task_struct *ll_task; | |
1da177e4 | 506 | |
60b0d655 | 507 | static inline int simulate_ll(struct pt_regs *regs, unsigned int opcode) |
1da177e4 | 508 | { |
fe00f943 | 509 | unsigned long value, __user *vaddr; |
1da177e4 | 510 | long offset; |
1da177e4 LT |
511 | |
512 | /* | |
513 | * analyse the ll instruction that just caused a ri exception | |
514 | * and put the referenced address to addr. | |
515 | */ | |
516 | ||
517 | /* sign extend offset */ | |
518 | offset = opcode & OFFSET; | |
519 | offset <<= 16; | |
520 | offset >>= 16; | |
521 | ||
fe00f943 | 522 | vaddr = (unsigned long __user *) |
b9688310 | 523 | ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); |
1da177e4 | 524 | |
60b0d655 MR |
525 | if ((unsigned long)vaddr & 3) |
526 | return SIGBUS; | |
527 | if (get_user(value, vaddr)) | |
528 | return SIGSEGV; | |
1da177e4 LT |
529 | |
530 | preempt_disable(); | |
531 | ||
532 | if (ll_task == NULL || ll_task == current) { | |
533 | ll_bit = 1; | |
534 | } else { | |
535 | ll_bit = 0; | |
536 | } | |
537 | ll_task = current; | |
538 | ||
539 | preempt_enable(); | |
540 | ||
541 | regs->regs[(opcode & RT) >> 16] = value; | |
542 | ||
60b0d655 | 543 | return 0; |
1da177e4 LT |
544 | } |
545 | ||
60b0d655 | 546 | static inline int simulate_sc(struct pt_regs *regs, unsigned int opcode) |
1da177e4 | 547 | { |
fe00f943 RB |
548 | unsigned long __user *vaddr; |
549 | unsigned long reg; | |
1da177e4 | 550 | long offset; |
1da177e4 LT |
551 | |
552 | /* | |
553 | * analyse the sc instruction that just caused a ri exception | |
554 | * and put the referenced address to addr. | |
555 | */ | |
556 | ||
557 | /* sign extend offset */ | |
558 | offset = opcode & OFFSET; | |
559 | offset <<= 16; | |
560 | offset >>= 16; | |
561 | ||
fe00f943 | 562 | vaddr = (unsigned long __user *) |
b9688310 | 563 | ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); |
1da177e4 LT |
564 | reg = (opcode & RT) >> 16; |
565 | ||
60b0d655 MR |
566 | if ((unsigned long)vaddr & 3) |
567 | return SIGBUS; | |
1da177e4 LT |
568 | |
569 | preempt_disable(); | |
570 | ||
571 | if (ll_bit == 0 || ll_task != current) { | |
572 | regs->regs[reg] = 0; | |
573 | preempt_enable(); | |
60b0d655 | 574 | return 0; |
1da177e4 LT |
575 | } |
576 | ||
577 | preempt_enable(); | |
578 | ||
60b0d655 MR |
579 | if (put_user(regs->regs[reg], vaddr)) |
580 | return SIGSEGV; | |
1da177e4 LT |
581 | |
582 | regs->regs[reg] = 1; | |
583 | ||
60b0d655 | 584 | return 0; |
1da177e4 LT |
585 | } |
586 | ||
587 | /* | |
588 | * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both | |
589 | * opcodes are supposed to result in coprocessor unusable exceptions if | |
590 | * executed on ll/sc-less processors. That's the theory. In practice a | |
591 | * few processors such as NEC's VR4100 throw reserved instruction exceptions | |
592 | * instead, so we're doing the emulation thing in both exception handlers. | |
593 | */ | |
60b0d655 | 594 | static int simulate_llsc(struct pt_regs *regs, unsigned int opcode) |
1da177e4 | 595 | { |
7f788d2d DCZ |
596 | if ((opcode & OPCODE) == LL) { |
597 | perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, | |
a8b0ca17 | 598 | 1, regs, 0); |
60b0d655 | 599 | return simulate_ll(regs, opcode); |
7f788d2d DCZ |
600 | } |
601 | if ((opcode & OPCODE) == SC) { | |
602 | perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, | |
a8b0ca17 | 603 | 1, regs, 0); |
60b0d655 | 604 | return simulate_sc(regs, opcode); |
7f788d2d | 605 | } |
1da177e4 | 606 | |
60b0d655 | 607 | return -1; /* Must be something else ... */ |
1da177e4 LT |
608 | } |
609 | ||
3c37026d RB |
610 | /* |
611 | * Simulate trapping 'rdhwr' instructions to provide user accessible | |
1f5826bd | 612 | * registers not implemented in hardware. |
3c37026d | 613 | */ |
2a0b24f5 | 614 | static int simulate_rdhwr(struct pt_regs *regs, int rd, int rt) |
3c37026d | 615 | { |
dc8f6029 | 616 | struct thread_info *ti = task_thread_info(current); |
3c37026d | 617 | |
2a0b24f5 SH |
618 | perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, |
619 | 1, regs, 0); | |
620 | switch (rd) { | |
621 | case 0: /* CPU number */ | |
622 | regs->regs[rt] = smp_processor_id(); | |
623 | return 0; | |
624 | case 1: /* SYNCI length */ | |
625 | regs->regs[rt] = min(current_cpu_data.dcache.linesz, | |
626 | current_cpu_data.icache.linesz); | |
627 | return 0; | |
628 | case 2: /* Read count register */ | |
629 | regs->regs[rt] = read_c0_count(); | |
630 | return 0; | |
631 | case 3: /* Count register resolution */ | |
69f24d17 | 632 | switch (current_cpu_type()) { |
2a0b24f5 SH |
633 | case CPU_20KC: |
634 | case CPU_25KF: | |
635 | regs->regs[rt] = 1; | |
636 | break; | |
637 | default: | |
638 | regs->regs[rt] = 2; | |
639 | } | |
640 | return 0; | |
641 | case 29: | |
642 | regs->regs[rt] = ti->tp_value; | |
643 | return 0; | |
644 | default: | |
645 | return -1; | |
646 | } | |
647 | } | |
648 | ||
649 | static int simulate_rdhwr_normal(struct pt_regs *regs, unsigned int opcode) | |
650 | { | |
3c37026d RB |
651 | if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) { |
652 | int rd = (opcode & RD) >> 11; | |
653 | int rt = (opcode & RT) >> 16; | |
2a0b24f5 SH |
654 | |
655 | simulate_rdhwr(regs, rd, rt); | |
656 | return 0; | |
657 | } | |
658 | ||
659 | /* Not ours. */ | |
660 | return -1; | |
661 | } | |
662 | ||
663 | static int simulate_rdhwr_mm(struct pt_regs *regs, unsigned short opcode) | |
664 | { | |
665 | if ((opcode & MM_POOL32A_FUNC) == MM_RDHWR) { | |
666 | int rd = (opcode & MM_RS) >> 16; | |
667 | int rt = (opcode & MM_RT) >> 21; | |
668 | simulate_rdhwr(regs, rd, rt); | |
669 | return 0; | |
3c37026d RB |
670 | } |
671 | ||
56ebd51b | 672 | /* Not ours. */ |
60b0d655 MR |
673 | return -1; |
674 | } | |
e5679882 | 675 | |
60b0d655 MR |
676 | static int simulate_sync(struct pt_regs *regs, unsigned int opcode) |
677 | { | |
7f788d2d DCZ |
678 | if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC) { |
679 | perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, | |
a8b0ca17 | 680 | 1, regs, 0); |
60b0d655 | 681 | return 0; |
7f788d2d | 682 | } |
60b0d655 MR |
683 | |
684 | return -1; /* Must be something else ... */ | |
3c37026d RB |
685 | } |
686 | ||
1da177e4 LT |
687 | asmlinkage void do_ov(struct pt_regs *regs) |
688 | { | |
c3fc5cd5 | 689 | enum ctx_state prev_state; |
1da177e4 LT |
690 | siginfo_t info; |
691 | ||
c3fc5cd5 | 692 | prev_state = exception_enter(); |
36ccf1c0 RB |
693 | die_if_kernel("Integer overflow", regs); |
694 | ||
1da177e4 LT |
695 | info.si_code = FPE_INTOVF; |
696 | info.si_signo = SIGFPE; | |
697 | info.si_errno = 0; | |
fe00f943 | 698 | info.si_addr = (void __user *) regs->cp0_epc; |
1da177e4 | 699 | force_sig_info(SIGFPE, &info, current); |
c3fc5cd5 | 700 | exception_exit(prev_state); |
1da177e4 LT |
701 | } |
702 | ||
102cedc3 | 703 | int process_fpemu_return(int sig, void __user *fault_addr) |
515b029d DD |
704 | { |
705 | if (sig == SIGSEGV || sig == SIGBUS) { | |
706 | struct siginfo si = {0}; | |
707 | si.si_addr = fault_addr; | |
708 | si.si_signo = sig; | |
709 | if (sig == SIGSEGV) { | |
f7a89f1b | 710 | down_read(¤t->mm->mmap_sem); |
515b029d DD |
711 | if (find_vma(current->mm, (unsigned long)fault_addr)) |
712 | si.si_code = SEGV_ACCERR; | |
713 | else | |
714 | si.si_code = SEGV_MAPERR; | |
f7a89f1b | 715 | up_read(¤t->mm->mmap_sem); |
515b029d DD |
716 | } else { |
717 | si.si_code = BUS_ADRERR; | |
718 | } | |
719 | force_sig_info(sig, &si, current); | |
720 | return 1; | |
721 | } else if (sig) { | |
722 | force_sig(sig, current); | |
723 | return 1; | |
724 | } else { | |
725 | return 0; | |
726 | } | |
727 | } | |
728 | ||
4227a2d4 PB |
729 | static int simulate_fp(struct pt_regs *regs, unsigned int opcode, |
730 | unsigned long old_epc, unsigned long old_ra) | |
731 | { | |
732 | union mips_instruction inst = { .word = opcode }; | |
733 | void __user *fault_addr = NULL; | |
734 | int sig; | |
735 | ||
736 | /* If it's obviously not an FP instruction, skip it */ | |
737 | switch (inst.i_format.opcode) { | |
738 | case cop1_op: | |
739 | case cop1x_op: | |
740 | case lwc1_op: | |
741 | case ldc1_op: | |
742 | case swc1_op: | |
743 | case sdc1_op: | |
744 | break; | |
745 | ||
746 | default: | |
747 | return -1; | |
748 | } | |
749 | ||
750 | /* | |
751 | * do_ri skipped over the instruction via compute_return_epc, undo | |
752 | * that for the FPU emulator. | |
753 | */ | |
754 | regs->cp0_epc = old_epc; | |
755 | regs->regs[31] = old_ra; | |
756 | ||
757 | /* Save the FP context to struct thread_struct */ | |
758 | lose_fpu(1); | |
759 | ||
760 | /* Run the emulator */ | |
761 | sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1, | |
762 | &fault_addr); | |
763 | ||
764 | /* If something went wrong, signal */ | |
765 | process_fpemu_return(sig, fault_addr); | |
766 | ||
767 | /* Restore the hardware register state */ | |
768 | own_fpu(1); | |
769 | ||
770 | return 0; | |
771 | } | |
772 | ||
1da177e4 LT |
773 | /* |
774 | * XXX Delayed fp exceptions when doing a lazy ctx switch XXX | |
775 | */ | |
776 | asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31) | |
777 | { | |
c3fc5cd5 | 778 | enum ctx_state prev_state; |
515b029d | 779 | siginfo_t info = {0}; |
948a34cf | 780 | |
c3fc5cd5 | 781 | prev_state = exception_enter(); |
dc73e4c1 RB |
782 | if (notify_die(DIE_FP, "FP exception", regs, 0, regs_to_trapnr(regs), |
783 | SIGFPE) == NOTIFY_STOP) | |
c3fc5cd5 | 784 | goto out; |
57725f9e CD |
785 | die_if_kernel("FP exception in kernel code", regs); |
786 | ||
1da177e4 LT |
787 | if (fcr31 & FPU_CSR_UNI_X) { |
788 | int sig; | |
515b029d | 789 | void __user *fault_addr = NULL; |
1da177e4 | 790 | |
1da177e4 | 791 | /* |
a3dddd56 | 792 | * Unimplemented operation exception. If we've got the full |
1da177e4 LT |
793 | * software emulator on-board, let's use it... |
794 | * | |
795 | * Force FPU to dump state into task/thread context. We're | |
796 | * moving a lot of data here for what is probably a single | |
797 | * instruction, but the alternative is to pre-decode the FP | |
798 | * register operands before invoking the emulator, which seems | |
799 | * a bit extreme for what should be an infrequent event. | |
800 | */ | |
cd21dfcf | 801 | /* Ensure 'resume' not overwrite saved fp context again. */ |
53dc8028 | 802 | lose_fpu(1); |
1da177e4 LT |
803 | |
804 | /* Run the emulator */ | |
515b029d DD |
805 | sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1, |
806 | &fault_addr); | |
1da177e4 LT |
807 | |
808 | /* | |
809 | * We can't allow the emulated instruction to leave any of | |
810 | * the cause bit set in $fcr31. | |
811 | */ | |
eae89076 | 812 | current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X; |
1da177e4 LT |
813 | |
814 | /* Restore the hardware register state */ | |
70342287 | 815 | own_fpu(1); /* Using the FPU again. */ |
1da177e4 LT |
816 | |
817 | /* If something went wrong, signal */ | |
515b029d | 818 | process_fpemu_return(sig, fault_addr); |
1da177e4 | 819 | |
c3fc5cd5 | 820 | goto out; |
ed2d72c1 MR |
821 | } |
822 | ||
823 | /* | |
824 | * Inexact can happen together with Overflow or Underflow. | |
825 | * Respect the mask to deliver the correct exception. | |
826 | */ | |
827 | fcr31 &= (fcr31 & FPU_CSR_ALL_E) << | |
828 | (ffs(FPU_CSR_ALL_X) - ffs(FPU_CSR_ALL_E)); | |
829 | if (fcr31 & FPU_CSR_INV_X) | |
948a34cf TS |
830 | info.si_code = FPE_FLTINV; |
831 | else if (fcr31 & FPU_CSR_DIV_X) | |
832 | info.si_code = FPE_FLTDIV; | |
833 | else if (fcr31 & FPU_CSR_OVF_X) | |
834 | info.si_code = FPE_FLTOVF; | |
835 | else if (fcr31 & FPU_CSR_UDF_X) | |
836 | info.si_code = FPE_FLTUND; | |
837 | else if (fcr31 & FPU_CSR_INE_X) | |
838 | info.si_code = FPE_FLTRES; | |
839 | else | |
840 | info.si_code = __SI_FAULT; | |
841 | info.si_signo = SIGFPE; | |
842 | info.si_errno = 0; | |
843 | info.si_addr = (void __user *) regs->cp0_epc; | |
844 | force_sig_info(SIGFPE, &info, current); | |
c3fc5cd5 RB |
845 | |
846 | out: | |
847 | exception_exit(prev_state); | |
1da177e4 LT |
848 | } |
849 | ||
b0a668fb | 850 | void do_trap_or_bp(struct pt_regs *regs, unsigned int code, |
df270051 | 851 | const char *str) |
1da177e4 | 852 | { |
1da177e4 | 853 | siginfo_t info; |
df270051 | 854 | char b[40]; |
1da177e4 | 855 | |
5dd11d5d | 856 | #ifdef CONFIG_KGDB_LOW_LEVEL_TRAP |
70dc6f04 | 857 | if (kgdb_ll_trap(DIE_TRAP, str, regs, code, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP) |
5dd11d5d JW |
858 | return; |
859 | #endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */ | |
860 | ||
dc73e4c1 RB |
861 | if (notify_die(DIE_TRAP, str, regs, code, regs_to_trapnr(regs), |
862 | SIGTRAP) == NOTIFY_STOP) | |
88547001 JW |
863 | return; |
864 | ||
1da177e4 | 865 | /* |
df270051 RB |
866 | * A short test says that IRIX 5.3 sends SIGTRAP for all trap |
867 | * insns, even for trap and break codes that indicate arithmetic | |
868 | * failures. Weird ... | |
1da177e4 LT |
869 | * But should we continue the brokenness??? --macro |
870 | */ | |
df270051 RB |
871 | switch (code) { |
872 | case BRK_OVERFLOW: | |
873 | case BRK_DIVZERO: | |
874 | scnprintf(b, sizeof(b), "%s instruction in kernel code", str); | |
875 | die_if_kernel(b, regs); | |
876 | if (code == BRK_DIVZERO) | |
1da177e4 LT |
877 | info.si_code = FPE_INTDIV; |
878 | else | |
879 | info.si_code = FPE_INTOVF; | |
880 | info.si_signo = SIGFPE; | |
881 | info.si_errno = 0; | |
fe00f943 | 882 | info.si_addr = (void __user *) regs->cp0_epc; |
1da177e4 LT |
883 | force_sig_info(SIGFPE, &info, current); |
884 | break; | |
63dc68a8 | 885 | case BRK_BUG: |
df270051 RB |
886 | die_if_kernel("Kernel bug detected", regs); |
887 | force_sig(SIGTRAP, current); | |
63dc68a8 | 888 | break; |
ba3049ed RB |
889 | case BRK_MEMU: |
890 | /* | |
1f443779 MR |
891 | * This breakpoint code is used by the FPU emulator to retake |
892 | * control of the CPU after executing the instruction from the | |
893 | * delay slot of an emulated branch. | |
ba3049ed RB |
894 | * |
895 | * Terminate if exception was recognized as a delay slot return | |
896 | * otherwise handle as normal. | |
897 | */ | |
898 | if (do_dsemulret(regs)) | |
899 | return; | |
900 | ||
901 | die_if_kernel("Math emu break/trap", regs); | |
902 | force_sig(SIGTRAP, current); | |
903 | break; | |
1da177e4 | 904 | default: |
df270051 RB |
905 | scnprintf(b, sizeof(b), "%s instruction in kernel code", str); |
906 | die_if_kernel(b, regs); | |
1da177e4 LT |
907 | force_sig(SIGTRAP, current); |
908 | } | |
df270051 RB |
909 | } |
910 | ||
911 | asmlinkage void do_bp(struct pt_regs *regs) | |
912 | { | |
f6a31da5 | 913 | unsigned long epc = msk_isa16_mode(exception_epc(regs)); |
df270051 | 914 | unsigned int opcode, bcode; |
c3fc5cd5 | 915 | enum ctx_state prev_state; |
078dde5e LY |
916 | mm_segment_t seg; |
917 | ||
918 | seg = get_fs(); | |
919 | if (!user_mode(regs)) | |
920 | set_fs(KERNEL_DS); | |
2a0b24f5 | 921 | |
c3fc5cd5 | 922 | prev_state = exception_enter(); |
2a0b24f5 | 923 | if (get_isa16_mode(regs->cp0_epc)) { |
f6a31da5 MR |
924 | u16 instr[2]; |
925 | ||
926 | if (__get_user(instr[0], (u16 __user *)epc)) | |
927 | goto out_sigsegv; | |
928 | ||
929 | if (!cpu_has_mmips) { | |
b08a9c95 | 930 | /* MIPS16e mode */ |
68893e00 | 931 | bcode = (instr[0] >> 5) & 0x3f; |
f6a31da5 MR |
932 | } else if (mm_insn_16bit(instr[0])) { |
933 | /* 16-bit microMIPS BREAK */ | |
934 | bcode = instr[0] & 0xf; | |
935 | } else { | |
936 | /* 32-bit microMIPS BREAK */ | |
937 | if (__get_user(instr[1], (u16 __user *)(epc + 2))) | |
938 | goto out_sigsegv; | |
939 | opcode = (instr[0] << 16) | instr[1]; | |
940 | bcode = (opcode >> 6) & ((1 << 20) - 1); | |
2a0b24f5 SH |
941 | } |
942 | } else { | |
f6a31da5 | 943 | if (__get_user(opcode, (unsigned int __user *)epc)) |
2a0b24f5 | 944 | goto out_sigsegv; |
f6a31da5 | 945 | bcode = (opcode >> 6) & ((1 << 20) - 1); |
2a0b24f5 | 946 | } |
df270051 RB |
947 | |
948 | /* | |
949 | * There is the ancient bug in the MIPS assemblers that the break | |
950 | * code starts left to bit 16 instead to bit 6 in the opcode. | |
951 | * Gas is bug-compatible, but not always, grrr... | |
952 | * We handle both cases with a simple heuristics. --macro | |
953 | */ | |
df270051 | 954 | if (bcode >= (1 << 10)) |
c9875032 | 955 | bcode = ((bcode & ((1 << 10) - 1)) << 10) | (bcode >> 10); |
df270051 | 956 | |
c1bf207d DD |
957 | /* |
958 | * notify the kprobe handlers, if instruction is likely to | |
959 | * pertain to them. | |
960 | */ | |
961 | switch (bcode) { | |
962 | case BRK_KPROBE_BP: | |
dc73e4c1 RB |
963 | if (notify_die(DIE_BREAK, "debug", regs, bcode, |
964 | regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP) | |
c3fc5cd5 | 965 | goto out; |
c1bf207d DD |
966 | else |
967 | break; | |
968 | case BRK_KPROBE_SSTEPBP: | |
dc73e4c1 RB |
969 | if (notify_die(DIE_SSTEPBP, "single_step", regs, bcode, |
970 | regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP) | |
c3fc5cd5 | 971 | goto out; |
c1bf207d DD |
972 | else |
973 | break; | |
974 | default: | |
975 | break; | |
976 | } | |
977 | ||
df270051 | 978 | do_trap_or_bp(regs, bcode, "Break"); |
c3fc5cd5 RB |
979 | |
980 | out: | |
078dde5e | 981 | set_fs(seg); |
c3fc5cd5 | 982 | exception_exit(prev_state); |
90fccb13 | 983 | return; |
e5679882 RB |
984 | |
985 | out_sigsegv: | |
986 | force_sig(SIGSEGV, current); | |
c3fc5cd5 | 987 | goto out; |
1da177e4 LT |
988 | } |
989 | ||
990 | asmlinkage void do_tr(struct pt_regs *regs) | |
991 | { | |
a9a6e7a0 | 992 | u32 opcode, tcode = 0; |
c3fc5cd5 | 993 | enum ctx_state prev_state; |
2a0b24f5 | 994 | u16 instr[2]; |
078dde5e | 995 | mm_segment_t seg; |
a9a6e7a0 | 996 | unsigned long epc = msk_isa16_mode(exception_epc(regs)); |
1da177e4 | 997 | |
078dde5e LY |
998 | seg = get_fs(); |
999 | if (!user_mode(regs)) | |
1000 | set_fs(get_ds()); | |
1001 | ||
c3fc5cd5 | 1002 | prev_state = exception_enter(); |
a9a6e7a0 MR |
1003 | if (get_isa16_mode(regs->cp0_epc)) { |
1004 | if (__get_user(instr[0], (u16 __user *)(epc + 0)) || | |
1005 | __get_user(instr[1], (u16 __user *)(epc + 2))) | |
2a0b24f5 | 1006 | goto out_sigsegv; |
a9a6e7a0 MR |
1007 | opcode = (instr[0] << 16) | instr[1]; |
1008 | /* Immediate versions don't provide a code. */ | |
1009 | if (!(opcode & OPCODE)) | |
1010 | tcode = (opcode >> 12) & ((1 << 4) - 1); | |
1011 | } else { | |
1012 | if (__get_user(opcode, (u32 __user *)epc)) | |
1013 | goto out_sigsegv; | |
1014 | /* Immediate versions don't provide a code. */ | |
1015 | if (!(opcode & OPCODE)) | |
1016 | tcode = (opcode >> 6) & ((1 << 10) - 1); | |
2a0b24f5 | 1017 | } |
1da177e4 | 1018 | |
df270051 | 1019 | do_trap_or_bp(regs, tcode, "Trap"); |
c3fc5cd5 RB |
1020 | |
1021 | out: | |
078dde5e | 1022 | set_fs(seg); |
c3fc5cd5 | 1023 | exception_exit(prev_state); |
90fccb13 | 1024 | return; |
e5679882 RB |
1025 | |
1026 | out_sigsegv: | |
1027 | force_sig(SIGSEGV, current); | |
c3fc5cd5 | 1028 | goto out; |
1da177e4 LT |
1029 | } |
1030 | ||
1031 | asmlinkage void do_ri(struct pt_regs *regs) | |
1032 | { | |
60b0d655 MR |
1033 | unsigned int __user *epc = (unsigned int __user *)exception_epc(regs); |
1034 | unsigned long old_epc = regs->cp0_epc; | |
2a0b24f5 | 1035 | unsigned long old31 = regs->regs[31]; |
c3fc5cd5 | 1036 | enum ctx_state prev_state; |
60b0d655 MR |
1037 | unsigned int opcode = 0; |
1038 | int status = -1; | |
1da177e4 | 1039 | |
b0a668fb LY |
1040 | /* |
1041 | * Avoid any kernel code. Just emulate the R2 instruction | |
1042 | * as quickly as possible. | |
1043 | */ | |
1044 | if (mipsr2_emulation && cpu_has_mips_r6 && | |
4a7c2371 MR |
1045 | likely(user_mode(regs)) && |
1046 | likely(get_user(opcode, epc) >= 0)) { | |
1047 | status = mipsr2_decoder(regs, opcode); | |
1048 | switch (status) { | |
1049 | case 0: | |
1050 | case SIGEMT: | |
1051 | task_thread_info(current)->r2_emul_return = 1; | |
1052 | return; | |
1053 | case SIGILL: | |
1054 | goto no_r2_instr; | |
1055 | default: | |
1056 | process_fpemu_return(status, | |
1057 | ¤t->thread.cp0_baduaddr); | |
1058 | task_thread_info(current)->r2_emul_return = 1; | |
1059 | return; | |
b0a668fb LY |
1060 | } |
1061 | } | |
1062 | ||
1063 | no_r2_instr: | |
1064 | ||
c3fc5cd5 | 1065 | prev_state = exception_enter(); |
b0a668fb | 1066 | |
dc73e4c1 RB |
1067 | if (notify_die(DIE_RI, "RI Fault", regs, 0, regs_to_trapnr(regs), |
1068 | SIGILL) == NOTIFY_STOP) | |
c3fc5cd5 | 1069 | goto out; |
88547001 | 1070 | |
60b0d655 | 1071 | die_if_kernel("Reserved instruction in kernel code", regs); |
1da177e4 | 1072 | |
60b0d655 | 1073 | if (unlikely(compute_return_epc(regs) < 0)) |
c3fc5cd5 | 1074 | goto out; |
3c37026d | 1075 | |
2a0b24f5 SH |
1076 | if (get_isa16_mode(regs->cp0_epc)) { |
1077 | unsigned short mmop[2] = { 0 }; | |
60b0d655 | 1078 | |
2a0b24f5 SH |
1079 | if (unlikely(get_user(mmop[0], epc) < 0)) |
1080 | status = SIGSEGV; | |
1081 | if (unlikely(get_user(mmop[1], epc) < 0)) | |
1082 | status = SIGSEGV; | |
1083 | opcode = (mmop[0] << 16) | mmop[1]; | |
60b0d655 | 1084 | |
2a0b24f5 SH |
1085 | if (status < 0) |
1086 | status = simulate_rdhwr_mm(regs, opcode); | |
1087 | } else { | |
1088 | if (unlikely(get_user(opcode, epc) < 0)) | |
1089 | status = SIGSEGV; | |
60b0d655 | 1090 | |
2a0b24f5 SH |
1091 | if (!cpu_has_llsc && status < 0) |
1092 | status = simulate_llsc(regs, opcode); | |
1093 | ||
1094 | if (status < 0) | |
1095 | status = simulate_rdhwr_normal(regs, opcode); | |
1096 | ||
1097 | if (status < 0) | |
1098 | status = simulate_sync(regs, opcode); | |
4227a2d4 PB |
1099 | |
1100 | if (status < 0) | |
1101 | status = simulate_fp(regs, opcode, old_epc, old31); | |
2a0b24f5 | 1102 | } |
60b0d655 MR |
1103 | |
1104 | if (status < 0) | |
1105 | status = SIGILL; | |
1106 | ||
1107 | if (unlikely(status > 0)) { | |
1108 | regs->cp0_epc = old_epc; /* Undo skip-over. */ | |
2a0b24f5 | 1109 | regs->regs[31] = old31; |
60b0d655 MR |
1110 | force_sig(status, current); |
1111 | } | |
c3fc5cd5 RB |
1112 | |
1113 | out: | |
1114 | exception_exit(prev_state); | |
1da177e4 LT |
1115 | } |
1116 | ||
d223a861 RB |
1117 | /* |
1118 | * MIPS MT processors may have fewer FPU contexts than CPU threads. If we've | |
1119 | * emulated more than some threshold number of instructions, force migration to | |
1120 | * a "CPU" that has FP support. | |
1121 | */ | |
1122 | static void mt_ase_fp_affinity(void) | |
1123 | { | |
1124 | #ifdef CONFIG_MIPS_MT_FPAFF | |
1125 | if (mt_fpemul_threshold > 0 && | |
1126 | ((current->thread.emulated_fp++ > mt_fpemul_threshold))) { | |
1127 | /* | |
1128 | * If there's no FPU present, or if the application has already | |
1129 | * restricted the allowed set to exclude any CPUs with FPUs, | |
1130 | * we'll skip the procedure. | |
1131 | */ | |
1132 | if (cpus_intersects(current->cpus_allowed, mt_fpu_cpumask)) { | |
1133 | cpumask_t tmask; | |
1134 | ||
9cc12363 KK |
1135 | current->thread.user_cpus_allowed |
1136 | = current->cpus_allowed; | |
1137 | cpus_and(tmask, current->cpus_allowed, | |
1138 | mt_fpu_cpumask); | |
ed1bbdef | 1139 | set_cpus_allowed_ptr(current, &tmask); |
293c5bd1 | 1140 | set_thread_flag(TIF_FPUBOUND); |
d223a861 RB |
1141 | } |
1142 | } | |
1143 | #endif /* CONFIG_MIPS_MT_FPAFF */ | |
1144 | } | |
1145 | ||
69f3a7de RB |
1146 | /* |
1147 | * No lock; only written during early bootup by CPU 0. | |
1148 | */ | |
1149 | static RAW_NOTIFIER_HEAD(cu2_chain); | |
1150 | ||
1151 | int __ref register_cu2_notifier(struct notifier_block *nb) | |
1152 | { | |
1153 | return raw_notifier_chain_register(&cu2_chain, nb); | |
1154 | } | |
1155 | ||
1156 | int cu2_notifier_call_chain(unsigned long val, void *v) | |
1157 | { | |
1158 | return raw_notifier_call_chain(&cu2_chain, val, v); | |
1159 | } | |
1160 | ||
1161 | static int default_cu2_call(struct notifier_block *nfb, unsigned long action, | |
70342287 | 1162 | void *data) |
69f3a7de RB |
1163 | { |
1164 | struct pt_regs *regs = data; | |
1165 | ||
83bee792 | 1166 | die_if_kernel("COP2: Unhandled kernel unaligned access or invalid " |
69f3a7de | 1167 | "instruction", regs); |
83bee792 | 1168 | force_sig(SIGILL, current); |
69f3a7de RB |
1169 | |
1170 | return NOTIFY_OK; | |
1171 | } | |
1172 | ||
9791554b PB |
1173 | static int wait_on_fp_mode_switch(atomic_t *p) |
1174 | { | |
1175 | /* | |
1176 | * The FP mode for this task is currently being switched. That may | |
1177 | * involve modifications to the format of this tasks FP context which | |
1178 | * make it unsafe to proceed with execution for the moment. Instead, | |
1179 | * schedule some other task. | |
1180 | */ | |
1181 | schedule(); | |
1182 | return 0; | |
1183 | } | |
1184 | ||
1db1af84 PB |
1185 | static int enable_restore_fp_context(int msa) |
1186 | { | |
c9017757 | 1187 | int err, was_fpu_owner, prior_msa; |
1db1af84 | 1188 | |
9791554b PB |
1189 | /* |
1190 | * If an FP mode switch is currently underway, wait for it to | |
1191 | * complete before proceeding. | |
1192 | */ | |
1193 | wait_on_atomic_t(¤t->mm->context.fp_mode_switching, | |
1194 | wait_on_fp_mode_switch, TASK_KILLABLE); | |
1195 | ||
1db1af84 PB |
1196 | if (!used_math()) { |
1197 | /* First time FP context user. */ | |
762a1f43 | 1198 | preempt_disable(); |
1db1af84 | 1199 | err = init_fpu(); |
c9017757 | 1200 | if (msa && !err) { |
1db1af84 | 1201 | enable_msa(); |
c9017757 | 1202 | _init_msa_upper(); |
732c0c3c PB |
1203 | set_thread_flag(TIF_USEDMSA); |
1204 | set_thread_flag(TIF_MSA_CTX_LIVE); | |
c9017757 | 1205 | } |
762a1f43 | 1206 | preempt_enable(); |
1db1af84 PB |
1207 | if (!err) |
1208 | set_used_math(); | |
1209 | return err; | |
1210 | } | |
1211 | ||
1212 | /* | |
1213 | * This task has formerly used the FP context. | |
1214 | * | |
1215 | * If this thread has no live MSA vector context then we can simply | |
1216 | * restore the scalar FP context. If it has live MSA vector context | |
1217 | * (that is, it has or may have used MSA since last performing a | |
1218 | * function call) then we'll need to restore the vector context. This | |
1219 | * applies even if we're currently only executing a scalar FP | |
1220 | * instruction. This is because if we were to later execute an MSA | |
1221 | * instruction then we'd either have to: | |
1222 | * | |
1223 | * - Restore the vector context & clobber any registers modified by | |
1224 | * scalar FP instructions between now & then. | |
1225 | * | |
1226 | * or | |
1227 | * | |
1228 | * - Not restore the vector context & lose the most significant bits | |
1229 | * of all vector registers. | |
1230 | * | |
1231 | * Neither of those options is acceptable. We cannot restore the least | |
1232 | * significant bits of the registers now & only restore the most | |
1233 | * significant bits later because the most significant bits of any | |
1234 | * vector registers whose aliased FP register is modified now will have | |
1235 | * been zeroed. We'd have no way to know that when restoring the vector | |
1236 | * context & thus may load an outdated value for the most significant | |
1237 | * bits of a vector register. | |
1238 | */ | |
1239 | if (!msa && !thread_msa_context_live()) | |
1240 | return own_fpu(1); | |
1241 | ||
1242 | /* | |
1243 | * This task is using or has previously used MSA. Thus we require | |
1244 | * that Status.FR == 1. | |
1245 | */ | |
762a1f43 | 1246 | preempt_disable(); |
1db1af84 | 1247 | was_fpu_owner = is_fpu_owner(); |
762a1f43 | 1248 | err = own_fpu_inatomic(0); |
1db1af84 | 1249 | if (err) |
762a1f43 | 1250 | goto out; |
1db1af84 PB |
1251 | |
1252 | enable_msa(); | |
1253 | write_msa_csr(current->thread.fpu.msacsr); | |
1254 | set_thread_flag(TIF_USEDMSA); | |
1255 | ||
1256 | /* | |
1257 | * If this is the first time that the task is using MSA and it has | |
1258 | * previously used scalar FP in this time slice then we already nave | |
c9017757 PB |
1259 | * FP context which we shouldn't clobber. We do however need to clear |
1260 | * the upper 64b of each vector register so that this task has no | |
1261 | * opportunity to see data left behind by another. | |
1db1af84 | 1262 | */ |
c9017757 PB |
1263 | prior_msa = test_and_set_thread_flag(TIF_MSA_CTX_LIVE); |
1264 | if (!prior_msa && was_fpu_owner) { | |
1265 | _init_msa_upper(); | |
762a1f43 PB |
1266 | |
1267 | goto out; | |
c9017757 | 1268 | } |
1db1af84 | 1269 | |
c9017757 PB |
1270 | if (!prior_msa) { |
1271 | /* | |
1272 | * Restore the least significant 64b of each vector register | |
1273 | * from the existing scalar FP context. | |
1274 | */ | |
1275 | _restore_fp(current); | |
b8340673 | 1276 | |
c9017757 PB |
1277 | /* |
1278 | * The task has not formerly used MSA, so clear the upper 64b | |
1279 | * of each vector register such that it cannot see data left | |
1280 | * behind by another task. | |
1281 | */ | |
1282 | _init_msa_upper(); | |
1283 | } else { | |
1284 | /* We need to restore the vector context. */ | |
1285 | restore_msa(current); | |
b8340673 | 1286 | |
c9017757 PB |
1287 | /* Restore the scalar FP control & status register */ |
1288 | if (!was_fpu_owner) | |
d76e9b9f JH |
1289 | write_32bit_cp1_register(CP1_STATUS, |
1290 | current->thread.fpu.fcr31); | |
c9017757 | 1291 | } |
762a1f43 PB |
1292 | |
1293 | out: | |
1294 | preempt_enable(); | |
1295 | ||
1db1af84 PB |
1296 | return 0; |
1297 | } | |
1298 | ||
1da177e4 LT |
1299 | asmlinkage void do_cpu(struct pt_regs *regs) |
1300 | { | |
c3fc5cd5 | 1301 | enum ctx_state prev_state; |
60b0d655 | 1302 | unsigned int __user *epc; |
2a0b24f5 | 1303 | unsigned long old_epc, old31; |
60b0d655 | 1304 | unsigned int opcode; |
1da177e4 | 1305 | unsigned int cpid; |
597ce172 | 1306 | int status, err; |
f9bb4cf3 | 1307 | unsigned long __maybe_unused flags; |
1da177e4 | 1308 | |
c3fc5cd5 | 1309 | prev_state = exception_enter(); |
1da177e4 LT |
1310 | cpid = (regs->cp0_cause >> CAUSEB_CE) & 3; |
1311 | ||
83bee792 J |
1312 | if (cpid != 2) |
1313 | die_if_kernel("do_cpu invoked from kernel context!", regs); | |
1314 | ||
1da177e4 LT |
1315 | switch (cpid) { |
1316 | case 0: | |
60b0d655 MR |
1317 | epc = (unsigned int __user *)exception_epc(regs); |
1318 | old_epc = regs->cp0_epc; | |
2a0b24f5 | 1319 | old31 = regs->regs[31]; |
60b0d655 MR |
1320 | opcode = 0; |
1321 | status = -1; | |
1da177e4 | 1322 | |
60b0d655 | 1323 | if (unlikely(compute_return_epc(regs) < 0)) |
27e28e8e | 1324 | break; |
3c37026d | 1325 | |
2a0b24f5 SH |
1326 | if (get_isa16_mode(regs->cp0_epc)) { |
1327 | unsigned short mmop[2] = { 0 }; | |
60b0d655 | 1328 | |
2a0b24f5 SH |
1329 | if (unlikely(get_user(mmop[0], epc) < 0)) |
1330 | status = SIGSEGV; | |
1331 | if (unlikely(get_user(mmop[1], epc) < 0)) | |
1332 | status = SIGSEGV; | |
1333 | opcode = (mmop[0] << 16) | mmop[1]; | |
60b0d655 | 1334 | |
2a0b24f5 SH |
1335 | if (status < 0) |
1336 | status = simulate_rdhwr_mm(regs, opcode); | |
1337 | } else { | |
1338 | if (unlikely(get_user(opcode, epc) < 0)) | |
1339 | status = SIGSEGV; | |
1340 | ||
1341 | if (!cpu_has_llsc && status < 0) | |
1342 | status = simulate_llsc(regs, opcode); | |
1343 | ||
1344 | if (status < 0) | |
1345 | status = simulate_rdhwr_normal(regs, opcode); | |
1346 | } | |
60b0d655 MR |
1347 | |
1348 | if (status < 0) | |
1349 | status = SIGILL; | |
1350 | ||
1351 | if (unlikely(status > 0)) { | |
1352 | regs->cp0_epc = old_epc; /* Undo skip-over. */ | |
2a0b24f5 | 1353 | regs->regs[31] = old31; |
60b0d655 MR |
1354 | force_sig(status, current); |
1355 | } | |
1356 | ||
27e28e8e | 1357 | break; |
1da177e4 | 1358 | |
051ff44a MR |
1359 | case 3: |
1360 | /* | |
2d83fea7 MR |
1361 | * The COP3 opcode space and consequently the CP0.Status.CU3 |
1362 | * bit and the CP0.Cause.CE=3 encoding have been removed as | |
1363 | * of the MIPS III ISA. From the MIPS IV and MIPS32r2 ISAs | |
1364 | * up the space has been reused for COP1X instructions, that | |
1365 | * are enabled by the CP0.Status.CU1 bit and consequently | |
1366 | * use the CP0.Cause.CE=1 encoding for Coprocessor Unusable | |
1367 | * exceptions. Some FPU-less processors that implement one | |
1368 | * of these ISAs however use this code erroneously for COP1X | |
1369 | * instructions. Therefore we redirect this trap to the FP | |
1370 | * emulator too. | |
051ff44a | 1371 | */ |
2d83fea7 | 1372 | if (raw_cpu_has_fpu || !cpu_has_mips_4_5_64_r2_r6) { |
27e28e8e | 1373 | force_sig(SIGILL, current); |
051ff44a | 1374 | break; |
27e28e8e | 1375 | } |
051ff44a MR |
1376 | /* Fall through. */ |
1377 | ||
1da177e4 | 1378 | case 1: |
1db1af84 | 1379 | err = enable_restore_fp_context(0); |
1da177e4 | 1380 | |
597ce172 | 1381 | if (!raw_cpu_has_fpu || err) { |
e04582b7 | 1382 | int sig; |
515b029d | 1383 | void __user *fault_addr = NULL; |
e04582b7 | 1384 | sig = fpu_emulator_cop1Handler(regs, |
515b029d DD |
1385 | ¤t->thread.fpu, |
1386 | 0, &fault_addr); | |
597ce172 | 1387 | if (!process_fpemu_return(sig, fault_addr) && !err) |
d223a861 | 1388 | mt_ase_fp_affinity(); |
1da177e4 LT |
1389 | } |
1390 | ||
27e28e8e | 1391 | break; |
1da177e4 LT |
1392 | |
1393 | case 2: | |
69f3a7de | 1394 | raw_notifier_call_chain(&cu2_chain, CU2_EXCEPTION, regs); |
27e28e8e | 1395 | break; |
1da177e4 LT |
1396 | } |
1397 | ||
c3fc5cd5 | 1398 | exception_exit(prev_state); |
1da177e4 LT |
1399 | } |
1400 | ||
2bcb3fbc PB |
1401 | asmlinkage void do_msa_fpe(struct pt_regs *regs) |
1402 | { | |
1403 | enum ctx_state prev_state; | |
1404 | ||
1405 | prev_state = exception_enter(); | |
1406 | die_if_kernel("do_msa_fpe invoked from kernel context!", regs); | |
1407 | force_sig(SIGFPE, current); | |
1408 | exception_exit(prev_state); | |
1409 | } | |
1410 | ||
1db1af84 PB |
1411 | asmlinkage void do_msa(struct pt_regs *regs) |
1412 | { | |
1413 | enum ctx_state prev_state; | |
1414 | int err; | |
1415 | ||
1416 | prev_state = exception_enter(); | |
1417 | ||
1418 | if (!cpu_has_msa || test_thread_flag(TIF_32BIT_FPREGS)) { | |
1419 | force_sig(SIGILL, current); | |
1420 | goto out; | |
1421 | } | |
1422 | ||
1423 | die_if_kernel("do_msa invoked from kernel context!", regs); | |
1424 | ||
1425 | err = enable_restore_fp_context(1); | |
1426 | if (err) | |
1427 | force_sig(SIGILL, current); | |
1428 | out: | |
1429 | exception_exit(prev_state); | |
1430 | } | |
1431 | ||
1da177e4 LT |
1432 | asmlinkage void do_mdmx(struct pt_regs *regs) |
1433 | { | |
c3fc5cd5 RB |
1434 | enum ctx_state prev_state; |
1435 | ||
1436 | prev_state = exception_enter(); | |
1da177e4 | 1437 | force_sig(SIGILL, current); |
c3fc5cd5 | 1438 | exception_exit(prev_state); |
1da177e4 LT |
1439 | } |
1440 | ||
8bc6d05b DD |
1441 | /* |
1442 | * Called with interrupts disabled. | |
1443 | */ | |
1da177e4 LT |
1444 | asmlinkage void do_watch(struct pt_regs *regs) |
1445 | { | |
c3fc5cd5 | 1446 | enum ctx_state prev_state; |
b67b2b70 DD |
1447 | u32 cause; |
1448 | ||
c3fc5cd5 | 1449 | prev_state = exception_enter(); |
1da177e4 | 1450 | /* |
b67b2b70 DD |
1451 | * Clear WP (bit 22) bit of cause register so we don't loop |
1452 | * forever. | |
1da177e4 | 1453 | */ |
b67b2b70 DD |
1454 | cause = read_c0_cause(); |
1455 | cause &= ~(1 << 22); | |
1456 | write_c0_cause(cause); | |
1457 | ||
1458 | /* | |
1459 | * If the current thread has the watch registers loaded, save | |
1460 | * their values and send SIGTRAP. Otherwise another thread | |
1461 | * left the registers set, clear them and continue. | |
1462 | */ | |
1463 | if (test_tsk_thread_flag(current, TIF_LOAD_WATCH)) { | |
1464 | mips_read_watch_registers(); | |
8bc6d05b | 1465 | local_irq_enable(); |
b67b2b70 | 1466 | force_sig(SIGTRAP, current); |
8bc6d05b | 1467 | } else { |
b67b2b70 | 1468 | mips_clear_watch_registers(); |
8bc6d05b DD |
1469 | local_irq_enable(); |
1470 | } | |
c3fc5cd5 | 1471 | exception_exit(prev_state); |
1da177e4 LT |
1472 | } |
1473 | ||
1474 | asmlinkage void do_mcheck(struct pt_regs *regs) | |
1475 | { | |
cac4bcbc RB |
1476 | const int field = 2 * sizeof(unsigned long); |
1477 | int multi_match = regs->cp0_status & ST0_TS; | |
c3fc5cd5 | 1478 | enum ctx_state prev_state; |
cac4bcbc | 1479 | |
c3fc5cd5 | 1480 | prev_state = exception_enter(); |
1da177e4 | 1481 | show_regs(regs); |
cac4bcbc RB |
1482 | |
1483 | if (multi_match) { | |
314727fe MC |
1484 | pr_err("Index : %0x\n", read_c0_index()); |
1485 | pr_err("Pagemask: %0x\n", read_c0_pagemask()); | |
1486 | pr_err("EntryHi : %0*lx\n", field, read_c0_entryhi()); | |
1487 | pr_err("EntryLo0: %0*lx\n", field, read_c0_entrylo0()); | |
1488 | pr_err("EntryLo1: %0*lx\n", field, read_c0_entrylo1()); | |
26b40ef1 MC |
1489 | pr_err("Wired : %0x\n", read_c0_wired()); |
1490 | pr_err("Pagegrain: %0x\n", read_c0_pagegrain()); | |
31ec86b8 MC |
1491 | if (cpu_has_htw) { |
1492 | pr_err("PWField : %0*lx\n", field, read_c0_pwfield()); | |
1493 | pr_err("PWSize : %0*lx\n", field, read_c0_pwsize()); | |
1494 | pr_err("PWCtl : %0x\n", read_c0_pwctl()); | |
1495 | } | |
314727fe | 1496 | pr_err("\n"); |
cac4bcbc RB |
1497 | dump_tlb_all(); |
1498 | } | |
1499 | ||
e1bb8289 | 1500 | show_code((unsigned int __user *) regs->cp0_epc); |
cac4bcbc | 1501 | |
1da177e4 LT |
1502 | /* |
1503 | * Some chips may have other causes of machine check (e.g. SB1 | |
1504 | * graduation timer) | |
1505 | */ | |
1506 | panic("Caught Machine Check exception - %scaused by multiple " | |
1507 | "matching entries in the TLB.", | |
cac4bcbc | 1508 | (multi_match) ? "" : "not "); |
1da177e4 LT |
1509 | } |
1510 | ||
340ee4b9 RB |
1511 | asmlinkage void do_mt(struct pt_regs *regs) |
1512 | { | |
41c594ab RB |
1513 | int subcode; |
1514 | ||
41c594ab RB |
1515 | subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT) |
1516 | >> VPECONTROL_EXCPT_SHIFT; | |
1517 | switch (subcode) { | |
1518 | case 0: | |
e35a5e35 | 1519 | printk(KERN_DEBUG "Thread Underflow\n"); |
41c594ab RB |
1520 | break; |
1521 | case 1: | |
e35a5e35 | 1522 | printk(KERN_DEBUG "Thread Overflow\n"); |
41c594ab RB |
1523 | break; |
1524 | case 2: | |
e35a5e35 | 1525 | printk(KERN_DEBUG "Invalid YIELD Qualifier\n"); |
41c594ab RB |
1526 | break; |
1527 | case 3: | |
e35a5e35 | 1528 | printk(KERN_DEBUG "Gating Storage Exception\n"); |
41c594ab RB |
1529 | break; |
1530 | case 4: | |
e35a5e35 | 1531 | printk(KERN_DEBUG "YIELD Scheduler Exception\n"); |
41c594ab RB |
1532 | break; |
1533 | case 5: | |
f232c7e8 | 1534 | printk(KERN_DEBUG "Gating Storage Scheduler Exception\n"); |
41c594ab RB |
1535 | break; |
1536 | default: | |
e35a5e35 | 1537 | printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n", |
41c594ab RB |
1538 | subcode); |
1539 | break; | |
1540 | } | |
340ee4b9 RB |
1541 | die_if_kernel("MIPS MT Thread exception in kernel", regs); |
1542 | ||
1543 | force_sig(SIGILL, current); | |
1544 | } | |
1545 | ||
1546 | ||
e50c0a8f RB |
1547 | asmlinkage void do_dsp(struct pt_regs *regs) |
1548 | { | |
1549 | if (cpu_has_dsp) | |
ab75dc02 | 1550 | panic("Unexpected DSP exception"); |
e50c0a8f RB |
1551 | |
1552 | force_sig(SIGILL, current); | |
1553 | } | |
1554 | ||
1da177e4 LT |
1555 | asmlinkage void do_reserved(struct pt_regs *regs) |
1556 | { | |
1557 | /* | |
70342287 | 1558 | * Game over - no way to handle this if it ever occurs. Most probably |
1da177e4 LT |
1559 | * caused by a new unknown cpu type or after another deadly |
1560 | * hard/software error. | |
1561 | */ | |
1562 | show_regs(regs); | |
1563 | panic("Caught reserved exception %ld - should not happen.", | |
1564 | (regs->cp0_cause & 0x7f) >> 2); | |
1565 | } | |
1566 | ||
39b8d525 RB |
1567 | static int __initdata l1parity = 1; |
1568 | static int __init nol1parity(char *s) | |
1569 | { | |
1570 | l1parity = 0; | |
1571 | return 1; | |
1572 | } | |
1573 | __setup("nol1par", nol1parity); | |
1574 | static int __initdata l2parity = 1; | |
1575 | static int __init nol2parity(char *s) | |
1576 | { | |
1577 | l2parity = 0; | |
1578 | return 1; | |
1579 | } | |
1580 | __setup("nol2par", nol2parity); | |
1581 | ||
1da177e4 LT |
1582 | /* |
1583 | * Some MIPS CPUs can enable/disable for cache parity detection, but do | |
1584 | * it different ways. | |
1585 | */ | |
1586 | static inline void parity_protection_init(void) | |
1587 | { | |
10cc3529 | 1588 | switch (current_cpu_type()) { |
1da177e4 | 1589 | case CPU_24K: |
98a41de9 | 1590 | case CPU_34K: |
39b8d525 RB |
1591 | case CPU_74K: |
1592 | case CPU_1004K: | |
442e14a2 | 1593 | case CPU_1074K: |
26ab96df | 1594 | case CPU_INTERAPTIV: |
708ac4b8 | 1595 | case CPU_PROAPTIV: |
aced4cbd | 1596 | case CPU_P5600: |
4695089f | 1597 | case CPU_QEMU_GENERIC: |
39b8d525 RB |
1598 | { |
1599 | #define ERRCTL_PE 0x80000000 | |
1600 | #define ERRCTL_L2P 0x00800000 | |
1601 | unsigned long errctl; | |
1602 | unsigned int l1parity_present, l2parity_present; | |
1603 | ||
1604 | errctl = read_c0_ecc(); | |
1605 | errctl &= ~(ERRCTL_PE|ERRCTL_L2P); | |
1606 | ||
1607 | /* probe L1 parity support */ | |
1608 | write_c0_ecc(errctl | ERRCTL_PE); | |
1609 | back_to_back_c0_hazard(); | |
1610 | l1parity_present = (read_c0_ecc() & ERRCTL_PE); | |
1611 | ||
1612 | /* probe L2 parity support */ | |
1613 | write_c0_ecc(errctl|ERRCTL_L2P); | |
1614 | back_to_back_c0_hazard(); | |
1615 | l2parity_present = (read_c0_ecc() & ERRCTL_L2P); | |
1616 | ||
1617 | if (l1parity_present && l2parity_present) { | |
1618 | if (l1parity) | |
1619 | errctl |= ERRCTL_PE; | |
1620 | if (l1parity ^ l2parity) | |
1621 | errctl |= ERRCTL_L2P; | |
1622 | } else if (l1parity_present) { | |
1623 | if (l1parity) | |
1624 | errctl |= ERRCTL_PE; | |
1625 | } else if (l2parity_present) { | |
1626 | if (l2parity) | |
1627 | errctl |= ERRCTL_L2P; | |
1628 | } else { | |
1629 | /* No parity available */ | |
1630 | } | |
1631 | ||
1632 | printk(KERN_INFO "Writing ErrCtl register=%08lx\n", errctl); | |
1633 | ||
1634 | write_c0_ecc(errctl); | |
1635 | back_to_back_c0_hazard(); | |
1636 | errctl = read_c0_ecc(); | |
1637 | printk(KERN_INFO "Readback ErrCtl register=%08lx\n", errctl); | |
1638 | ||
1639 | if (l1parity_present) | |
1640 | printk(KERN_INFO "Cache parity protection %sabled\n", | |
1641 | (errctl & ERRCTL_PE) ? "en" : "dis"); | |
1642 | ||
1643 | if (l2parity_present) { | |
1644 | if (l1parity_present && l1parity) | |
1645 | errctl ^= ERRCTL_L2P; | |
1646 | printk(KERN_INFO "L2 cache parity protection %sabled\n", | |
1647 | (errctl & ERRCTL_L2P) ? "en" : "dis"); | |
1648 | } | |
1649 | } | |
1650 | break; | |
1651 | ||
1da177e4 | 1652 | case CPU_5KC: |
78d4803f | 1653 | case CPU_5KE: |
2fa36399 | 1654 | case CPU_LOONGSON1: |
14f18b7f RB |
1655 | write_c0_ecc(0x80000000); |
1656 | back_to_back_c0_hazard(); | |
1657 | /* Set the PE bit (bit 31) in the c0_errctl register. */ | |
1658 | printk(KERN_INFO "Cache parity protection %sabled\n", | |
1659 | (read_c0_ecc() & 0x80000000) ? "en" : "dis"); | |
1da177e4 LT |
1660 | break; |
1661 | case CPU_20KC: | |
1662 | case CPU_25KF: | |
1663 | /* Clear the DE bit (bit 16) in the c0_status register. */ | |
1664 | printk(KERN_INFO "Enable cache parity protection for " | |
1665 | "MIPS 20KC/25KF CPUs.\n"); | |
1666 | clear_c0_status(ST0_DE); | |
1667 | break; | |
1668 | default: | |
1669 | break; | |
1670 | } | |
1671 | } | |
1672 | ||
1673 | asmlinkage void cache_parity_error(void) | |
1674 | { | |
1675 | const int field = 2 * sizeof(unsigned long); | |
1676 | unsigned int reg_val; | |
1677 | ||
1678 | /* For the moment, report the problem and hang. */ | |
1679 | printk("Cache error exception:\n"); | |
1680 | printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc()); | |
1681 | reg_val = read_c0_cacheerr(); | |
1682 | printk("c0_cacheerr == %08x\n", reg_val); | |
1683 | ||
1684 | printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n", | |
1685 | reg_val & (1<<30) ? "secondary" : "primary", | |
1686 | reg_val & (1<<31) ? "data" : "insn"); | |
9c7d5768 | 1687 | if ((cpu_has_mips_r2_r6) && |
721a9205 | 1688 | ((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_MIPS)) { |
6de20451 LY |
1689 | pr_err("Error bits: %s%s%s%s%s%s%s%s\n", |
1690 | reg_val & (1<<29) ? "ED " : "", | |
1691 | reg_val & (1<<28) ? "ET " : "", | |
1692 | reg_val & (1<<27) ? "ES " : "", | |
1693 | reg_val & (1<<26) ? "EE " : "", | |
1694 | reg_val & (1<<25) ? "EB " : "", | |
1695 | reg_val & (1<<24) ? "EI " : "", | |
1696 | reg_val & (1<<23) ? "E1 " : "", | |
1697 | reg_val & (1<<22) ? "E0 " : ""); | |
1698 | } else { | |
1699 | pr_err("Error bits: %s%s%s%s%s%s%s\n", | |
1700 | reg_val & (1<<29) ? "ED " : "", | |
1701 | reg_val & (1<<28) ? "ET " : "", | |
1702 | reg_val & (1<<26) ? "EE " : "", | |
1703 | reg_val & (1<<25) ? "EB " : "", | |
1704 | reg_val & (1<<24) ? "EI " : "", | |
1705 | reg_val & (1<<23) ? "E1 " : "", | |
1706 | reg_val & (1<<22) ? "E0 " : ""); | |
1707 | } | |
1da177e4 LT |
1708 | printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1)); |
1709 | ||
ec917c2c | 1710 | #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) |
1da177e4 LT |
1711 | if (reg_val & (1<<22)) |
1712 | printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0()); | |
1713 | ||
1714 | if (reg_val & (1<<23)) | |
1715 | printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1()); | |
1716 | #endif | |
1717 | ||
1718 | panic("Can't handle the cache error!"); | |
1719 | } | |
1720 | ||
75b5b5e0 LY |
1721 | asmlinkage void do_ftlb(void) |
1722 | { | |
1723 | const int field = 2 * sizeof(unsigned long); | |
1724 | unsigned int reg_val; | |
1725 | ||
1726 | /* For the moment, report the problem and hang. */ | |
9c7d5768 | 1727 | if ((cpu_has_mips_r2_r6) && |
721a9205 | 1728 | ((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_MIPS)) { |
75b5b5e0 LY |
1729 | pr_err("FTLB error exception, cp0_ecc=0x%08x:\n", |
1730 | read_c0_ecc()); | |
1731 | pr_err("cp0_errorepc == %0*lx\n", field, read_c0_errorepc()); | |
1732 | reg_val = read_c0_cacheerr(); | |
1733 | pr_err("c0_cacheerr == %08x\n", reg_val); | |
1734 | ||
1735 | if ((reg_val & 0xc0000000) == 0xc0000000) { | |
1736 | pr_err("Decoded c0_cacheerr: FTLB parity error\n"); | |
1737 | } else { | |
1738 | pr_err("Decoded c0_cacheerr: %s cache fault in %s reference.\n", | |
1739 | reg_val & (1<<30) ? "secondary" : "primary", | |
1740 | reg_val & (1<<31) ? "data" : "insn"); | |
1741 | } | |
1742 | } else { | |
1743 | pr_err("FTLB error exception\n"); | |
1744 | } | |
1745 | /* Just print the cacheerr bits for now */ | |
1746 | cache_parity_error(); | |
1747 | } | |
1748 | ||
1da177e4 LT |
1749 | /* |
1750 | * SDBBP EJTAG debug exception handler. | |
1751 | * We skip the instruction and return to the next instruction. | |
1752 | */ | |
1753 | void ejtag_exception_handler(struct pt_regs *regs) | |
1754 | { | |
1755 | const int field = 2 * sizeof(unsigned long); | |
2a0b24f5 | 1756 | unsigned long depc, old_epc, old_ra; |
1da177e4 LT |
1757 | unsigned int debug; |
1758 | ||
70ae6126 | 1759 | printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n"); |
1da177e4 LT |
1760 | depc = read_c0_depc(); |
1761 | debug = read_c0_debug(); | |
70ae6126 | 1762 | printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug); |
1da177e4 LT |
1763 | if (debug & 0x80000000) { |
1764 | /* | |
1765 | * In branch delay slot. | |
1766 | * We cheat a little bit here and use EPC to calculate the | |
1767 | * debug return address (DEPC). EPC is restored after the | |
1768 | * calculation. | |
1769 | */ | |
1770 | old_epc = regs->cp0_epc; | |
2a0b24f5 | 1771 | old_ra = regs->regs[31]; |
1da177e4 | 1772 | regs->cp0_epc = depc; |
2a0b24f5 | 1773 | compute_return_epc(regs); |
1da177e4 LT |
1774 | depc = regs->cp0_epc; |
1775 | regs->cp0_epc = old_epc; | |
2a0b24f5 | 1776 | regs->regs[31] = old_ra; |
1da177e4 LT |
1777 | } else |
1778 | depc += 4; | |
1779 | write_c0_depc(depc); | |
1780 | ||
1781 | #if 0 | |
70ae6126 | 1782 | printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n"); |
1da177e4 LT |
1783 | write_c0_debug(debug | 0x100); |
1784 | #endif | |
1785 | } | |
1786 | ||
1787 | /* | |
1788 | * NMI exception handler. | |
34bd92e2 | 1789 | * No lock; only written during early bootup by CPU 0. |
1da177e4 | 1790 | */ |
34bd92e2 KC |
1791 | static RAW_NOTIFIER_HEAD(nmi_chain); |
1792 | ||
1793 | int register_nmi_notifier(struct notifier_block *nb) | |
1794 | { | |
1795 | return raw_notifier_chain_register(&nmi_chain, nb); | |
1796 | } | |
1797 | ||
ff2d8b19 | 1798 | void __noreturn nmi_exception_handler(struct pt_regs *regs) |
1da177e4 | 1799 | { |
83e4da1e LY |
1800 | char str[100]; |
1801 | ||
34bd92e2 | 1802 | raw_notifier_call_chain(&nmi_chain, 0, regs); |
41c594ab | 1803 | bust_spinlocks(1); |
83e4da1e LY |
1804 | snprintf(str, 100, "CPU%d NMI taken, CP0_EPC=%lx\n", |
1805 | smp_processor_id(), regs->cp0_epc); | |
1806 | regs->cp0_epc = read_c0_errorepc(); | |
1807 | die(str, regs); | |
1da177e4 LT |
1808 | } |
1809 | ||
e01402b1 RB |
1810 | #define VECTORSPACING 0x100 /* for EI/VI mode */ |
1811 | ||
1812 | unsigned long ebase; | |
1da177e4 | 1813 | unsigned long exception_handlers[32]; |
e01402b1 | 1814 | unsigned long vi_handlers[64]; |
1da177e4 | 1815 | |
2d1b6e95 | 1816 | void __init *set_except_vector(int n, void *addr) |
1da177e4 LT |
1817 | { |
1818 | unsigned long handler = (unsigned long) addr; | |
b22d1b6a | 1819 | unsigned long old_handler; |
1da177e4 | 1820 | |
2a0b24f5 SH |
1821 | #ifdef CONFIG_CPU_MICROMIPS |
1822 | /* | |
1823 | * Only the TLB handlers are cache aligned with an even | |
1824 | * address. All other handlers are on an odd address and | |
1825 | * require no modification. Otherwise, MIPS32 mode will | |
1826 | * be entered when handling any TLB exceptions. That | |
1827 | * would be bad...since we must stay in microMIPS mode. | |
1828 | */ | |
1829 | if (!(handler & 0x1)) | |
1830 | handler |= 1; | |
1831 | #endif | |
b22d1b6a | 1832 | old_handler = xchg(&exception_handlers[n], handler); |
1da177e4 | 1833 | |
1da177e4 | 1834 | if (n == 0 && cpu_has_divec) { |
2a0b24f5 SH |
1835 | #ifdef CONFIG_CPU_MICROMIPS |
1836 | unsigned long jump_mask = ~((1 << 27) - 1); | |
1837 | #else | |
92bbe1b9 | 1838 | unsigned long jump_mask = ~((1 << 28) - 1); |
2a0b24f5 | 1839 | #endif |
92bbe1b9 FF |
1840 | u32 *buf = (u32 *)(ebase + 0x200); |
1841 | unsigned int k0 = 26; | |
1842 | if ((handler & jump_mask) == ((ebase + 0x200) & jump_mask)) { | |
1843 | uasm_i_j(&buf, handler & ~jump_mask); | |
1844 | uasm_i_nop(&buf); | |
1845 | } else { | |
1846 | UASM_i_LA(&buf, k0, handler); | |
1847 | uasm_i_jr(&buf, k0); | |
1848 | uasm_i_nop(&buf); | |
1849 | } | |
1850 | local_flush_icache_range(ebase + 0x200, (unsigned long)buf); | |
e01402b1 RB |
1851 | } |
1852 | return (void *)old_handler; | |
1853 | } | |
1854 | ||
86a1708a | 1855 | static void do_default_vi(void) |
6ba07e59 AN |
1856 | { |
1857 | show_regs(get_irq_regs()); | |
1858 | panic("Caught unexpected vectored interrupt."); | |
1859 | } | |
1860 | ||
ef300e42 | 1861 | static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs) |
e01402b1 RB |
1862 | { |
1863 | unsigned long handler; | |
1864 | unsigned long old_handler = vi_handlers[n]; | |
f6771dbb | 1865 | int srssets = current_cpu_data.srsets; |
2a0b24f5 | 1866 | u16 *h; |
e01402b1 RB |
1867 | unsigned char *b; |
1868 | ||
b72b7092 | 1869 | BUG_ON(!cpu_has_veic && !cpu_has_vint); |
e01402b1 RB |
1870 | |
1871 | if (addr == NULL) { | |
1872 | handler = (unsigned long) do_default_vi; | |
1873 | srs = 0; | |
41c594ab | 1874 | } else |
e01402b1 | 1875 | handler = (unsigned long) addr; |
2a0b24f5 | 1876 | vi_handlers[n] = handler; |
e01402b1 RB |
1877 | |
1878 | b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING); | |
1879 | ||
f6771dbb | 1880 | if (srs >= srssets) |
e01402b1 RB |
1881 | panic("Shadow register set %d not supported", srs); |
1882 | ||
1883 | if (cpu_has_veic) { | |
1884 | if (board_bind_eic_interrupt) | |
49a89efb | 1885 | board_bind_eic_interrupt(n, srs); |
41c594ab | 1886 | } else if (cpu_has_vint) { |
e01402b1 | 1887 | /* SRSMap is only defined if shadow sets are implemented */ |
f6771dbb | 1888 | if (srssets > 1) |
49a89efb | 1889 | change_c0_srsmap(0xf << n*4, srs << n*4); |
e01402b1 RB |
1890 | } |
1891 | ||
1892 | if (srs == 0) { | |
1893 | /* | |
1894 | * If no shadow set is selected then use the default handler | |
2a0b24f5 | 1895 | * that does normal register saving and standard interrupt exit |
e01402b1 | 1896 | */ |
e01402b1 RB |
1897 | extern char except_vec_vi, except_vec_vi_lui; |
1898 | extern char except_vec_vi_ori, except_vec_vi_end; | |
c65a5480 | 1899 | extern char rollback_except_vec_vi; |
f94d9a8e | 1900 | char *vec_start = using_rollback_handler() ? |
c65a5480 | 1901 | &rollback_except_vec_vi : &except_vec_vi; |
2a0b24f5 SH |
1902 | #if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_BIG_ENDIAN) |
1903 | const int lui_offset = &except_vec_vi_lui - vec_start + 2; | |
1904 | const int ori_offset = &except_vec_vi_ori - vec_start + 2; | |
1905 | #else | |
c65a5480 AN |
1906 | const int lui_offset = &except_vec_vi_lui - vec_start; |
1907 | const int ori_offset = &except_vec_vi_ori - vec_start; | |
2a0b24f5 SH |
1908 | #endif |
1909 | const int handler_len = &except_vec_vi_end - vec_start; | |
e01402b1 RB |
1910 | |
1911 | if (handler_len > VECTORSPACING) { | |
1912 | /* | |
1913 | * Sigh... panicing won't help as the console | |
1914 | * is probably not configured :( | |
1915 | */ | |
49a89efb | 1916 | panic("VECTORSPACING too small"); |
e01402b1 RB |
1917 | } |
1918 | ||
2a0b24f5 SH |
1919 | set_handler(((unsigned long)b - ebase), vec_start, |
1920 | #ifdef CONFIG_CPU_MICROMIPS | |
1921 | (handler_len - 1)); | |
1922 | #else | |
1923 | handler_len); | |
1924 | #endif | |
2a0b24f5 SH |
1925 | h = (u16 *)(b + lui_offset); |
1926 | *h = (handler >> 16) & 0xffff; | |
1927 | h = (u16 *)(b + ori_offset); | |
1928 | *h = (handler & 0xffff); | |
e0cee3ee TB |
1929 | local_flush_icache_range((unsigned long)b, |
1930 | (unsigned long)(b+handler_len)); | |
e01402b1 RB |
1931 | } |
1932 | else { | |
1933 | /* | |
2a0b24f5 SH |
1934 | * In other cases jump directly to the interrupt handler. It |
1935 | * is the handler's responsibility to save registers if required | |
1936 | * (eg hi/lo) and return from the exception using "eret". | |
e01402b1 | 1937 | */ |
2a0b24f5 SH |
1938 | u32 insn; |
1939 | ||
1940 | h = (u16 *)b; | |
1941 | /* j handler */ | |
1942 | #ifdef CONFIG_CPU_MICROMIPS | |
1943 | insn = 0xd4000000 | (((u32)handler & 0x07ffffff) >> 1); | |
1944 | #else | |
1945 | insn = 0x08000000 | (((u32)handler & 0x0fffffff) >> 2); | |
1946 | #endif | |
1947 | h[0] = (insn >> 16) & 0xffff; | |
1948 | h[1] = insn & 0xffff; | |
1949 | h[2] = 0; | |
1950 | h[3] = 0; | |
e0cee3ee TB |
1951 | local_flush_icache_range((unsigned long)b, |
1952 | (unsigned long)(b+8)); | |
1da177e4 | 1953 | } |
e01402b1 | 1954 | |
1da177e4 LT |
1955 | return (void *)old_handler; |
1956 | } | |
1957 | ||
ef300e42 | 1958 | void *set_vi_handler(int n, vi_handler_t addr) |
e01402b1 | 1959 | { |
ff3eab2a | 1960 | return set_vi_srs_handler(n, addr, 0); |
e01402b1 | 1961 | } |
f41ae0b2 | 1962 | |
1da177e4 LT |
1963 | extern void tlb_init(void); |
1964 | ||
42f77542 RB |
1965 | /* |
1966 | * Timer interrupt | |
1967 | */ | |
1968 | int cp0_compare_irq; | |
68b6352c | 1969 | EXPORT_SYMBOL_GPL(cp0_compare_irq); |
010c108d | 1970 | int cp0_compare_irq_shift; |
42f77542 RB |
1971 | |
1972 | /* | |
1973 | * Performance counter IRQ or -1 if shared with timer | |
1974 | */ | |
1975 | int cp0_perfcount_irq; | |
1976 | EXPORT_SYMBOL_GPL(cp0_perfcount_irq); | |
1977 | ||
8f7ff027 JH |
1978 | /* |
1979 | * Fast debug channel IRQ or -1 if not present | |
1980 | */ | |
1981 | int cp0_fdc_irq; | |
1982 | EXPORT_SYMBOL_GPL(cp0_fdc_irq); | |
1983 | ||
078a55fc | 1984 | static int noulri; |
bdc94eb4 CD |
1985 | |
1986 | static int __init ulri_disable(char *s) | |
1987 | { | |
1988 | pr_info("Disabling ulri\n"); | |
1989 | noulri = 1; | |
1990 | ||
1991 | return 1; | |
1992 | } | |
1993 | __setup("noulri", ulri_disable); | |
1994 | ||
ae4ce454 JH |
1995 | /* configure STATUS register */ |
1996 | static void configure_status(void) | |
1da177e4 | 1997 | { |
1da177e4 LT |
1998 | /* |
1999 | * Disable coprocessors and select 32-bit or 64-bit addressing | |
2000 | * and the 16/32 or 32/32 FPR register model. Reset the BEV | |
2001 | * flag that some firmware may have left set and the TS bit (for | |
2002 | * IP27). Set XX for ISA IV code to work. | |
2003 | */ | |
ae4ce454 | 2004 | unsigned int status_set = ST0_CU0; |
875d43e7 | 2005 | #ifdef CONFIG_64BIT |
1da177e4 LT |
2006 | status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX; |
2007 | #endif | |
adb37892 | 2008 | if (current_cpu_data.isa_level & MIPS_CPU_ISA_IV) |
1da177e4 | 2009 | status_set |= ST0_XX; |
bbaf238b CD |
2010 | if (cpu_has_dsp) |
2011 | status_set |= ST0_MX; | |
2012 | ||
b38c7399 | 2013 | change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX, |
1da177e4 | 2014 | status_set); |
ae4ce454 JH |
2015 | } |
2016 | ||
2017 | /* configure HWRENA register */ | |
2018 | static void configure_hwrena(void) | |
2019 | { | |
2020 | unsigned int hwrena = cpu_hwrena_impl_bits; | |
1da177e4 | 2021 | |
9c7d5768 | 2022 | if (cpu_has_mips_r2_r6) |
18d693b3 | 2023 | hwrena |= 0x0000000f; |
a3692020 | 2024 | |
18d693b3 KC |
2025 | if (!noulri && cpu_has_userlocal) |
2026 | hwrena |= (1 << 29); | |
a3692020 | 2027 | |
18d693b3 KC |
2028 | if (hwrena) |
2029 | write_c0_hwrena(hwrena); | |
ae4ce454 | 2030 | } |
e01402b1 | 2031 | |
ae4ce454 JH |
2032 | static void configure_exception_vector(void) |
2033 | { | |
e01402b1 | 2034 | if (cpu_has_veic || cpu_has_vint) { |
9fb4c2b9 | 2035 | unsigned long sr = set_c0_status(ST0_BEV); |
49a89efb | 2036 | write_c0_ebase(ebase); |
9fb4c2b9 | 2037 | write_c0_status(sr); |
e01402b1 | 2038 | /* Setting vector spacing enables EI/VI mode */ |
49a89efb | 2039 | change_c0_intctl(0x3e0, VECTORSPACING); |
e01402b1 | 2040 | } |
d03d0a57 RB |
2041 | if (cpu_has_divec) { |
2042 | if (cpu_has_mipsmt) { | |
2043 | unsigned int vpflags = dvpe(); | |
2044 | set_c0_cause(CAUSEF_IV); | |
2045 | evpe(vpflags); | |
2046 | } else | |
2047 | set_c0_cause(CAUSEF_IV); | |
2048 | } | |
ae4ce454 JH |
2049 | } |
2050 | ||
2051 | void per_cpu_trap_init(bool is_boot_cpu) | |
2052 | { | |
2053 | unsigned int cpu = smp_processor_id(); | |
ae4ce454 JH |
2054 | |
2055 | configure_status(); | |
2056 | configure_hwrena(); | |
2057 | ||
ae4ce454 | 2058 | configure_exception_vector(); |
3b1d4ed5 RB |
2059 | |
2060 | /* | |
2061 | * Before R2 both interrupt numbers were fixed to 7, so on R2 only: | |
2062 | * | |
2063 | * o read IntCtl.IPTI to determine the timer interrupt | |
2064 | * o read IntCtl.IPPCI to determine the performance counter interrupt | |
8f7ff027 | 2065 | * o read IntCtl.IPFDC to determine the fast debug channel interrupt |
3b1d4ed5 | 2066 | */ |
9c7d5768 | 2067 | if (cpu_has_mips_r2_r6) { |
010c108d DV |
2068 | cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP; |
2069 | cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7; | |
2070 | cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7; | |
8f7ff027 JH |
2071 | cp0_fdc_irq = (read_c0_intctl() >> INTCTLB_IPFDC) & 7; |
2072 | if (!cp0_fdc_irq) | |
2073 | cp0_fdc_irq = -1; | |
2074 | ||
c3e838a2 CD |
2075 | } else { |
2076 | cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ; | |
c6a4ebb9 | 2077 | cp0_compare_irq_shift = CP0_LEGACY_PERFCNT_IRQ; |
c3e838a2 | 2078 | cp0_perfcount_irq = -1; |
8f7ff027 | 2079 | cp0_fdc_irq = -1; |
3b1d4ed5 RB |
2080 | } |
2081 | ||
48c4ac97 DD |
2082 | if (!cpu_data[cpu].asid_cache) |
2083 | cpu_data[cpu].asid_cache = ASID_FIRST_VERSION; | |
1da177e4 LT |
2084 | |
2085 | atomic_inc(&init_mm.mm_count); | |
2086 | current->active_mm = &init_mm; | |
2087 | BUG_ON(current->mm); | |
2088 | enter_lazy_tlb(&init_mm, current); | |
2089 | ||
6650df3c DD |
2090 | /* Boot CPU's cache setup in setup_arch(). */ |
2091 | if (!is_boot_cpu) | |
2092 | cpu_cache_init(); | |
41c594ab | 2093 | tlb_init(); |
3d8bfdd0 | 2094 | TLBMISS_HANDLER_SETUP(); |
1da177e4 LT |
2095 | } |
2096 | ||
e01402b1 | 2097 | /* Install CPU exception handler */ |
078a55fc | 2098 | void set_handler(unsigned long offset, void *addr, unsigned long size) |
e01402b1 | 2099 | { |
2a0b24f5 SH |
2100 | #ifdef CONFIG_CPU_MICROMIPS |
2101 | memcpy((void *)(ebase + offset), ((unsigned char *)addr - 1), size); | |
2102 | #else | |
e01402b1 | 2103 | memcpy((void *)(ebase + offset), addr, size); |
2a0b24f5 | 2104 | #endif |
e0cee3ee | 2105 | local_flush_icache_range(ebase + offset, ebase + offset + size); |
e01402b1 RB |
2106 | } |
2107 | ||
078a55fc | 2108 | static char panic_null_cerr[] = |
641e97f3 RB |
2109 | "Trying to set NULL cache error exception handler"; |
2110 | ||
42fe7ee3 RB |
2111 | /* |
2112 | * Install uncached CPU exception handler. | |
2113 | * This is suitable only for the cache error exception which is the only | |
2114 | * exception handler that is being run uncached. | |
2115 | */ | |
078a55fc | 2116 | void set_uncached_handler(unsigned long offset, void *addr, |
234fcd14 | 2117 | unsigned long size) |
e01402b1 | 2118 | { |
4f81b01a | 2119 | unsigned long uncached_ebase = CKSEG1ADDR(ebase); |
e01402b1 | 2120 | |
641e97f3 RB |
2121 | if (!addr) |
2122 | panic(panic_null_cerr); | |
2123 | ||
e01402b1 RB |
2124 | memcpy((void *)(uncached_ebase + offset), addr, size); |
2125 | } | |
2126 | ||
5b10496b AN |
2127 | static int __initdata rdhwr_noopt; |
2128 | static int __init set_rdhwr_noopt(char *str) | |
2129 | { | |
2130 | rdhwr_noopt = 1; | |
2131 | return 1; | |
2132 | } | |
2133 | ||
2134 | __setup("rdhwr_noopt", set_rdhwr_noopt); | |
2135 | ||
1da177e4 LT |
2136 | void __init trap_init(void) |
2137 | { | |
2a0b24f5 | 2138 | extern char except_vec3_generic; |
1da177e4 | 2139 | extern char except_vec4; |
2a0b24f5 | 2140 | extern char except_vec3_r4000; |
1da177e4 | 2141 | unsigned long i; |
c65a5480 AN |
2142 | |
2143 | check_wait(); | |
1da177e4 | 2144 | |
88547001 JW |
2145 | #if defined(CONFIG_KGDB) |
2146 | if (kgdb_early_setup) | |
70342287 | 2147 | return; /* Already done */ |
88547001 JW |
2148 | #endif |
2149 | ||
9fb4c2b9 CD |
2150 | if (cpu_has_veic || cpu_has_vint) { |
2151 | unsigned long size = 0x200 + VECTORSPACING*64; | |
2152 | ebase = (unsigned long) | |
2153 | __alloc_bootmem(size, 1 << fls(size), 0); | |
2154 | } else { | |
9843b030 SL |
2155 | #ifdef CONFIG_KVM_GUEST |
2156 | #define KVM_GUEST_KSEG0 0x40000000 | |
2157 | ebase = KVM_GUEST_KSEG0; | |
2158 | #else | |
2159 | ebase = CKSEG0; | |
2160 | #endif | |
9c7d5768 | 2161 | if (cpu_has_mips_r2_r6) |
566f74f6 DD |
2162 | ebase += (read_c0_ebase() & 0x3ffff000); |
2163 | } | |
e01402b1 | 2164 | |
c6213c6c SH |
2165 | if (cpu_has_mmips) { |
2166 | unsigned int config3 = read_c0_config3(); | |
2167 | ||
2168 | if (IS_ENABLED(CONFIG_CPU_MICROMIPS)) | |
2169 | write_c0_config3(config3 | MIPS_CONF3_ISA_OE); | |
2170 | else | |
2171 | write_c0_config3(config3 & ~MIPS_CONF3_ISA_OE); | |
2172 | } | |
2173 | ||
6fb97eff KC |
2174 | if (board_ebase_setup) |
2175 | board_ebase_setup(); | |
6650df3c | 2176 | per_cpu_trap_init(true); |
1da177e4 LT |
2177 | |
2178 | /* | |
2179 | * Copy the generic exception handlers to their final destination. | |
2180 | * This will be overriden later as suitable for a particular | |
2181 | * configuration. | |
2182 | */ | |
e01402b1 | 2183 | set_handler(0x180, &except_vec3_generic, 0x80); |
1da177e4 LT |
2184 | |
2185 | /* | |
2186 | * Setup default vectors | |
2187 | */ | |
2188 | for (i = 0; i <= 31; i++) | |
2189 | set_except_vector(i, handle_reserved); | |
2190 | ||
2191 | /* | |
2192 | * Copy the EJTAG debug exception vector handler code to it's final | |
2193 | * destination. | |
2194 | */ | |
e01402b1 | 2195 | if (cpu_has_ejtag && board_ejtag_handler_setup) |
49a89efb | 2196 | board_ejtag_handler_setup(); |
1da177e4 LT |
2197 | |
2198 | /* | |
2199 | * Only some CPUs have the watch exceptions. | |
2200 | */ | |
2201 | if (cpu_has_watch) | |
2202 | set_except_vector(23, handle_watch); | |
2203 | ||
2204 | /* | |
e01402b1 | 2205 | * Initialise interrupt handlers |
1da177e4 | 2206 | */ |
e01402b1 RB |
2207 | if (cpu_has_veic || cpu_has_vint) { |
2208 | int nvec = cpu_has_veic ? 64 : 8; | |
2209 | for (i = 0; i < nvec; i++) | |
ff3eab2a | 2210 | set_vi_handler(i, NULL); |
e01402b1 RB |
2211 | } |
2212 | else if (cpu_has_divec) | |
2213 | set_handler(0x200, &except_vec4, 0x8); | |
1da177e4 LT |
2214 | |
2215 | /* | |
2216 | * Some CPUs can enable/disable for cache parity detection, but does | |
2217 | * it different ways. | |
2218 | */ | |
2219 | parity_protection_init(); | |
2220 | ||
2221 | /* | |
2222 | * The Data Bus Errors / Instruction Bus Errors are signaled | |
2223 | * by external hardware. Therefore these two exceptions | |
2224 | * may have board specific handlers. | |
2225 | */ | |
2226 | if (board_be_init) | |
2227 | board_be_init(); | |
2228 | ||
f94d9a8e RB |
2229 | set_except_vector(0, using_rollback_handler() ? rollback_handle_int |
2230 | : handle_int); | |
1da177e4 LT |
2231 | set_except_vector(1, handle_tlbm); |
2232 | set_except_vector(2, handle_tlbl); | |
2233 | set_except_vector(3, handle_tlbs); | |
2234 | ||
2235 | set_except_vector(4, handle_adel); | |
2236 | set_except_vector(5, handle_ades); | |
2237 | ||
2238 | set_except_vector(6, handle_ibe); | |
2239 | set_except_vector(7, handle_dbe); | |
2240 | ||
2241 | set_except_vector(8, handle_sys); | |
2242 | set_except_vector(9, handle_bp); | |
5b10496b AN |
2243 | set_except_vector(10, rdhwr_noopt ? handle_ri : |
2244 | (cpu_has_vtag_icache ? | |
2245 | handle_ri_rdhwr_vivt : handle_ri_rdhwr)); | |
1da177e4 LT |
2246 | set_except_vector(11, handle_cpu); |
2247 | set_except_vector(12, handle_ov); | |
2248 | set_except_vector(13, handle_tr); | |
2bcb3fbc | 2249 | set_except_vector(14, handle_msa_fpe); |
1da177e4 | 2250 | |
10cc3529 RB |
2251 | if (current_cpu_type() == CPU_R6000 || |
2252 | current_cpu_type() == CPU_R6000A) { | |
1da177e4 LT |
2253 | /* |
2254 | * The R6000 is the only R-series CPU that features a machine | |
2255 | * check exception (similar to the R4000 cache error) and | |
2256 | * unaligned ldc1/sdc1 exception. The handlers have not been | |
70342287 | 2257 | * written yet. Well, anyway there is no R6000 machine on the |
1da177e4 LT |
2258 | * current list of targets for Linux/MIPS. |
2259 | * (Duh, crap, there is someone with a triple R6k machine) | |
2260 | */ | |
2261 | //set_except_vector(14, handle_mc); | |
2262 | //set_except_vector(15, handle_ndc); | |
2263 | } | |
2264 | ||
e01402b1 RB |
2265 | |
2266 | if (board_nmi_handler_setup) | |
2267 | board_nmi_handler_setup(); | |
2268 | ||
e50c0a8f RB |
2269 | if (cpu_has_fpu && !cpu_has_nofpuex) |
2270 | set_except_vector(15, handle_fpe); | |
2271 | ||
75b5b5e0 | 2272 | set_except_vector(16, handle_ftlb); |
5890f70f LY |
2273 | |
2274 | if (cpu_has_rixiex) { | |
2275 | set_except_vector(19, tlb_do_page_fault_0); | |
2276 | set_except_vector(20, tlb_do_page_fault_0); | |
2277 | } | |
2278 | ||
1db1af84 | 2279 | set_except_vector(21, handle_msa); |
e50c0a8f RB |
2280 | set_except_vector(22, handle_mdmx); |
2281 | ||
2282 | if (cpu_has_mcheck) | |
2283 | set_except_vector(24, handle_mcheck); | |
2284 | ||
340ee4b9 RB |
2285 | if (cpu_has_mipsmt) |
2286 | set_except_vector(25, handle_mt); | |
2287 | ||
acaec427 | 2288 | set_except_vector(26, handle_dsp); |
e50c0a8f | 2289 | |
fcbf1dfd DD |
2290 | if (board_cache_error_setup) |
2291 | board_cache_error_setup(); | |
2292 | ||
e50c0a8f RB |
2293 | if (cpu_has_vce) |
2294 | /* Special exception: R4[04]00 uses also the divec space. */ | |
2a0b24f5 | 2295 | set_handler(0x180, &except_vec3_r4000, 0x100); |
e50c0a8f | 2296 | else if (cpu_has_4kex) |
2a0b24f5 | 2297 | set_handler(0x180, &except_vec3_generic, 0x80); |
e50c0a8f | 2298 | else |
2a0b24f5 | 2299 | set_handler(0x080, &except_vec3_generic, 0x80); |
e50c0a8f | 2300 | |
e0cee3ee | 2301 | local_flush_icache_range(ebase, ebase + 0x400); |
0510617b TB |
2302 | |
2303 | sort_extable(__start___dbe_table, __stop___dbe_table); | |
69f3a7de | 2304 | |
4483b159 | 2305 | cu2_notifier(default_cu2_call, 0x80000000); /* Run last */ |
1da177e4 | 2306 | } |
ae4ce454 JH |
2307 | |
2308 | static int trap_pm_notifier(struct notifier_block *self, unsigned long cmd, | |
2309 | void *v) | |
2310 | { | |
2311 | switch (cmd) { | |
2312 | case CPU_PM_ENTER_FAILED: | |
2313 | case CPU_PM_EXIT: | |
2314 | configure_status(); | |
2315 | configure_hwrena(); | |
2316 | configure_exception_vector(); | |
2317 | ||
2318 | /* Restore register with CPU number for TLB handlers */ | |
2319 | TLBMISS_HANDLER_RESTORE(); | |
2320 | ||
2321 | break; | |
2322 | } | |
2323 | ||
2324 | return NOTIFY_OK; | |
2325 | } | |
2326 | ||
2327 | static struct notifier_block trap_pm_notifier_block = { | |
2328 | .notifier_call = trap_pm_notifier, | |
2329 | }; | |
2330 | ||
2331 | static int __init trap_pm_init(void) | |
2332 | { | |
2333 | return cpu_pm_register_notifier(&trap_pm_notifier_block); | |
2334 | } | |
2335 | arch_initcall(trap_pm_init); |