Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Handle unaligned accesses by emulation. | |
3 | * | |
4 | * This file is subject to the terms and conditions of the GNU General Public | |
5 | * License. See the file "COPYING" in the main directory of this archive | |
6 | * for more details. | |
7 | * | |
8 | * Copyright (C) 1996, 1998, 1999, 2002 by Ralf Baechle | |
9 | * Copyright (C) 1999 Silicon Graphics, Inc. | |
10 | * | |
11 | * This file contains exception handler for address error exception with the | |
12 | * special capability to execute faulting instructions in software. The | |
13 | * handler does not try to handle the case when the program counter points | |
14 | * to an address not aligned to a word boundary. | |
15 | * | |
16 | * Putting data to unaligned addresses is a bad practice even on Intel where | |
17 | * only the performance is affected. Much worse is that such code is non- | |
18 | * portable. Due to several programs that die on MIPS due to alignment | |
19 | * problems I decided to implement this handler anyway though I originally | |
20 | * didn't intend to do this at all for user code. | |
21 | * | |
22 | * For now I enable fixing of address errors by default to make life easier. | |
23 | * I however intend to disable this somewhen in the future when the alignment | |
24 | * problems with user programs have been fixed. For programmers this is the | |
25 | * right way to go. | |
26 | * | |
27 | * Fixing address errors is a per process option. The option is inherited | |
28 | * across fork(2) and execve(2) calls. If you really want to use the | |
29 | * option in your user programs - I discourage the use of the software | |
30 | * emulation strongly - use the following code in your userland stuff: | |
31 | * | |
32 | * #include <sys/sysmips.h> | |
33 | * | |
34 | * ... | |
35 | * sysmips(MIPS_FIXADE, x); | |
36 | * ... | |
37 | * | |
38 | * The argument x is 0 for disabling software emulation, enabled otherwise. | |
39 | * | |
40 | * Below a little program to play around with this feature. | |
41 | * | |
42 | * #include <stdio.h> | |
43 | * #include <sys/sysmips.h> | |
44 | * | |
45 | * struct foo { | |
46 | * unsigned char bar[8]; | |
47 | * }; | |
48 | * | |
49 | * main(int argc, char *argv[]) | |
50 | * { | |
51 | * struct foo x = {0, 1, 2, 3, 4, 5, 6, 7}; | |
52 | * unsigned int *p = (unsigned int *) (x.bar + 3); | |
53 | * int i; | |
54 | * | |
55 | * if (argc > 1) | |
56 | * sysmips(MIPS_FIXADE, atoi(argv[1])); | |
57 | * | |
58 | * printf("*p = %08lx\n", *p); | |
59 | * | |
60 | * *p = 0xdeadface; | |
61 | * | |
62 | * for(i = 0; i <= 7; i++) | |
63 | * printf("%02x ", x.bar[i]); | |
64 | * printf("\n"); | |
65 | * } | |
66 | * | |
67 | * Coprocessor loads are not supported; I think this case is unimportant | |
68 | * in the practice. | |
69 | * | |
70 | * TODO: Handle ndc (attempted store to doubleword in uncached memory) | |
71 | * exception for the R6000. | |
72 | * A store crossing a page boundary might be executed only partially. | |
73 | * Undo the partial store in this case. | |
74 | */ | |
1da177e4 LT |
75 | #include <linux/mm.h> |
76 | #include <linux/module.h> | |
77 | #include <linux/signal.h> | |
78 | #include <linux/smp.h> | |
e8edc6e0 | 79 | #include <linux/sched.h> |
6312e0ee | 80 | #include <linux/debugfs.h> |
1da177e4 LT |
81 | #include <asm/asm.h> |
82 | #include <asm/branch.h> | |
83 | #include <asm/byteorder.h> | |
84 | #include <asm/inst.h> | |
85 | #include <asm/uaccess.h> | |
86 | #include <asm/system.h> | |
87 | ||
88 | #define STR(x) __STR(x) | |
89 | #define __STR(x) #x | |
90 | ||
6312e0ee AN |
91 | enum { |
92 | UNALIGNED_ACTION_QUIET, | |
93 | UNALIGNED_ACTION_SIGNAL, | |
94 | UNALIGNED_ACTION_SHOW, | |
95 | }; | |
96 | #ifdef CONFIG_DEBUG_FS | |
97 | static u32 unaligned_instructions; | |
98 | static u32 unaligned_action; | |
99 | #else | |
100 | #define unaligned_action UNALIGNED_ACTION_QUIET | |
1da177e4 | 101 | #endif |
6312e0ee | 102 | extern void show_registers(struct pt_regs *regs); |
1da177e4 LT |
103 | |
104 | static inline int emulate_load_store_insn(struct pt_regs *regs, | |
fe00f943 | 105 | void __user *addr, unsigned int __user *pc, |
1da177e4 LT |
106 | unsigned long **regptr, unsigned long *newvalue) |
107 | { | |
108 | union mips_instruction insn; | |
109 | unsigned long value; | |
110 | unsigned int res; | |
111 | ||
112 | regs->regs[0] = 0; | |
113 | *regptr=NULL; | |
114 | ||
115 | /* | |
116 | * This load never faults. | |
117 | */ | |
fe00f943 | 118 | __get_user(insn.word, pc); |
1da177e4 LT |
119 | |
120 | switch (insn.i_format.opcode) { | |
121 | /* | |
122 | * These are instructions that a compiler doesn't generate. We | |
123 | * can assume therefore that the code is MIPS-aware and | |
124 | * really buggy. Emulating these instructions would break the | |
125 | * semantics anyway. | |
126 | */ | |
127 | case ll_op: | |
128 | case lld_op: | |
129 | case sc_op: | |
130 | case scd_op: | |
131 | ||
132 | /* | |
133 | * For these instructions the only way to create an address | |
134 | * error is an attempted access to kernel/supervisor address | |
135 | * space. | |
136 | */ | |
137 | case ldl_op: | |
138 | case ldr_op: | |
139 | case lwl_op: | |
140 | case lwr_op: | |
141 | case sdl_op: | |
142 | case sdr_op: | |
143 | case swl_op: | |
144 | case swr_op: | |
145 | case lb_op: | |
146 | case lbu_op: | |
147 | case sb_op: | |
148 | goto sigbus; | |
149 | ||
150 | /* | |
151 | * The remaining opcodes are the ones that are really of interest. | |
152 | */ | |
153 | case lh_op: | |
154 | if (!access_ok(VERIFY_READ, addr, 2)) | |
155 | goto sigbus; | |
156 | ||
157 | __asm__ __volatile__ (".set\tnoat\n" | |
158 | #ifdef __BIG_ENDIAN | |
159 | "1:\tlb\t%0, 0(%2)\n" | |
160 | "2:\tlbu\t$1, 1(%2)\n\t" | |
161 | #endif | |
162 | #ifdef __LITTLE_ENDIAN | |
163 | "1:\tlb\t%0, 1(%2)\n" | |
164 | "2:\tlbu\t$1, 0(%2)\n\t" | |
165 | #endif | |
166 | "sll\t%0, 0x8\n\t" | |
167 | "or\t%0, $1\n\t" | |
168 | "li\t%1, 0\n" | |
169 | "3:\t.set\tat\n\t" | |
170 | ".section\t.fixup,\"ax\"\n\t" | |
171 | "4:\tli\t%1, %3\n\t" | |
172 | "j\t3b\n\t" | |
173 | ".previous\n\t" | |
174 | ".section\t__ex_table,\"a\"\n\t" | |
175 | STR(PTR)"\t1b, 4b\n\t" | |
176 | STR(PTR)"\t2b, 4b\n\t" | |
177 | ".previous" | |
178 | : "=&r" (value), "=r" (res) | |
179 | : "r" (addr), "i" (-EFAULT)); | |
180 | if (res) | |
181 | goto fault; | |
182 | *newvalue = value; | |
183 | *regptr = ®s->regs[insn.i_format.rt]; | |
184 | break; | |
185 | ||
186 | case lw_op: | |
187 | if (!access_ok(VERIFY_READ, addr, 4)) | |
188 | goto sigbus; | |
189 | ||
190 | __asm__ __volatile__ ( | |
191 | #ifdef __BIG_ENDIAN | |
192 | "1:\tlwl\t%0, (%2)\n" | |
193 | "2:\tlwr\t%0, 3(%2)\n\t" | |
194 | #endif | |
195 | #ifdef __LITTLE_ENDIAN | |
196 | "1:\tlwl\t%0, 3(%2)\n" | |
197 | "2:\tlwr\t%0, (%2)\n\t" | |
198 | #endif | |
199 | "li\t%1, 0\n" | |
200 | "3:\t.section\t.fixup,\"ax\"\n\t" | |
201 | "4:\tli\t%1, %3\n\t" | |
202 | "j\t3b\n\t" | |
203 | ".previous\n\t" | |
204 | ".section\t__ex_table,\"a\"\n\t" | |
205 | STR(PTR)"\t1b, 4b\n\t" | |
206 | STR(PTR)"\t2b, 4b\n\t" | |
207 | ".previous" | |
208 | : "=&r" (value), "=r" (res) | |
209 | : "r" (addr), "i" (-EFAULT)); | |
210 | if (res) | |
211 | goto fault; | |
212 | *newvalue = value; | |
213 | *regptr = ®s->regs[insn.i_format.rt]; | |
214 | break; | |
215 | ||
216 | case lhu_op: | |
217 | if (!access_ok(VERIFY_READ, addr, 2)) | |
218 | goto sigbus; | |
219 | ||
220 | __asm__ __volatile__ ( | |
221 | ".set\tnoat\n" | |
222 | #ifdef __BIG_ENDIAN | |
223 | "1:\tlbu\t%0, 0(%2)\n" | |
224 | "2:\tlbu\t$1, 1(%2)\n\t" | |
225 | #endif | |
226 | #ifdef __LITTLE_ENDIAN | |
227 | "1:\tlbu\t%0, 1(%2)\n" | |
228 | "2:\tlbu\t$1, 0(%2)\n\t" | |
229 | #endif | |
230 | "sll\t%0, 0x8\n\t" | |
231 | "or\t%0, $1\n\t" | |
232 | "li\t%1, 0\n" | |
233 | "3:\t.set\tat\n\t" | |
234 | ".section\t.fixup,\"ax\"\n\t" | |
235 | "4:\tli\t%1, %3\n\t" | |
236 | "j\t3b\n\t" | |
237 | ".previous\n\t" | |
238 | ".section\t__ex_table,\"a\"\n\t" | |
239 | STR(PTR)"\t1b, 4b\n\t" | |
240 | STR(PTR)"\t2b, 4b\n\t" | |
241 | ".previous" | |
242 | : "=&r" (value), "=r" (res) | |
243 | : "r" (addr), "i" (-EFAULT)); | |
244 | if (res) | |
245 | goto fault; | |
246 | *newvalue = value; | |
247 | *regptr = ®s->regs[insn.i_format.rt]; | |
248 | break; | |
249 | ||
250 | case lwu_op: | |
875d43e7 | 251 | #ifdef CONFIG_64BIT |
1da177e4 LT |
252 | /* |
253 | * A 32-bit kernel might be running on a 64-bit processor. But | |
254 | * if we're on a 32-bit processor and an i-cache incoherency | |
255 | * or race makes us see a 64-bit instruction here the sdl/sdr | |
256 | * would blow up, so for now we don't handle unaligned 64-bit | |
257 | * instructions on 32-bit kernels. | |
258 | */ | |
259 | if (!access_ok(VERIFY_READ, addr, 4)) | |
260 | goto sigbus; | |
261 | ||
262 | __asm__ __volatile__ ( | |
263 | #ifdef __BIG_ENDIAN | |
264 | "1:\tlwl\t%0, (%2)\n" | |
265 | "2:\tlwr\t%0, 3(%2)\n\t" | |
266 | #endif | |
267 | #ifdef __LITTLE_ENDIAN | |
268 | "1:\tlwl\t%0, 3(%2)\n" | |
269 | "2:\tlwr\t%0, (%2)\n\t" | |
270 | #endif | |
271 | "dsll\t%0, %0, 32\n\t" | |
272 | "dsrl\t%0, %0, 32\n\t" | |
273 | "li\t%1, 0\n" | |
274 | "3:\t.section\t.fixup,\"ax\"\n\t" | |
275 | "4:\tli\t%1, %3\n\t" | |
276 | "j\t3b\n\t" | |
277 | ".previous\n\t" | |
278 | ".section\t__ex_table,\"a\"\n\t" | |
279 | STR(PTR)"\t1b, 4b\n\t" | |
280 | STR(PTR)"\t2b, 4b\n\t" | |
281 | ".previous" | |
282 | : "=&r" (value), "=r" (res) | |
283 | : "r" (addr), "i" (-EFAULT)); | |
284 | if (res) | |
285 | goto fault; | |
286 | *newvalue = value; | |
287 | *regptr = ®s->regs[insn.i_format.rt]; | |
288 | break; | |
875d43e7 | 289 | #endif /* CONFIG_64BIT */ |
1da177e4 LT |
290 | |
291 | /* Cannot handle 64-bit instructions in 32-bit kernel */ | |
292 | goto sigill; | |
293 | ||
294 | case ld_op: | |
875d43e7 | 295 | #ifdef CONFIG_64BIT |
1da177e4 LT |
296 | /* |
297 | * A 32-bit kernel might be running on a 64-bit processor. But | |
298 | * if we're on a 32-bit processor and an i-cache incoherency | |
299 | * or race makes us see a 64-bit instruction here the sdl/sdr | |
300 | * would blow up, so for now we don't handle unaligned 64-bit | |
301 | * instructions on 32-bit kernels. | |
302 | */ | |
303 | if (!access_ok(VERIFY_READ, addr, 8)) | |
304 | goto sigbus; | |
305 | ||
306 | __asm__ __volatile__ ( | |
307 | #ifdef __BIG_ENDIAN | |
308 | "1:\tldl\t%0, (%2)\n" | |
309 | "2:\tldr\t%0, 7(%2)\n\t" | |
310 | #endif | |
311 | #ifdef __LITTLE_ENDIAN | |
312 | "1:\tldl\t%0, 7(%2)\n" | |
313 | "2:\tldr\t%0, (%2)\n\t" | |
314 | #endif | |
315 | "li\t%1, 0\n" | |
316 | "3:\t.section\t.fixup,\"ax\"\n\t" | |
317 | "4:\tli\t%1, %3\n\t" | |
318 | "j\t3b\n\t" | |
319 | ".previous\n\t" | |
320 | ".section\t__ex_table,\"a\"\n\t" | |
321 | STR(PTR)"\t1b, 4b\n\t" | |
322 | STR(PTR)"\t2b, 4b\n\t" | |
323 | ".previous" | |
324 | : "=&r" (value), "=r" (res) | |
325 | : "r" (addr), "i" (-EFAULT)); | |
326 | if (res) | |
327 | goto fault; | |
328 | *newvalue = value; | |
329 | *regptr = ®s->regs[insn.i_format.rt]; | |
330 | break; | |
875d43e7 | 331 | #endif /* CONFIG_64BIT */ |
1da177e4 LT |
332 | |
333 | /* Cannot handle 64-bit instructions in 32-bit kernel */ | |
334 | goto sigill; | |
335 | ||
336 | case sh_op: | |
337 | if (!access_ok(VERIFY_WRITE, addr, 2)) | |
338 | goto sigbus; | |
339 | ||
340 | value = regs->regs[insn.i_format.rt]; | |
341 | __asm__ __volatile__ ( | |
342 | #ifdef __BIG_ENDIAN | |
343 | ".set\tnoat\n" | |
344 | "1:\tsb\t%1, 1(%2)\n\t" | |
345 | "srl\t$1, %1, 0x8\n" | |
346 | "2:\tsb\t$1, 0(%2)\n\t" | |
347 | ".set\tat\n\t" | |
348 | #endif | |
349 | #ifdef __LITTLE_ENDIAN | |
350 | ".set\tnoat\n" | |
351 | "1:\tsb\t%1, 0(%2)\n\t" | |
352 | "srl\t$1,%1, 0x8\n" | |
353 | "2:\tsb\t$1, 1(%2)\n\t" | |
354 | ".set\tat\n\t" | |
355 | #endif | |
356 | "li\t%0, 0\n" | |
357 | "3:\n\t" | |
358 | ".section\t.fixup,\"ax\"\n\t" | |
359 | "4:\tli\t%0, %3\n\t" | |
360 | "j\t3b\n\t" | |
361 | ".previous\n\t" | |
362 | ".section\t__ex_table,\"a\"\n\t" | |
363 | STR(PTR)"\t1b, 4b\n\t" | |
364 | STR(PTR)"\t2b, 4b\n\t" | |
365 | ".previous" | |
366 | : "=r" (res) | |
367 | : "r" (value), "r" (addr), "i" (-EFAULT)); | |
368 | if (res) | |
369 | goto fault; | |
370 | break; | |
371 | ||
372 | case sw_op: | |
373 | if (!access_ok(VERIFY_WRITE, addr, 4)) | |
374 | goto sigbus; | |
375 | ||
376 | value = regs->regs[insn.i_format.rt]; | |
377 | __asm__ __volatile__ ( | |
378 | #ifdef __BIG_ENDIAN | |
379 | "1:\tswl\t%1,(%2)\n" | |
380 | "2:\tswr\t%1, 3(%2)\n\t" | |
381 | #endif | |
382 | #ifdef __LITTLE_ENDIAN | |
383 | "1:\tswl\t%1, 3(%2)\n" | |
384 | "2:\tswr\t%1, (%2)\n\t" | |
385 | #endif | |
386 | "li\t%0, 0\n" | |
387 | "3:\n\t" | |
388 | ".section\t.fixup,\"ax\"\n\t" | |
389 | "4:\tli\t%0, %3\n\t" | |
390 | "j\t3b\n\t" | |
391 | ".previous\n\t" | |
392 | ".section\t__ex_table,\"a\"\n\t" | |
393 | STR(PTR)"\t1b, 4b\n\t" | |
394 | STR(PTR)"\t2b, 4b\n\t" | |
395 | ".previous" | |
396 | : "=r" (res) | |
397 | : "r" (value), "r" (addr), "i" (-EFAULT)); | |
398 | if (res) | |
399 | goto fault; | |
400 | break; | |
401 | ||
402 | case sd_op: | |
875d43e7 | 403 | #ifdef CONFIG_64BIT |
1da177e4 LT |
404 | /* |
405 | * A 32-bit kernel might be running on a 64-bit processor. But | |
406 | * if we're on a 32-bit processor and an i-cache incoherency | |
407 | * or race makes us see a 64-bit instruction here the sdl/sdr | |
408 | * would blow up, so for now we don't handle unaligned 64-bit | |
409 | * instructions on 32-bit kernels. | |
410 | */ | |
411 | if (!access_ok(VERIFY_WRITE, addr, 8)) | |
412 | goto sigbus; | |
413 | ||
414 | value = regs->regs[insn.i_format.rt]; | |
415 | __asm__ __volatile__ ( | |
416 | #ifdef __BIG_ENDIAN | |
417 | "1:\tsdl\t%1,(%2)\n" | |
418 | "2:\tsdr\t%1, 7(%2)\n\t" | |
419 | #endif | |
420 | #ifdef __LITTLE_ENDIAN | |
421 | "1:\tsdl\t%1, 7(%2)\n" | |
422 | "2:\tsdr\t%1, (%2)\n\t" | |
423 | #endif | |
424 | "li\t%0, 0\n" | |
425 | "3:\n\t" | |
426 | ".section\t.fixup,\"ax\"\n\t" | |
427 | "4:\tli\t%0, %3\n\t" | |
428 | "j\t3b\n\t" | |
429 | ".previous\n\t" | |
430 | ".section\t__ex_table,\"a\"\n\t" | |
431 | STR(PTR)"\t1b, 4b\n\t" | |
432 | STR(PTR)"\t2b, 4b\n\t" | |
433 | ".previous" | |
434 | : "=r" (res) | |
435 | : "r" (value), "r" (addr), "i" (-EFAULT)); | |
436 | if (res) | |
437 | goto fault; | |
438 | break; | |
875d43e7 | 439 | #endif /* CONFIG_64BIT */ |
1da177e4 LT |
440 | |
441 | /* Cannot handle 64-bit instructions in 32-bit kernel */ | |
442 | goto sigill; | |
443 | ||
444 | case lwc1_op: | |
445 | case ldc1_op: | |
446 | case swc1_op: | |
447 | case sdc1_op: | |
448 | /* | |
449 | * I herewith declare: this does not happen. So send SIGBUS. | |
450 | */ | |
451 | goto sigbus; | |
452 | ||
453 | case lwc2_op: | |
454 | case ldc2_op: | |
455 | case swc2_op: | |
456 | case sdc2_op: | |
457 | /* | |
458 | * These are the coprocessor 2 load/stores. The current | |
459 | * implementations don't use cp2 and cp2 should always be | |
460 | * disabled in c0_status. So send SIGILL. | |
461 | * (No longer true: The Sony Praystation uses cp2 for | |
462 | * 3D matrix operations. Dunno if that thingy has a MMU ...) | |
463 | */ | |
464 | default: | |
465 | /* | |
466 | * Pheeee... We encountered an yet unknown instruction or | |
467 | * cache coherence problem. Die sucker, die ... | |
468 | */ | |
469 | goto sigill; | |
470 | } | |
471 | ||
6312e0ee | 472 | #ifdef CONFIG_DEBUG_FS |
1da177e4 LT |
473 | unaligned_instructions++; |
474 | #endif | |
475 | ||
476 | return 0; | |
477 | ||
478 | fault: | |
479 | /* Did we have an exception handler installed? */ | |
480 | if (fixup_exception(regs)) | |
481 | return 1; | |
482 | ||
483 | die_if_kernel ("Unhandled kernel unaligned access", regs); | |
484 | send_sig(SIGSEGV, current, 1); | |
485 | ||
486 | return 0; | |
487 | ||
488 | sigbus: | |
489 | die_if_kernel("Unhandled kernel unaligned access", regs); | |
490 | send_sig(SIGBUS, current, 1); | |
491 | ||
492 | return 0; | |
493 | ||
494 | sigill: | |
495 | die_if_kernel("Unhandled kernel unaligned access or invalid instruction", regs); | |
496 | send_sig(SIGILL, current, 1); | |
497 | ||
498 | return 0; | |
499 | } | |
500 | ||
501 | asmlinkage void do_ade(struct pt_regs *regs) | |
502 | { | |
503 | unsigned long *regptr, newval; | |
504 | extern int do_dsemulret(struct pt_regs *); | |
fe00f943 | 505 | unsigned int __user *pc; |
1da177e4 | 506 | mm_segment_t seg; |
1da177e4 LT |
507 | |
508 | /* | |
509 | * Address errors may be deliberately induced by the FPU emulator to | |
510 | * retake control of the CPU after executing the instruction in the | |
511 | * delay slot of an emulated branch. | |
512 | */ | |
513 | /* Terminate if exception was recognized as a delay slot return */ | |
514 | if (do_dsemulret(regs)) | |
515 | return; | |
516 | ||
517 | /* Otherwise handle as normal */ | |
518 | ||
519 | /* | |
520 | * Did we catch a fault trying to load an instruction? | |
521 | * Or are we running in MIPS16 mode? | |
522 | */ | |
523 | if ((regs->cp0_badvaddr == regs->cp0_epc) || (regs->cp0_epc & 0x1)) | |
524 | goto sigbus; | |
525 | ||
fe00f943 | 526 | pc = (unsigned int __user *) exception_epc(regs); |
b772e6d2 | 527 | if (user_mode(regs) && (current->thread.mflags & MF_FIXADE) == 0) |
1da177e4 | 528 | goto sigbus; |
6312e0ee AN |
529 | if (unaligned_action == UNALIGNED_ACTION_SIGNAL) |
530 | goto sigbus; | |
531 | else if (unaligned_action == UNALIGNED_ACTION_SHOW) | |
532 | show_registers(regs); | |
1da177e4 LT |
533 | |
534 | /* | |
535 | * Do branch emulation only if we didn't forward the exception. | |
536 | * This is all so but ugly ... | |
537 | */ | |
538 | seg = get_fs(); | |
539 | if (!user_mode(regs)) | |
540 | set_fs(KERNEL_DS); | |
fe00f943 | 541 | if (!emulate_load_store_insn(regs, (void __user *)regs->cp0_badvaddr, pc, |
1da177e4 LT |
542 | ®ptr, &newval)) { |
543 | compute_return_epc(regs); | |
544 | /* | |
545 | * Now that branch is evaluated, update the dest | |
546 | * register if necessary | |
547 | */ | |
548 | if (regptr) | |
549 | *regptr = newval; | |
550 | } | |
551 | set_fs(seg); | |
552 | ||
553 | return; | |
554 | ||
555 | sigbus: | |
556 | die_if_kernel("Kernel unaligned instruction access", regs); | |
557 | force_sig(SIGBUS, current); | |
558 | ||
559 | /* | |
560 | * XXX On return from the signal handler we should advance the epc | |
561 | */ | |
562 | } | |
6312e0ee AN |
563 | |
564 | #ifdef CONFIG_DEBUG_FS | |
565 | extern struct dentry *mips_debugfs_dir; | |
566 | static int __init debugfs_unaligned(void) | |
567 | { | |
568 | struct dentry *d; | |
569 | ||
570 | if (!mips_debugfs_dir) | |
571 | return -ENODEV; | |
572 | d = debugfs_create_u32("unaligned_instructions", S_IRUGO, | |
573 | mips_debugfs_dir, &unaligned_instructions); | |
574 | if (IS_ERR(d)) | |
575 | return PTR_ERR(d); | |
576 | d = debugfs_create_u32("unaligned_action", S_IRUGO | S_IWUSR, | |
577 | mips_debugfs_dir, &unaligned_action); | |
578 | if (IS_ERR(d)) | |
579 | return PTR_ERR(d); | |
580 | return 0; | |
581 | } | |
582 | __initcall(debugfs_unaligned); | |
583 | #endif |