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e685c689 | 1 | /* |
d116e812 DCZ |
2 | * This file is subject to the terms and conditions of the GNU General Public |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * KVM/MIPS: Instruction/Exception emulation | |
7 | * | |
8 | * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. | |
9 | * Authors: Sanjay Lal <sanjayl@kymasys.com> | |
10 | */ | |
e685c689 SL |
11 | |
12 | #include <linux/errno.h> | |
13 | #include <linux/err.h> | |
e30492bb | 14 | #include <linux/ktime.h> |
e685c689 SL |
15 | #include <linux/kvm_host.h> |
16 | #include <linux/module.h> | |
17 | #include <linux/vmalloc.h> | |
18 | #include <linux/fs.h> | |
19 | #include <linux/bootmem.h> | |
20 | #include <linux/random.h> | |
21 | #include <asm/page.h> | |
22 | #include <asm/cacheflush.h> | |
f4956f62 | 23 | #include <asm/cacheops.h> |
e685c689 SL |
24 | #include <asm/cpu-info.h> |
25 | #include <asm/mmu_context.h> | |
26 | #include <asm/tlbflush.h> | |
27 | #include <asm/inst.h> | |
28 | ||
29 | #undef CONFIG_MIPS_MT | |
30 | #include <asm/r4kcache.h> | |
31 | #define CONFIG_MIPS_MT | |
32 | ||
d7d5b05f DCZ |
33 | #include "interrupt.h" |
34 | #include "commpage.h" | |
e685c689 SL |
35 | |
36 | #include "trace.h" | |
37 | ||
38 | /* | |
39 | * Compute the return address and do emulate branch simulation, if required. | |
40 | * This function should be called only in branch delay slot active. | |
41 | */ | |
42 | unsigned long kvm_compute_return_epc(struct kvm_vcpu *vcpu, | |
43 | unsigned long instpc) | |
44 | { | |
45 | unsigned int dspcontrol; | |
46 | union mips_instruction insn; | |
47 | struct kvm_vcpu_arch *arch = &vcpu->arch; | |
48 | long epc = instpc; | |
49 | long nextpc = KVM_INVALID_INST; | |
50 | ||
51 | if (epc & 3) | |
52 | goto unaligned; | |
53 | ||
d116e812 | 54 | /* Read the instruction */ |
8cffd197 | 55 | insn.word = kvm_get_inst((u32 *) epc, vcpu); |
e685c689 SL |
56 | |
57 | if (insn.word == KVM_INVALID_INST) | |
58 | return KVM_INVALID_INST; | |
59 | ||
60 | switch (insn.i_format.opcode) { | |
d116e812 | 61 | /* jr and jalr are in r_format format. */ |
e685c689 SL |
62 | case spec_op: |
63 | switch (insn.r_format.func) { | |
64 | case jalr_op: | |
65 | arch->gprs[insn.r_format.rd] = epc + 8; | |
66 | /* Fall through */ | |
67 | case jr_op: | |
68 | nextpc = arch->gprs[insn.r_format.rs]; | |
69 | break; | |
70 | } | |
71 | break; | |
72 | ||
73 | /* | |
74 | * This group contains: | |
75 | * bltz_op, bgez_op, bltzl_op, bgezl_op, | |
76 | * bltzal_op, bgezal_op, bltzall_op, bgezall_op. | |
77 | */ | |
78 | case bcond_op: | |
79 | switch (insn.i_format.rt) { | |
80 | case bltz_op: | |
81 | case bltzl_op: | |
82 | if ((long)arch->gprs[insn.i_format.rs] < 0) | |
83 | epc = epc + 4 + (insn.i_format.simmediate << 2); | |
84 | else | |
85 | epc += 8; | |
86 | nextpc = epc; | |
87 | break; | |
88 | ||
89 | case bgez_op: | |
90 | case bgezl_op: | |
91 | if ((long)arch->gprs[insn.i_format.rs] >= 0) | |
92 | epc = epc + 4 + (insn.i_format.simmediate << 2); | |
93 | else | |
94 | epc += 8; | |
95 | nextpc = epc; | |
96 | break; | |
97 | ||
98 | case bltzal_op: | |
99 | case bltzall_op: | |
100 | arch->gprs[31] = epc + 8; | |
101 | if ((long)arch->gprs[insn.i_format.rs] < 0) | |
102 | epc = epc + 4 + (insn.i_format.simmediate << 2); | |
103 | else | |
104 | epc += 8; | |
105 | nextpc = epc; | |
106 | break; | |
107 | ||
108 | case bgezal_op: | |
109 | case bgezall_op: | |
110 | arch->gprs[31] = epc + 8; | |
111 | if ((long)arch->gprs[insn.i_format.rs] >= 0) | |
112 | epc = epc + 4 + (insn.i_format.simmediate << 2); | |
113 | else | |
114 | epc += 8; | |
115 | nextpc = epc; | |
116 | break; | |
117 | case bposge32_op: | |
118 | if (!cpu_has_dsp) | |
119 | goto sigill; | |
120 | ||
121 | dspcontrol = rddsp(0x01); | |
122 | ||
d116e812 | 123 | if (dspcontrol >= 32) |
e685c689 | 124 | epc = epc + 4 + (insn.i_format.simmediate << 2); |
d116e812 | 125 | else |
e685c689 SL |
126 | epc += 8; |
127 | nextpc = epc; | |
128 | break; | |
129 | } | |
130 | break; | |
131 | ||
d116e812 | 132 | /* These are unconditional and in j_format. */ |
e685c689 SL |
133 | case jal_op: |
134 | arch->gprs[31] = instpc + 8; | |
135 | case j_op: | |
136 | epc += 4; | |
137 | epc >>= 28; | |
138 | epc <<= 28; | |
139 | epc |= (insn.j_format.target << 2); | |
140 | nextpc = epc; | |
141 | break; | |
142 | ||
d116e812 | 143 | /* These are conditional and in i_format. */ |
e685c689 SL |
144 | case beq_op: |
145 | case beql_op: | |
146 | if (arch->gprs[insn.i_format.rs] == | |
147 | arch->gprs[insn.i_format.rt]) | |
148 | epc = epc + 4 + (insn.i_format.simmediate << 2); | |
149 | else | |
150 | epc += 8; | |
151 | nextpc = epc; | |
152 | break; | |
153 | ||
154 | case bne_op: | |
155 | case bnel_op: | |
156 | if (arch->gprs[insn.i_format.rs] != | |
157 | arch->gprs[insn.i_format.rt]) | |
158 | epc = epc + 4 + (insn.i_format.simmediate << 2); | |
159 | else | |
160 | epc += 8; | |
161 | nextpc = epc; | |
162 | break; | |
163 | ||
2e0badfa JH |
164 | case blez_op: /* POP06 */ |
165 | #ifndef CONFIG_CPU_MIPSR6 | |
166 | case blezl_op: /* removed in R6 */ | |
167 | #endif | |
168 | if (insn.i_format.rt != 0) | |
169 | goto compact_branch; | |
e685c689 SL |
170 | if ((long)arch->gprs[insn.i_format.rs] <= 0) |
171 | epc = epc + 4 + (insn.i_format.simmediate << 2); | |
172 | else | |
173 | epc += 8; | |
174 | nextpc = epc; | |
175 | break; | |
176 | ||
2e0badfa JH |
177 | case bgtz_op: /* POP07 */ |
178 | #ifndef CONFIG_CPU_MIPSR6 | |
179 | case bgtzl_op: /* removed in R6 */ | |
180 | #endif | |
181 | if (insn.i_format.rt != 0) | |
182 | goto compact_branch; | |
e685c689 SL |
183 | if ((long)arch->gprs[insn.i_format.rs] > 0) |
184 | epc = epc + 4 + (insn.i_format.simmediate << 2); | |
185 | else | |
186 | epc += 8; | |
187 | nextpc = epc; | |
188 | break; | |
189 | ||
d116e812 | 190 | /* And now the FPA/cp1 branch instructions. */ |
e685c689 | 191 | case cop1_op: |
6ad78a5c | 192 | kvm_err("%s: unsupported cop1_op\n", __func__); |
e685c689 | 193 | break; |
2e0badfa JH |
194 | |
195 | #ifdef CONFIG_CPU_MIPSR6 | |
196 | /* R6 added the following compact branches with forbidden slots */ | |
197 | case blezl_op: /* POP26 */ | |
198 | case bgtzl_op: /* POP27 */ | |
199 | /* only rt == 0 isn't compact branch */ | |
200 | if (insn.i_format.rt != 0) | |
201 | goto compact_branch; | |
202 | break; | |
203 | case pop10_op: | |
204 | case pop30_op: | |
205 | /* only rs == rt == 0 is reserved, rest are compact branches */ | |
206 | if (insn.i_format.rs != 0 || insn.i_format.rt != 0) | |
207 | goto compact_branch; | |
208 | break; | |
209 | case pop66_op: | |
210 | case pop76_op: | |
211 | /* only rs == 0 isn't compact branch */ | |
212 | if (insn.i_format.rs != 0) | |
213 | goto compact_branch; | |
214 | break; | |
215 | compact_branch: | |
216 | /* | |
217 | * If we've hit an exception on the forbidden slot, then | |
218 | * the branch must not have been taken. | |
219 | */ | |
220 | epc += 8; | |
221 | nextpc = epc; | |
222 | break; | |
223 | #else | |
224 | compact_branch: | |
225 | /* Compact branches not supported before R6 */ | |
226 | break; | |
227 | #endif | |
e685c689 SL |
228 | } |
229 | ||
230 | return nextpc; | |
231 | ||
232 | unaligned: | |
6ad78a5c | 233 | kvm_err("%s: unaligned epc\n", __func__); |
e685c689 SL |
234 | return nextpc; |
235 | ||
236 | sigill: | |
6ad78a5c | 237 | kvm_err("%s: DSP branch but not DSP ASE\n", __func__); |
e685c689 SL |
238 | return nextpc; |
239 | } | |
240 | ||
bdb7ed86 | 241 | enum emulation_result update_pc(struct kvm_vcpu *vcpu, u32 cause) |
e685c689 SL |
242 | { |
243 | unsigned long branch_pc; | |
244 | enum emulation_result er = EMULATE_DONE; | |
245 | ||
246 | if (cause & CAUSEF_BD) { | |
247 | branch_pc = kvm_compute_return_epc(vcpu, vcpu->arch.pc); | |
248 | if (branch_pc == KVM_INVALID_INST) { | |
249 | er = EMULATE_FAIL; | |
250 | } else { | |
251 | vcpu->arch.pc = branch_pc; | |
d116e812 DCZ |
252 | kvm_debug("BD update_pc(): New PC: %#lx\n", |
253 | vcpu->arch.pc); | |
e685c689 SL |
254 | } |
255 | } else | |
256 | vcpu->arch.pc += 4; | |
257 | ||
258 | kvm_debug("update_pc(): New PC: %#lx\n", vcpu->arch.pc); | |
259 | ||
260 | return er; | |
261 | } | |
262 | ||
e30492bb JH |
263 | /** |
264 | * kvm_mips_count_disabled() - Find whether the CP0_Count timer is disabled. | |
265 | * @vcpu: Virtual CPU. | |
e685c689 | 266 | * |
f8239342 JH |
267 | * Returns: 1 if the CP0_Count timer is disabled by either the guest |
268 | * CP0_Cause.DC bit or the count_ctl.DC bit. | |
e30492bb | 269 | * 0 otherwise (in which case CP0_Count timer is running). |
e685c689 | 270 | */ |
e30492bb | 271 | static inline int kvm_mips_count_disabled(struct kvm_vcpu *vcpu) |
e685c689 SL |
272 | { |
273 | struct mips_coproc *cop0 = vcpu->arch.cop0; | |
d116e812 | 274 | |
f8239342 JH |
275 | return (vcpu->arch.count_ctl & KVM_REG_MIPS_COUNT_CTL_DC) || |
276 | (kvm_read_c0_guest_cause(cop0) & CAUSEF_DC); | |
e30492bb | 277 | } |
e685c689 | 278 | |
e30492bb JH |
279 | /** |
280 | * kvm_mips_ktime_to_count() - Scale ktime_t to a 32-bit count. | |
281 | * | |
282 | * Caches the dynamic nanosecond bias in vcpu->arch.count_dyn_bias. | |
283 | * | |
284 | * Assumes !kvm_mips_count_disabled(@vcpu) (guest CP0_Count timer is running). | |
285 | */ | |
bdb7ed86 | 286 | static u32 kvm_mips_ktime_to_count(struct kvm_vcpu *vcpu, ktime_t now) |
e30492bb JH |
287 | { |
288 | s64 now_ns, periods; | |
289 | u64 delta; | |
290 | ||
291 | now_ns = ktime_to_ns(now); | |
292 | delta = now_ns + vcpu->arch.count_dyn_bias; | |
293 | ||
294 | if (delta >= vcpu->arch.count_period) { | |
295 | /* If delta is out of safe range the bias needs adjusting */ | |
296 | periods = div64_s64(now_ns, vcpu->arch.count_period); | |
297 | vcpu->arch.count_dyn_bias = -periods * vcpu->arch.count_period; | |
298 | /* Recalculate delta with new bias */ | |
299 | delta = now_ns + vcpu->arch.count_dyn_bias; | |
e685c689 SL |
300 | } |
301 | ||
e30492bb JH |
302 | /* |
303 | * We've ensured that: | |
304 | * delta < count_period | |
305 | * | |
306 | * Therefore the intermediate delta*count_hz will never overflow since | |
307 | * at the boundary condition: | |
308 | * delta = count_period | |
309 | * delta = NSEC_PER_SEC * 2^32 / count_hz | |
310 | * delta * count_hz = NSEC_PER_SEC * 2^32 | |
311 | */ | |
312 | return div_u64(delta * vcpu->arch.count_hz, NSEC_PER_SEC); | |
313 | } | |
314 | ||
f8239342 JH |
315 | /** |
316 | * kvm_mips_count_time() - Get effective current time. | |
317 | * @vcpu: Virtual CPU. | |
318 | * | |
319 | * Get effective monotonic ktime. This is usually a straightforward ktime_get(), | |
320 | * except when the master disable bit is set in count_ctl, in which case it is | |
321 | * count_resume, i.e. the time that the count was disabled. | |
322 | * | |
323 | * Returns: Effective monotonic ktime for CP0_Count. | |
324 | */ | |
325 | static inline ktime_t kvm_mips_count_time(struct kvm_vcpu *vcpu) | |
326 | { | |
327 | if (unlikely(vcpu->arch.count_ctl & KVM_REG_MIPS_COUNT_CTL_DC)) | |
328 | return vcpu->arch.count_resume; | |
329 | ||
330 | return ktime_get(); | |
331 | } | |
332 | ||
e30492bb JH |
333 | /** |
334 | * kvm_mips_read_count_running() - Read the current count value as if running. | |
335 | * @vcpu: Virtual CPU. | |
336 | * @now: Kernel time to read CP0_Count at. | |
337 | * | |
338 | * Returns the current guest CP0_Count register at time @now and handles if the | |
339 | * timer interrupt is pending and hasn't been handled yet. | |
340 | * | |
341 | * Returns: The current value of the guest CP0_Count register. | |
342 | */ | |
bdb7ed86 | 343 | static u32 kvm_mips_read_count_running(struct kvm_vcpu *vcpu, ktime_t now) |
e30492bb | 344 | { |
4355c44f JH |
345 | struct mips_coproc *cop0 = vcpu->arch.cop0; |
346 | ktime_t expires, threshold; | |
8cffd197 | 347 | u32 count, compare; |
e30492bb JH |
348 | int running; |
349 | ||
4355c44f JH |
350 | /* Calculate the biased and scaled guest CP0_Count */ |
351 | count = vcpu->arch.count_bias + kvm_mips_ktime_to_count(vcpu, now); | |
352 | compare = kvm_read_c0_guest_compare(cop0); | |
353 | ||
354 | /* | |
355 | * Find whether CP0_Count has reached the closest timer interrupt. If | |
356 | * not, we shouldn't inject it. | |
357 | */ | |
8cffd197 | 358 | if ((s32)(count - compare) < 0) |
4355c44f JH |
359 | return count; |
360 | ||
361 | /* | |
362 | * The CP0_Count we're going to return has already reached the closest | |
363 | * timer interrupt. Quickly check if it really is a new interrupt by | |
364 | * looking at whether the interval until the hrtimer expiry time is | |
365 | * less than 1/4 of the timer period. | |
366 | */ | |
e30492bb | 367 | expires = hrtimer_get_expires(&vcpu->arch.comparecount_timer); |
4355c44f JH |
368 | threshold = ktime_add_ns(now, vcpu->arch.count_period / 4); |
369 | if (ktime_before(expires, threshold)) { | |
e30492bb JH |
370 | /* |
371 | * Cancel it while we handle it so there's no chance of | |
372 | * interference with the timeout handler. | |
373 | */ | |
374 | running = hrtimer_cancel(&vcpu->arch.comparecount_timer); | |
375 | ||
376 | /* Nothing should be waiting on the timeout */ | |
377 | kvm_mips_callbacks->queue_timer_int(vcpu); | |
378 | ||
379 | /* | |
380 | * Restart the timer if it was running based on the expiry time | |
381 | * we read, so that we don't push it back 2 periods. | |
382 | */ | |
383 | if (running) { | |
384 | expires = ktime_add_ns(expires, | |
385 | vcpu->arch.count_period); | |
386 | hrtimer_start(&vcpu->arch.comparecount_timer, expires, | |
387 | HRTIMER_MODE_ABS); | |
388 | } | |
389 | } | |
390 | ||
4355c44f | 391 | return count; |
e30492bb JH |
392 | } |
393 | ||
394 | /** | |
395 | * kvm_mips_read_count() - Read the current count value. | |
396 | * @vcpu: Virtual CPU. | |
397 | * | |
398 | * Read the current guest CP0_Count value, taking into account whether the timer | |
399 | * is stopped. | |
400 | * | |
401 | * Returns: The current guest CP0_Count value. | |
402 | */ | |
bdb7ed86 | 403 | u32 kvm_mips_read_count(struct kvm_vcpu *vcpu) |
e30492bb JH |
404 | { |
405 | struct mips_coproc *cop0 = vcpu->arch.cop0; | |
406 | ||
407 | /* If count disabled just read static copy of count */ | |
408 | if (kvm_mips_count_disabled(vcpu)) | |
409 | return kvm_read_c0_guest_count(cop0); | |
410 | ||
411 | return kvm_mips_read_count_running(vcpu, ktime_get()); | |
412 | } | |
413 | ||
414 | /** | |
415 | * kvm_mips_freeze_hrtimer() - Safely stop the hrtimer. | |
416 | * @vcpu: Virtual CPU. | |
417 | * @count: Output pointer for CP0_Count value at point of freeze. | |
418 | * | |
419 | * Freeze the hrtimer safely and return both the ktime and the CP0_Count value | |
420 | * at the point it was frozen. It is guaranteed that any pending interrupts at | |
421 | * the point it was frozen are handled, and none after that point. | |
422 | * | |
423 | * This is useful where the time/CP0_Count is needed in the calculation of the | |
424 | * new parameters. | |
425 | * | |
426 | * Assumes !kvm_mips_count_disabled(@vcpu) (guest CP0_Count timer is running). | |
427 | * | |
428 | * Returns: The ktime at the point of freeze. | |
429 | */ | |
bdb7ed86 | 430 | static ktime_t kvm_mips_freeze_hrtimer(struct kvm_vcpu *vcpu, u32 *count) |
e30492bb JH |
431 | { |
432 | ktime_t now; | |
433 | ||
434 | /* stop hrtimer before finding time */ | |
435 | hrtimer_cancel(&vcpu->arch.comparecount_timer); | |
436 | now = ktime_get(); | |
437 | ||
438 | /* find count at this point and handle pending hrtimer */ | |
439 | *count = kvm_mips_read_count_running(vcpu, now); | |
440 | ||
441 | return now; | |
442 | } | |
443 | ||
e30492bb JH |
444 | /** |
445 | * kvm_mips_resume_hrtimer() - Resume hrtimer, updating expiry. | |
446 | * @vcpu: Virtual CPU. | |
447 | * @now: ktime at point of resume. | |
448 | * @count: CP0_Count at point of resume. | |
449 | * | |
450 | * Resumes the timer and updates the timer expiry based on @now and @count. | |
451 | * This can be used in conjunction with kvm_mips_freeze_timer() when timer | |
452 | * parameters need to be changed. | |
453 | * | |
454 | * It is guaranteed that a timer interrupt immediately after resume will be | |
455 | * handled, but not if CP_Compare is exactly at @count. That case is already | |
456 | * handled by kvm_mips_freeze_timer(). | |
457 | * | |
458 | * Assumes !kvm_mips_count_disabled(@vcpu) (guest CP0_Count timer is running). | |
459 | */ | |
460 | static void kvm_mips_resume_hrtimer(struct kvm_vcpu *vcpu, | |
bdb7ed86 | 461 | ktime_t now, u32 count) |
e30492bb JH |
462 | { |
463 | struct mips_coproc *cop0 = vcpu->arch.cop0; | |
8cffd197 | 464 | u32 compare; |
e30492bb JH |
465 | u64 delta; |
466 | ktime_t expire; | |
467 | ||
468 | /* Calculate timeout (wrap 0 to 2^32) */ | |
469 | compare = kvm_read_c0_guest_compare(cop0); | |
8cffd197 | 470 | delta = (u64)(u32)(compare - count - 1) + 1; |
e30492bb JH |
471 | delta = div_u64(delta * NSEC_PER_SEC, vcpu->arch.count_hz); |
472 | expire = ktime_add_ns(now, delta); | |
473 | ||
474 | /* Update hrtimer to use new timeout */ | |
475 | hrtimer_cancel(&vcpu->arch.comparecount_timer); | |
476 | hrtimer_start(&vcpu->arch.comparecount_timer, expire, HRTIMER_MODE_ABS); | |
477 | } | |
478 | ||
e30492bb JH |
479 | /** |
480 | * kvm_mips_write_count() - Modify the count and update timer. | |
481 | * @vcpu: Virtual CPU. | |
482 | * @count: Guest CP0_Count value to set. | |
483 | * | |
484 | * Sets the CP0_Count value and updates the timer accordingly. | |
485 | */ | |
bdb7ed86 | 486 | void kvm_mips_write_count(struct kvm_vcpu *vcpu, u32 count) |
e30492bb JH |
487 | { |
488 | struct mips_coproc *cop0 = vcpu->arch.cop0; | |
489 | ktime_t now; | |
490 | ||
491 | /* Calculate bias */ | |
f8239342 | 492 | now = kvm_mips_count_time(vcpu); |
e30492bb JH |
493 | vcpu->arch.count_bias = count - kvm_mips_ktime_to_count(vcpu, now); |
494 | ||
495 | if (kvm_mips_count_disabled(vcpu)) | |
496 | /* The timer's disabled, adjust the static count */ | |
497 | kvm_write_c0_guest_count(cop0, count); | |
498 | else | |
499 | /* Update timeout */ | |
500 | kvm_mips_resume_hrtimer(vcpu, now, count); | |
501 | } | |
502 | ||
503 | /** | |
504 | * kvm_mips_init_count() - Initialise timer. | |
505 | * @vcpu: Virtual CPU. | |
506 | * | |
507 | * Initialise the timer to a sensible frequency, namely 100MHz, zero it, and set | |
508 | * it going if it's enabled. | |
509 | */ | |
510 | void kvm_mips_init_count(struct kvm_vcpu *vcpu) | |
511 | { | |
512 | /* 100 MHz */ | |
513 | vcpu->arch.count_hz = 100*1000*1000; | |
514 | vcpu->arch.count_period = div_u64((u64)NSEC_PER_SEC << 32, | |
515 | vcpu->arch.count_hz); | |
516 | vcpu->arch.count_dyn_bias = 0; | |
517 | ||
518 | /* Starting at 0 */ | |
519 | kvm_mips_write_count(vcpu, 0); | |
520 | } | |
521 | ||
f74a8e22 JH |
522 | /** |
523 | * kvm_mips_set_count_hz() - Update the frequency of the timer. | |
524 | * @vcpu: Virtual CPU. | |
525 | * @count_hz: Frequency of CP0_Count timer in Hz. | |
526 | * | |
527 | * Change the frequency of the CP0_Count timer. This is done atomically so that | |
528 | * CP0_Count is continuous and no timer interrupt is lost. | |
529 | * | |
530 | * Returns: -EINVAL if @count_hz is out of range. | |
531 | * 0 on success. | |
532 | */ | |
533 | int kvm_mips_set_count_hz(struct kvm_vcpu *vcpu, s64 count_hz) | |
534 | { | |
535 | struct mips_coproc *cop0 = vcpu->arch.cop0; | |
536 | int dc; | |
537 | ktime_t now; | |
538 | u32 count; | |
539 | ||
540 | /* ensure the frequency is in a sensible range... */ | |
541 | if (count_hz <= 0 || count_hz > NSEC_PER_SEC) | |
542 | return -EINVAL; | |
543 | /* ... and has actually changed */ | |
544 | if (vcpu->arch.count_hz == count_hz) | |
545 | return 0; | |
546 | ||
547 | /* Safely freeze timer so we can keep it continuous */ | |
548 | dc = kvm_mips_count_disabled(vcpu); | |
549 | if (dc) { | |
550 | now = kvm_mips_count_time(vcpu); | |
551 | count = kvm_read_c0_guest_count(cop0); | |
552 | } else { | |
553 | now = kvm_mips_freeze_hrtimer(vcpu, &count); | |
554 | } | |
555 | ||
556 | /* Update the frequency */ | |
557 | vcpu->arch.count_hz = count_hz; | |
558 | vcpu->arch.count_period = div_u64((u64)NSEC_PER_SEC << 32, count_hz); | |
559 | vcpu->arch.count_dyn_bias = 0; | |
560 | ||
561 | /* Calculate adjusted bias so dynamic count is unchanged */ | |
562 | vcpu->arch.count_bias = count - kvm_mips_ktime_to_count(vcpu, now); | |
563 | ||
564 | /* Update and resume hrtimer */ | |
565 | if (!dc) | |
566 | kvm_mips_resume_hrtimer(vcpu, now, count); | |
567 | return 0; | |
568 | } | |
569 | ||
e30492bb JH |
570 | /** |
571 | * kvm_mips_write_compare() - Modify compare and update timer. | |
572 | * @vcpu: Virtual CPU. | |
573 | * @compare: New CP0_Compare value. | |
b45bacd2 | 574 | * @ack: Whether to acknowledge timer interrupt. |
e30492bb JH |
575 | * |
576 | * Update CP0_Compare to a new value and update the timeout. | |
b45bacd2 JH |
577 | * If @ack, atomically acknowledge any pending timer interrupt, otherwise ensure |
578 | * any pending timer interrupt is preserved. | |
e30492bb | 579 | */ |
bdb7ed86 | 580 | void kvm_mips_write_compare(struct kvm_vcpu *vcpu, u32 compare, bool ack) |
e30492bb JH |
581 | { |
582 | struct mips_coproc *cop0 = vcpu->arch.cop0; | |
b45bacd2 JH |
583 | int dc; |
584 | u32 old_compare = kvm_read_c0_guest_compare(cop0); | |
585 | ktime_t now; | |
8cffd197 | 586 | u32 count; |
e30492bb JH |
587 | |
588 | /* if unchanged, must just be an ack */ | |
b45bacd2 JH |
589 | if (old_compare == compare) { |
590 | if (!ack) | |
591 | return; | |
592 | kvm_mips_callbacks->dequeue_timer_int(vcpu); | |
593 | kvm_write_c0_guest_compare(cop0, compare); | |
e30492bb | 594 | return; |
b45bacd2 JH |
595 | } |
596 | ||
597 | /* freeze_hrtimer() takes care of timer interrupts <= count */ | |
598 | dc = kvm_mips_count_disabled(vcpu); | |
599 | if (!dc) | |
600 | now = kvm_mips_freeze_hrtimer(vcpu, &count); | |
601 | ||
602 | if (ack) | |
603 | kvm_mips_callbacks->dequeue_timer_int(vcpu); | |
e30492bb | 604 | |
e30492bb JH |
605 | kvm_write_c0_guest_compare(cop0, compare); |
606 | ||
b45bacd2 JH |
607 | /* resume_hrtimer() takes care of timer interrupts > count */ |
608 | if (!dc) | |
609 | kvm_mips_resume_hrtimer(vcpu, now, count); | |
e30492bb JH |
610 | } |
611 | ||
612 | /** | |
613 | * kvm_mips_count_disable() - Disable count. | |
614 | * @vcpu: Virtual CPU. | |
615 | * | |
616 | * Disable the CP0_Count timer. A timer interrupt on or before the final stop | |
617 | * time will be handled but not after. | |
618 | * | |
f8239342 JH |
619 | * Assumes CP0_Count was previously enabled but now Guest.CP0_Cause.DC or |
620 | * count_ctl.DC has been set (count disabled). | |
e30492bb JH |
621 | * |
622 | * Returns: The time that the timer was stopped. | |
623 | */ | |
624 | static ktime_t kvm_mips_count_disable(struct kvm_vcpu *vcpu) | |
625 | { | |
626 | struct mips_coproc *cop0 = vcpu->arch.cop0; | |
8cffd197 | 627 | u32 count; |
e30492bb JH |
628 | ktime_t now; |
629 | ||
630 | /* Stop hrtimer */ | |
631 | hrtimer_cancel(&vcpu->arch.comparecount_timer); | |
632 | ||
633 | /* Set the static count from the dynamic count, handling pending TI */ | |
634 | now = ktime_get(); | |
635 | count = kvm_mips_read_count_running(vcpu, now); | |
636 | kvm_write_c0_guest_count(cop0, count); | |
637 | ||
638 | return now; | |
639 | } | |
640 | ||
641 | /** | |
642 | * kvm_mips_count_disable_cause() - Disable count using CP0_Cause.DC. | |
643 | * @vcpu: Virtual CPU. | |
644 | * | |
645 | * Disable the CP0_Count timer and set CP0_Cause.DC. A timer interrupt on or | |
f8239342 JH |
646 | * before the final stop time will be handled if the timer isn't disabled by |
647 | * count_ctl.DC, but not after. | |
e30492bb JH |
648 | * |
649 | * Assumes CP0_Cause.DC is clear (count enabled). | |
650 | */ | |
651 | void kvm_mips_count_disable_cause(struct kvm_vcpu *vcpu) | |
652 | { | |
653 | struct mips_coproc *cop0 = vcpu->arch.cop0; | |
654 | ||
655 | kvm_set_c0_guest_cause(cop0, CAUSEF_DC); | |
f8239342 JH |
656 | if (!(vcpu->arch.count_ctl & KVM_REG_MIPS_COUNT_CTL_DC)) |
657 | kvm_mips_count_disable(vcpu); | |
e30492bb JH |
658 | } |
659 | ||
660 | /** | |
661 | * kvm_mips_count_enable_cause() - Enable count using CP0_Cause.DC. | |
662 | * @vcpu: Virtual CPU. | |
663 | * | |
664 | * Enable the CP0_Count timer and clear CP0_Cause.DC. A timer interrupt after | |
f8239342 JH |
665 | * the start time will be handled if the timer isn't disabled by count_ctl.DC, |
666 | * potentially before even returning, so the caller should be careful with | |
667 | * ordering of CP0_Cause modifications so as not to lose it. | |
e30492bb JH |
668 | * |
669 | * Assumes CP0_Cause.DC is set (count disabled). | |
670 | */ | |
671 | void kvm_mips_count_enable_cause(struct kvm_vcpu *vcpu) | |
672 | { | |
673 | struct mips_coproc *cop0 = vcpu->arch.cop0; | |
8cffd197 | 674 | u32 count; |
e30492bb JH |
675 | |
676 | kvm_clear_c0_guest_cause(cop0, CAUSEF_DC); | |
677 | ||
678 | /* | |
679 | * Set the dynamic count to match the static count. | |
f8239342 JH |
680 | * This starts the hrtimer if count_ctl.DC allows it. |
681 | * Otherwise it conveniently updates the biases. | |
e30492bb JH |
682 | */ |
683 | count = kvm_read_c0_guest_count(cop0); | |
684 | kvm_mips_write_count(vcpu, count); | |
685 | } | |
686 | ||
f8239342 JH |
687 | /** |
688 | * kvm_mips_set_count_ctl() - Update the count control KVM register. | |
689 | * @vcpu: Virtual CPU. | |
690 | * @count_ctl: Count control register new value. | |
691 | * | |
692 | * Set the count control KVM register. The timer is updated accordingly. | |
693 | * | |
694 | * Returns: -EINVAL if reserved bits are set. | |
695 | * 0 on success. | |
696 | */ | |
697 | int kvm_mips_set_count_ctl(struct kvm_vcpu *vcpu, s64 count_ctl) | |
698 | { | |
699 | struct mips_coproc *cop0 = vcpu->arch.cop0; | |
700 | s64 changed = count_ctl ^ vcpu->arch.count_ctl; | |
701 | s64 delta; | |
702 | ktime_t expire, now; | |
8cffd197 | 703 | u32 count, compare; |
f8239342 JH |
704 | |
705 | /* Only allow defined bits to be changed */ | |
706 | if (changed & ~(s64)(KVM_REG_MIPS_COUNT_CTL_DC)) | |
707 | return -EINVAL; | |
708 | ||
709 | /* Apply new value */ | |
710 | vcpu->arch.count_ctl = count_ctl; | |
711 | ||
712 | /* Master CP0_Count disable */ | |
713 | if (changed & KVM_REG_MIPS_COUNT_CTL_DC) { | |
714 | /* Is CP0_Cause.DC already disabling CP0_Count? */ | |
715 | if (kvm_read_c0_guest_cause(cop0) & CAUSEF_DC) { | |
716 | if (count_ctl & KVM_REG_MIPS_COUNT_CTL_DC) | |
717 | /* Just record the current time */ | |
718 | vcpu->arch.count_resume = ktime_get(); | |
719 | } else if (count_ctl & KVM_REG_MIPS_COUNT_CTL_DC) { | |
720 | /* disable timer and record current time */ | |
721 | vcpu->arch.count_resume = kvm_mips_count_disable(vcpu); | |
722 | } else { | |
723 | /* | |
724 | * Calculate timeout relative to static count at resume | |
725 | * time (wrap 0 to 2^32). | |
726 | */ | |
727 | count = kvm_read_c0_guest_count(cop0); | |
728 | compare = kvm_read_c0_guest_compare(cop0); | |
8cffd197 | 729 | delta = (u64)(u32)(compare - count - 1) + 1; |
f8239342 JH |
730 | delta = div_u64(delta * NSEC_PER_SEC, |
731 | vcpu->arch.count_hz); | |
732 | expire = ktime_add_ns(vcpu->arch.count_resume, delta); | |
733 | ||
734 | /* Handle pending interrupt */ | |
735 | now = ktime_get(); | |
736 | if (ktime_compare(now, expire) >= 0) | |
737 | /* Nothing should be waiting on the timeout */ | |
738 | kvm_mips_callbacks->queue_timer_int(vcpu); | |
739 | ||
740 | /* Resume hrtimer without changing bias */ | |
741 | count = kvm_mips_read_count_running(vcpu, now); | |
742 | kvm_mips_resume_hrtimer(vcpu, now, count); | |
743 | } | |
744 | } | |
745 | ||
746 | return 0; | |
747 | } | |
748 | ||
749 | /** | |
750 | * kvm_mips_set_count_resume() - Update the count resume KVM register. | |
751 | * @vcpu: Virtual CPU. | |
752 | * @count_resume: Count resume register new value. | |
753 | * | |
754 | * Set the count resume KVM register. | |
755 | * | |
756 | * Returns: -EINVAL if out of valid range (0..now). | |
757 | * 0 on success. | |
758 | */ | |
759 | int kvm_mips_set_count_resume(struct kvm_vcpu *vcpu, s64 count_resume) | |
760 | { | |
761 | /* | |
762 | * It doesn't make sense for the resume time to be in the future, as it | |
763 | * would be possible for the next interrupt to be more than a full | |
764 | * period in the future. | |
765 | */ | |
766 | if (count_resume < 0 || count_resume > ktime_to_ns(ktime_get())) | |
767 | return -EINVAL; | |
768 | ||
769 | vcpu->arch.count_resume = ns_to_ktime(count_resume); | |
770 | return 0; | |
771 | } | |
772 | ||
e30492bb JH |
773 | /** |
774 | * kvm_mips_count_timeout() - Push timer forward on timeout. | |
775 | * @vcpu: Virtual CPU. | |
776 | * | |
777 | * Handle an hrtimer event by push the hrtimer forward a period. | |
778 | * | |
779 | * Returns: The hrtimer_restart value to return to the hrtimer subsystem. | |
780 | */ | |
781 | enum hrtimer_restart kvm_mips_count_timeout(struct kvm_vcpu *vcpu) | |
782 | { | |
783 | /* Add the Count period to the current expiry time */ | |
784 | hrtimer_add_expires_ns(&vcpu->arch.comparecount_timer, | |
785 | vcpu->arch.count_period); | |
786 | return HRTIMER_RESTART; | |
e685c689 SL |
787 | } |
788 | ||
789 | enum emulation_result kvm_mips_emul_eret(struct kvm_vcpu *vcpu) | |
790 | { | |
791 | struct mips_coproc *cop0 = vcpu->arch.cop0; | |
792 | enum emulation_result er = EMULATE_DONE; | |
793 | ||
794 | if (kvm_read_c0_guest_status(cop0) & ST0_EXL) { | |
795 | kvm_debug("[%#lx] ERET to %#lx\n", vcpu->arch.pc, | |
796 | kvm_read_c0_guest_epc(cop0)); | |
797 | kvm_clear_c0_guest_status(cop0, ST0_EXL); | |
798 | vcpu->arch.pc = kvm_read_c0_guest_epc(cop0); | |
799 | ||
800 | } else if (kvm_read_c0_guest_status(cop0) & ST0_ERL) { | |
801 | kvm_clear_c0_guest_status(cop0, ST0_ERL); | |
802 | vcpu->arch.pc = kvm_read_c0_guest_errorepc(cop0); | |
803 | } else { | |
6ad78a5c DCZ |
804 | kvm_err("[%#lx] ERET when MIPS_SR_EXL|MIPS_SR_ERL == 0\n", |
805 | vcpu->arch.pc); | |
e685c689 SL |
806 | er = EMULATE_FAIL; |
807 | } | |
808 | ||
809 | return er; | |
810 | } | |
811 | ||
812 | enum emulation_result kvm_mips_emul_wait(struct kvm_vcpu *vcpu) | |
813 | { | |
e685c689 SL |
814 | kvm_debug("[%#lx] !!!WAIT!!! (%#lx)\n", vcpu->arch.pc, |
815 | vcpu->arch.pending_exceptions); | |
816 | ||
817 | ++vcpu->stat.wait_exits; | |
1e09e86a | 818 | trace_kvm_exit(vcpu, KVM_TRACE_EXIT_WAIT); |
e685c689 SL |
819 | if (!vcpu->arch.pending_exceptions) { |
820 | vcpu->arch.wait = 1; | |
821 | kvm_vcpu_block(vcpu); | |
822 | ||
d116e812 DCZ |
823 | /* |
824 | * We we are runnable, then definitely go off to user space to | |
825 | * check if any I/O interrupts are pending. | |
e685c689 SL |
826 | */ |
827 | if (kvm_check_request(KVM_REQ_UNHALT, vcpu)) { | |
828 | clear_bit(KVM_REQ_UNHALT, &vcpu->requests); | |
829 | vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; | |
830 | } | |
831 | } | |
832 | ||
d98403a5 | 833 | return EMULATE_DONE; |
e685c689 SL |
834 | } |
835 | ||
d116e812 DCZ |
836 | /* |
837 | * XXXKYMA: Linux doesn't seem to use TLBR, return EMULATE_FAIL for now so that | |
838 | * we can catch this, if things ever change | |
e685c689 SL |
839 | */ |
840 | enum emulation_result kvm_mips_emul_tlbr(struct kvm_vcpu *vcpu) | |
841 | { | |
842 | struct mips_coproc *cop0 = vcpu->arch.cop0; | |
8cffd197 | 843 | unsigned long pc = vcpu->arch.pc; |
e685c689 | 844 | |
8cffd197 | 845 | kvm_err("[%#lx] COP0_TLBR [%ld]\n", pc, kvm_read_c0_guest_index(cop0)); |
d98403a5 | 846 | return EMULATE_FAIL; |
e685c689 SL |
847 | } |
848 | ||
849 | /* Write Guest TLB Entry @ Index */ | |
850 | enum emulation_result kvm_mips_emul_tlbwi(struct kvm_vcpu *vcpu) | |
851 | { | |
852 | struct mips_coproc *cop0 = vcpu->arch.cop0; | |
853 | int index = kvm_read_c0_guest_index(cop0); | |
e685c689 | 854 | struct kvm_mips_tlb *tlb = NULL; |
8cffd197 | 855 | unsigned long pc = vcpu->arch.pc; |
e685c689 SL |
856 | |
857 | if (index < 0 || index >= KVM_MIPS_GUEST_TLB_SIZE) { | |
6ad78a5c | 858 | kvm_debug("%s: illegal index: %d\n", __func__, index); |
8cffd197 | 859 | kvm_debug("[%#lx] COP0_TLBWI [%d] (entryhi: %#lx, entrylo0: %#lx entrylo1: %#lx, mask: %#lx)\n", |
6ad78a5c DCZ |
860 | pc, index, kvm_read_c0_guest_entryhi(cop0), |
861 | kvm_read_c0_guest_entrylo0(cop0), | |
862 | kvm_read_c0_guest_entrylo1(cop0), | |
863 | kvm_read_c0_guest_pagemask(cop0)); | |
e685c689 SL |
864 | index = (index & ~0x80000000) % KVM_MIPS_GUEST_TLB_SIZE; |
865 | } | |
866 | ||
867 | tlb = &vcpu->arch.guest_tlb[index]; | |
d116e812 DCZ |
868 | /* |
869 | * Probe the shadow host TLB for the entry being overwritten, if one | |
870 | * matches, invalidate it | |
871 | */ | |
e685c689 | 872 | kvm_mips_host_tlb_inv(vcpu, tlb->tlb_hi); |
e685c689 SL |
873 | |
874 | tlb->tlb_mask = kvm_read_c0_guest_pagemask(cop0); | |
875 | tlb->tlb_hi = kvm_read_c0_guest_entryhi(cop0); | |
9fbfb06a JH |
876 | tlb->tlb_lo[0] = kvm_read_c0_guest_entrylo0(cop0); |
877 | tlb->tlb_lo[1] = kvm_read_c0_guest_entrylo1(cop0); | |
e685c689 | 878 | |
8cffd197 | 879 | kvm_debug("[%#lx] COP0_TLBWI [%d] (entryhi: %#lx, entrylo0: %#lx entrylo1: %#lx, mask: %#lx)\n", |
d116e812 DCZ |
880 | pc, index, kvm_read_c0_guest_entryhi(cop0), |
881 | kvm_read_c0_guest_entrylo0(cop0), | |
882 | kvm_read_c0_guest_entrylo1(cop0), | |
883 | kvm_read_c0_guest_pagemask(cop0)); | |
e685c689 | 884 | |
d98403a5 | 885 | return EMULATE_DONE; |
e685c689 SL |
886 | } |
887 | ||
888 | /* Write Guest TLB Entry @ Random Index */ | |
889 | enum emulation_result kvm_mips_emul_tlbwr(struct kvm_vcpu *vcpu) | |
890 | { | |
891 | struct mips_coproc *cop0 = vcpu->arch.cop0; | |
e685c689 | 892 | struct kvm_mips_tlb *tlb = NULL; |
8cffd197 | 893 | unsigned long pc = vcpu->arch.pc; |
e685c689 SL |
894 | int index; |
895 | ||
e685c689 SL |
896 | get_random_bytes(&index, sizeof(index)); |
897 | index &= (KVM_MIPS_GUEST_TLB_SIZE - 1); | |
e685c689 | 898 | |
e685c689 SL |
899 | tlb = &vcpu->arch.guest_tlb[index]; |
900 | ||
d116e812 DCZ |
901 | /* |
902 | * Probe the shadow host TLB for the entry being overwritten, if one | |
903 | * matches, invalidate it | |
904 | */ | |
e685c689 | 905 | kvm_mips_host_tlb_inv(vcpu, tlb->tlb_hi); |
e685c689 SL |
906 | |
907 | tlb->tlb_mask = kvm_read_c0_guest_pagemask(cop0); | |
908 | tlb->tlb_hi = kvm_read_c0_guest_entryhi(cop0); | |
9fbfb06a JH |
909 | tlb->tlb_lo[0] = kvm_read_c0_guest_entrylo0(cop0); |
910 | tlb->tlb_lo[1] = kvm_read_c0_guest_entrylo1(cop0); | |
e685c689 | 911 | |
8cffd197 | 912 | kvm_debug("[%#lx] COP0_TLBWR[%d] (entryhi: %#lx, entrylo0: %#lx entrylo1: %#lx)\n", |
d116e812 DCZ |
913 | pc, index, kvm_read_c0_guest_entryhi(cop0), |
914 | kvm_read_c0_guest_entrylo0(cop0), | |
915 | kvm_read_c0_guest_entrylo1(cop0)); | |
e685c689 | 916 | |
d98403a5 | 917 | return EMULATE_DONE; |
e685c689 SL |
918 | } |
919 | ||
920 | enum emulation_result kvm_mips_emul_tlbp(struct kvm_vcpu *vcpu) | |
921 | { | |
922 | struct mips_coproc *cop0 = vcpu->arch.cop0; | |
923 | long entryhi = kvm_read_c0_guest_entryhi(cop0); | |
8cffd197 | 924 | unsigned long pc = vcpu->arch.pc; |
e685c689 SL |
925 | int index = -1; |
926 | ||
927 | index = kvm_mips_guest_tlb_lookup(vcpu, entryhi); | |
928 | ||
929 | kvm_write_c0_guest_index(cop0, index); | |
930 | ||
8cffd197 | 931 | kvm_debug("[%#lx] COP0_TLBP (entryhi: %#lx), index: %d\n", pc, entryhi, |
e685c689 SL |
932 | index); |
933 | ||
d98403a5 | 934 | return EMULATE_DONE; |
e685c689 SL |
935 | } |
936 | ||
c771607a JH |
937 | /** |
938 | * kvm_mips_config1_wrmask() - Find mask of writable bits in guest Config1 | |
939 | * @vcpu: Virtual CPU. | |
940 | * | |
941 | * Finds the mask of bits which are writable in the guest's Config1 CP0 | |
942 | * register, by userland (currently read-only to the guest). | |
943 | */ | |
944 | unsigned int kvm_mips_config1_wrmask(struct kvm_vcpu *vcpu) | |
945 | { | |
6cdc65e3 JH |
946 | unsigned int mask = 0; |
947 | ||
948 | /* Permit FPU to be present if FPU is supported */ | |
949 | if (kvm_mips_guest_can_have_fpu(&vcpu->arch)) | |
950 | mask |= MIPS_CONF1_FP; | |
951 | ||
952 | return mask; | |
c771607a JH |
953 | } |
954 | ||
955 | /** | |
956 | * kvm_mips_config3_wrmask() - Find mask of writable bits in guest Config3 | |
957 | * @vcpu: Virtual CPU. | |
958 | * | |
959 | * Finds the mask of bits which are writable in the guest's Config3 CP0 | |
960 | * register, by userland (currently read-only to the guest). | |
961 | */ | |
962 | unsigned int kvm_mips_config3_wrmask(struct kvm_vcpu *vcpu) | |
963 | { | |
cef061d0 JH |
964 | /* Config4 and ULRI are optional */ |
965 | unsigned int mask = MIPS_CONF_M | MIPS_CONF3_ULRI; | |
2b6009d6 JH |
966 | |
967 | /* Permit MSA to be present if MSA is supported */ | |
968 | if (kvm_mips_guest_can_have_msa(&vcpu->arch)) | |
969 | mask |= MIPS_CONF3_MSA; | |
970 | ||
971 | return mask; | |
c771607a JH |
972 | } |
973 | ||
974 | /** | |
975 | * kvm_mips_config4_wrmask() - Find mask of writable bits in guest Config4 | |
976 | * @vcpu: Virtual CPU. | |
977 | * | |
978 | * Finds the mask of bits which are writable in the guest's Config4 CP0 | |
979 | * register, by userland (currently read-only to the guest). | |
980 | */ | |
981 | unsigned int kvm_mips_config4_wrmask(struct kvm_vcpu *vcpu) | |
982 | { | |
983 | /* Config5 is optional */ | |
05108709 JH |
984 | unsigned int mask = MIPS_CONF_M; |
985 | ||
986 | /* KScrExist */ | |
987 | mask |= (unsigned int)vcpu->arch.kscratch_enabled << 16; | |
988 | ||
989 | return mask; | |
c771607a JH |
990 | } |
991 | ||
992 | /** | |
993 | * kvm_mips_config5_wrmask() - Find mask of writable bits in guest Config5 | |
994 | * @vcpu: Virtual CPU. | |
995 | * | |
996 | * Finds the mask of bits which are writable in the guest's Config5 CP0 | |
997 | * register, by the guest itself. | |
998 | */ | |
999 | unsigned int kvm_mips_config5_wrmask(struct kvm_vcpu *vcpu) | |
1000 | { | |
6cdc65e3 JH |
1001 | unsigned int mask = 0; |
1002 | ||
2b6009d6 JH |
1003 | /* Permit MSAEn changes if MSA supported and enabled */ |
1004 | if (kvm_mips_guest_has_msa(&vcpu->arch)) | |
1005 | mask |= MIPS_CONF5_MSAEN; | |
1006 | ||
6cdc65e3 JH |
1007 | /* |
1008 | * Permit guest FPU mode changes if FPU is enabled and the relevant | |
1009 | * feature exists according to FIR register. | |
1010 | */ | |
1011 | if (kvm_mips_guest_has_fpu(&vcpu->arch)) { | |
1012 | if (cpu_has_fre) | |
1013 | mask |= MIPS_CONF5_FRE; | |
1014 | /* We don't support UFR or UFE */ | |
1015 | } | |
1016 | ||
1017 | return mask; | |
c771607a JH |
1018 | } |
1019 | ||
258f3a2e JH |
1020 | enum emulation_result kvm_mips_emulate_CP0(union mips_instruction inst, |
1021 | u32 *opc, u32 cause, | |
bdb7ed86 | 1022 | struct kvm_run *run, |
d116e812 | 1023 | struct kvm_vcpu *vcpu) |
e685c689 SL |
1024 | { |
1025 | struct mips_coproc *cop0 = vcpu->arch.cop0; | |
1026 | enum emulation_result er = EMULATE_DONE; | |
258f3a2e | 1027 | u32 rt, rd, sel; |
e685c689 SL |
1028 | unsigned long curr_pc; |
1029 | ||
1030 | /* | |
1031 | * Update PC and hold onto current PC in case there is | |
1032 | * an error and we want to rollback the PC | |
1033 | */ | |
1034 | curr_pc = vcpu->arch.pc; | |
1035 | er = update_pc(vcpu, cause); | |
d116e812 | 1036 | if (er == EMULATE_FAIL) |
e685c689 | 1037 | return er; |
e685c689 | 1038 | |
258f3a2e JH |
1039 | if (inst.co_format.co) { |
1040 | switch (inst.co_format.func) { | |
e685c689 SL |
1041 | case tlbr_op: /* Read indexed TLB entry */ |
1042 | er = kvm_mips_emul_tlbr(vcpu); | |
1043 | break; | |
1044 | case tlbwi_op: /* Write indexed */ | |
1045 | er = kvm_mips_emul_tlbwi(vcpu); | |
1046 | break; | |
1047 | case tlbwr_op: /* Write random */ | |
1048 | er = kvm_mips_emul_tlbwr(vcpu); | |
1049 | break; | |
1050 | case tlbp_op: /* TLB Probe */ | |
1051 | er = kvm_mips_emul_tlbp(vcpu); | |
1052 | break; | |
1053 | case rfe_op: | |
6ad78a5c | 1054 | kvm_err("!!!COP0_RFE!!!\n"); |
e685c689 SL |
1055 | break; |
1056 | case eret_op: | |
1057 | er = kvm_mips_emul_eret(vcpu); | |
1058 | goto dont_update_pc; | |
e685c689 SL |
1059 | case wait_op: |
1060 | er = kvm_mips_emul_wait(vcpu); | |
1061 | break; | |
1062 | } | |
1063 | } else { | |
258f3a2e JH |
1064 | rt = inst.c0r_format.rt; |
1065 | rd = inst.c0r_format.rd; | |
1066 | sel = inst.c0r_format.sel; | |
1067 | ||
1068 | switch (inst.c0r_format.rs) { | |
e685c689 SL |
1069 | case mfc_op: |
1070 | #ifdef CONFIG_KVM_MIPS_DEBUG_COP0_COUNTERS | |
1071 | cop0->stat[rd][sel]++; | |
1072 | #endif | |
1073 | /* Get reg */ | |
1074 | if ((rd == MIPS_CP0_COUNT) && (sel == 0)) { | |
e30492bb | 1075 | vcpu->arch.gprs[rt] = kvm_mips_read_count(vcpu); |
e685c689 SL |
1076 | } else if ((rd == MIPS_CP0_ERRCTL) && (sel == 0)) { |
1077 | vcpu->arch.gprs[rt] = 0x0; | |
1078 | #ifdef CONFIG_KVM_MIPS_DYN_TRANS | |
1079 | kvm_mips_trans_mfc0(inst, opc, vcpu); | |
1080 | #endif | |
d116e812 | 1081 | } else { |
e685c689 SL |
1082 | vcpu->arch.gprs[rt] = cop0->reg[rd][sel]; |
1083 | ||
1084 | #ifdef CONFIG_KVM_MIPS_DYN_TRANS | |
1085 | kvm_mips_trans_mfc0(inst, opc, vcpu); | |
1086 | #endif | |
1087 | } | |
1088 | ||
6398da13 JH |
1089 | trace_kvm_hwr(vcpu, KVM_TRACE_MFC0, |
1090 | KVM_TRACE_COP0(rd, sel), | |
1091 | vcpu->arch.gprs[rt]); | |
e685c689 SL |
1092 | break; |
1093 | ||
1094 | case dmfc_op: | |
1095 | vcpu->arch.gprs[rt] = cop0->reg[rd][sel]; | |
6398da13 JH |
1096 | |
1097 | trace_kvm_hwr(vcpu, KVM_TRACE_DMFC0, | |
1098 | KVM_TRACE_COP0(rd, sel), | |
1099 | vcpu->arch.gprs[rt]); | |
e685c689 SL |
1100 | break; |
1101 | ||
1102 | case mtc_op: | |
1103 | #ifdef CONFIG_KVM_MIPS_DEBUG_COP0_COUNTERS | |
1104 | cop0->stat[rd][sel]++; | |
1105 | #endif | |
6398da13 JH |
1106 | trace_kvm_hwr(vcpu, KVM_TRACE_MTC0, |
1107 | KVM_TRACE_COP0(rd, sel), | |
1108 | vcpu->arch.gprs[rt]); | |
1109 | ||
e685c689 SL |
1110 | if ((rd == MIPS_CP0_TLB_INDEX) |
1111 | && (vcpu->arch.gprs[rt] >= | |
1112 | KVM_MIPS_GUEST_TLB_SIZE)) { | |
6ad78a5c DCZ |
1113 | kvm_err("Invalid TLB Index: %ld", |
1114 | vcpu->arch.gprs[rt]); | |
e685c689 SL |
1115 | er = EMULATE_FAIL; |
1116 | break; | |
1117 | } | |
1118 | #define C0_EBASE_CORE_MASK 0xff | |
1119 | if ((rd == MIPS_CP0_PRID) && (sel == 1)) { | |
1120 | /* Preserve CORE number */ | |
1121 | kvm_change_c0_guest_ebase(cop0, | |
1122 | ~(C0_EBASE_CORE_MASK), | |
1123 | vcpu->arch.gprs[rt]); | |
6ad78a5c DCZ |
1124 | kvm_err("MTCz, cop0->reg[EBASE]: %#lx\n", |
1125 | kvm_read_c0_guest_ebase(cop0)); | |
e685c689 | 1126 | } else if (rd == MIPS_CP0_TLB_HI && sel == 0) { |
8cffd197 | 1127 | u32 nasid = |
ca64c2be | 1128 | vcpu->arch.gprs[rt] & KVM_ENTRYHI_ASID; |
d116e812 | 1129 | if ((KSEGX(vcpu->arch.gprs[rt]) != CKSEG0) && |
48c4ac97 | 1130 | ((kvm_read_c0_guest_entryhi(cop0) & |
ca64c2be | 1131 | KVM_ENTRYHI_ASID) != nasid)) { |
9887d1c7 | 1132 | trace_kvm_asid_change(vcpu, |
d116e812 | 1133 | kvm_read_c0_guest_entryhi(cop0) |
9887d1c7 JH |
1134 | & KVM_ENTRYHI_ASID, |
1135 | nasid); | |
e685c689 SL |
1136 | |
1137 | /* Blow away the shadow host TLBs */ | |
1138 | kvm_mips_flush_host_tlb(1); | |
1139 | } | |
1140 | kvm_write_c0_guest_entryhi(cop0, | |
1141 | vcpu->arch.gprs[rt]); | |
1142 | } | |
1143 | /* Are we writing to COUNT */ | |
1144 | else if ((rd == MIPS_CP0_COUNT) && (sel == 0)) { | |
e30492bb | 1145 | kvm_mips_write_count(vcpu, vcpu->arch.gprs[rt]); |
e685c689 SL |
1146 | goto done; |
1147 | } else if ((rd == MIPS_CP0_COMPARE) && (sel == 0)) { | |
e685c689 SL |
1148 | /* If we are writing to COMPARE */ |
1149 | /* Clear pending timer interrupt, if any */ | |
e30492bb | 1150 | kvm_mips_write_compare(vcpu, |
b45bacd2 JH |
1151 | vcpu->arch.gprs[rt], |
1152 | true); | |
e685c689 | 1153 | } else if ((rd == MIPS_CP0_STATUS) && (sel == 0)) { |
6cdc65e3 JH |
1154 | unsigned int old_val, val, change; |
1155 | ||
1156 | old_val = kvm_read_c0_guest_status(cop0); | |
1157 | val = vcpu->arch.gprs[rt]; | |
1158 | change = val ^ old_val; | |
1159 | ||
1160 | /* Make sure that the NMI bit is never set */ | |
1161 | val &= ~ST0_NMI; | |
1162 | ||
1163 | /* | |
1164 | * Don't allow CU1 or FR to be set unless FPU | |
1165 | * capability enabled and exists in guest | |
1166 | * configuration. | |
1167 | */ | |
1168 | if (!kvm_mips_guest_has_fpu(&vcpu->arch)) | |
1169 | val &= ~(ST0_CU1 | ST0_FR); | |
1170 | ||
1171 | /* | |
1172 | * Also don't allow FR to be set if host doesn't | |
1173 | * support it. | |
1174 | */ | |
1175 | if (!(current_cpu_data.fpu_id & MIPS_FPIR_F64)) | |
1176 | val &= ~ST0_FR; | |
1177 | ||
1178 | ||
1179 | /* Handle changes in FPU mode */ | |
1180 | preempt_disable(); | |
1181 | ||
1182 | /* | |
1183 | * FPU and Vector register state is made | |
1184 | * UNPREDICTABLE by a change of FR, so don't | |
1185 | * even bother saving it. | |
1186 | */ | |
1187 | if (change & ST0_FR) | |
1188 | kvm_drop_fpu(vcpu); | |
1189 | ||
2b6009d6 JH |
1190 | /* |
1191 | * If MSA state is already live, it is undefined | |
1192 | * how it interacts with FR=0 FPU state, and we | |
1193 | * don't want to hit reserved instruction | |
1194 | * exceptions trying to save the MSA state later | |
1195 | * when CU=1 && FR=1, so play it safe and save | |
1196 | * it first. | |
1197 | */ | |
1198 | if (change & ST0_CU1 && !(val & ST0_FR) && | |
f943176a | 1199 | vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) |
2b6009d6 JH |
1200 | kvm_lose_fpu(vcpu); |
1201 | ||
d116e812 | 1202 | /* |
6cdc65e3 JH |
1203 | * Propagate CU1 (FPU enable) changes |
1204 | * immediately if the FPU context is already | |
1205 | * loaded. When disabling we leave the context | |
1206 | * loaded so it can be quickly enabled again in | |
1207 | * the near future. | |
d116e812 | 1208 | */ |
6cdc65e3 | 1209 | if (change & ST0_CU1 && |
f943176a | 1210 | vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) |
6cdc65e3 JH |
1211 | change_c0_status(ST0_CU1, val); |
1212 | ||
1213 | preempt_enable(); | |
1214 | ||
1215 | kvm_write_c0_guest_status(cop0, val); | |
e685c689 SL |
1216 | |
1217 | #ifdef CONFIG_KVM_MIPS_DYN_TRANS | |
6cdc65e3 JH |
1218 | /* |
1219 | * If FPU present, we need CU1/FR bits to take | |
1220 | * effect fairly soon. | |
1221 | */ | |
1222 | if (!kvm_mips_guest_has_fpu(&vcpu->arch)) | |
1223 | kvm_mips_trans_mtc0(inst, opc, vcpu); | |
e685c689 | 1224 | #endif |
6cdc65e3 JH |
1225 | } else if ((rd == MIPS_CP0_CONFIG) && (sel == 5)) { |
1226 | unsigned int old_val, val, change, wrmask; | |
1227 | ||
1228 | old_val = kvm_read_c0_guest_config5(cop0); | |
1229 | val = vcpu->arch.gprs[rt]; | |
1230 | ||
1231 | /* Only a few bits are writable in Config5 */ | |
1232 | wrmask = kvm_mips_config5_wrmask(vcpu); | |
1233 | change = (val ^ old_val) & wrmask; | |
1234 | val = old_val ^ change; | |
1235 | ||
1236 | ||
2b6009d6 | 1237 | /* Handle changes in FPU/MSA modes */ |
6cdc65e3 JH |
1238 | preempt_disable(); |
1239 | ||
1240 | /* | |
1241 | * Propagate FRE changes immediately if the FPU | |
1242 | * context is already loaded. | |
1243 | */ | |
1244 | if (change & MIPS_CONF5_FRE && | |
f943176a | 1245 | vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) |
6cdc65e3 JH |
1246 | change_c0_config5(MIPS_CONF5_FRE, val); |
1247 | ||
2b6009d6 JH |
1248 | /* |
1249 | * Propagate MSAEn changes immediately if the | |
1250 | * MSA context is already loaded. When disabling | |
1251 | * we leave the context loaded so it can be | |
1252 | * quickly enabled again in the near future. | |
1253 | */ | |
1254 | if (change & MIPS_CONF5_MSAEN && | |
f943176a | 1255 | vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) |
2b6009d6 JH |
1256 | change_c0_config5(MIPS_CONF5_MSAEN, |
1257 | val); | |
1258 | ||
6cdc65e3 JH |
1259 | preempt_enable(); |
1260 | ||
1261 | kvm_write_c0_guest_config5(cop0, val); | |
e30492bb | 1262 | } else if ((rd == MIPS_CP0_CAUSE) && (sel == 0)) { |
8cffd197 | 1263 | u32 old_cause, new_cause; |
d116e812 | 1264 | |
e30492bb JH |
1265 | old_cause = kvm_read_c0_guest_cause(cop0); |
1266 | new_cause = vcpu->arch.gprs[rt]; | |
1267 | /* Update R/W bits */ | |
1268 | kvm_change_c0_guest_cause(cop0, 0x08800300, | |
1269 | new_cause); | |
1270 | /* DC bit enabling/disabling timer? */ | |
1271 | if ((old_cause ^ new_cause) & CAUSEF_DC) { | |
1272 | if (new_cause & CAUSEF_DC) | |
1273 | kvm_mips_count_disable_cause(vcpu); | |
1274 | else | |
1275 | kvm_mips_count_enable_cause(vcpu); | |
1276 | } | |
cef061d0 JH |
1277 | } else if ((rd == MIPS_CP0_HWRENA) && (sel == 0)) { |
1278 | u32 mask = MIPS_HWRENA_CPUNUM | | |
1279 | MIPS_HWRENA_SYNCISTEP | | |
1280 | MIPS_HWRENA_CC | | |
1281 | MIPS_HWRENA_CCRES; | |
1282 | ||
1283 | if (kvm_read_c0_guest_config3(cop0) & | |
1284 | MIPS_CONF3_ULRI) | |
1285 | mask |= MIPS_HWRENA_ULR; | |
1286 | cop0->reg[rd][sel] = vcpu->arch.gprs[rt] & mask; | |
e685c689 SL |
1287 | } else { |
1288 | cop0->reg[rd][sel] = vcpu->arch.gprs[rt]; | |
1289 | #ifdef CONFIG_KVM_MIPS_DYN_TRANS | |
1290 | kvm_mips_trans_mtc0(inst, opc, vcpu); | |
1291 | #endif | |
1292 | } | |
e685c689 SL |
1293 | break; |
1294 | ||
1295 | case dmtc_op: | |
6ad78a5c DCZ |
1296 | kvm_err("!!!!!!![%#lx]dmtc_op: rt: %d, rd: %d, sel: %d!!!!!!\n", |
1297 | vcpu->arch.pc, rt, rd, sel); | |
6398da13 JH |
1298 | trace_kvm_hwr(vcpu, KVM_TRACE_DMTC0, |
1299 | KVM_TRACE_COP0(rd, sel), | |
1300 | vcpu->arch.gprs[rt]); | |
e685c689 SL |
1301 | er = EMULATE_FAIL; |
1302 | break; | |
1303 | ||
b2c59635 | 1304 | case mfmc0_op: |
e685c689 SL |
1305 | #ifdef KVM_MIPS_DEBUG_COP0_COUNTERS |
1306 | cop0->stat[MIPS_CP0_STATUS][0]++; | |
1307 | #endif | |
caa1faa7 | 1308 | if (rt != 0) |
e685c689 SL |
1309 | vcpu->arch.gprs[rt] = |
1310 | kvm_read_c0_guest_status(cop0); | |
e685c689 | 1311 | /* EI */ |
258f3a2e | 1312 | if (inst.mfmc0_format.sc) { |
b2c59635 | 1313 | kvm_debug("[%#lx] mfmc0_op: EI\n", |
e685c689 SL |
1314 | vcpu->arch.pc); |
1315 | kvm_set_c0_guest_status(cop0, ST0_IE); | |
1316 | } else { | |
b2c59635 | 1317 | kvm_debug("[%#lx] mfmc0_op: DI\n", |
e685c689 SL |
1318 | vcpu->arch.pc); |
1319 | kvm_clear_c0_guest_status(cop0, ST0_IE); | |
1320 | } | |
1321 | ||
1322 | break; | |
1323 | ||
1324 | case wrpgpr_op: | |
1325 | { | |
8cffd197 JH |
1326 | u32 css = cop0->reg[MIPS_CP0_STATUS][2] & 0xf; |
1327 | u32 pss = | |
e685c689 | 1328 | (cop0->reg[MIPS_CP0_STATUS][2] >> 6) & 0xf; |
d116e812 DCZ |
1329 | /* |
1330 | * We don't support any shadow register sets, so | |
1331 | * SRSCtl[PSS] == SRSCtl[CSS] = 0 | |
1332 | */ | |
e685c689 SL |
1333 | if (css || pss) { |
1334 | er = EMULATE_FAIL; | |
1335 | break; | |
1336 | } | |
1337 | kvm_debug("WRPGPR[%d][%d] = %#lx\n", pss, rd, | |
1338 | vcpu->arch.gprs[rt]); | |
1339 | vcpu->arch.gprs[rd] = vcpu->arch.gprs[rt]; | |
1340 | } | |
1341 | break; | |
1342 | default: | |
6ad78a5c | 1343 | kvm_err("[%#lx]MachEmulateCP0: unsupported COP0, copz: 0x%x\n", |
258f3a2e | 1344 | vcpu->arch.pc, inst.c0r_format.rs); |
e685c689 SL |
1345 | er = EMULATE_FAIL; |
1346 | break; | |
1347 | } | |
1348 | } | |
1349 | ||
1350 | done: | |
d116e812 DCZ |
1351 | /* Rollback PC only if emulation was unsuccessful */ |
1352 | if (er == EMULATE_FAIL) | |
e685c689 | 1353 | vcpu->arch.pc = curr_pc; |
e685c689 SL |
1354 | |
1355 | dont_update_pc: | |
1356 | /* | |
1357 | * This is for special instructions whose emulation | |
1358 | * updates the PC, so do not overwrite the PC under | |
1359 | * any circumstances | |
1360 | */ | |
1361 | ||
1362 | return er; | |
1363 | } | |
1364 | ||
258f3a2e JH |
1365 | enum emulation_result kvm_mips_emulate_store(union mips_instruction inst, |
1366 | u32 cause, | |
d116e812 DCZ |
1367 | struct kvm_run *run, |
1368 | struct kvm_vcpu *vcpu) | |
e685c689 SL |
1369 | { |
1370 | enum emulation_result er = EMULATE_DO_MMIO; | |
258f3a2e | 1371 | u32 rt; |
8cffd197 | 1372 | u32 bytes; |
e685c689 SL |
1373 | void *data = run->mmio.data; |
1374 | unsigned long curr_pc; | |
1375 | ||
1376 | /* | |
1377 | * Update PC and hold onto current PC in case there is | |
1378 | * an error and we want to rollback the PC | |
1379 | */ | |
1380 | curr_pc = vcpu->arch.pc; | |
1381 | er = update_pc(vcpu, cause); | |
1382 | if (er == EMULATE_FAIL) | |
1383 | return er; | |
1384 | ||
258f3a2e | 1385 | rt = inst.i_format.rt; |
e685c689 | 1386 | |
258f3a2e | 1387 | switch (inst.i_format.opcode) { |
e685c689 SL |
1388 | case sb_op: |
1389 | bytes = 1; | |
1390 | if (bytes > sizeof(run->mmio.data)) { | |
1391 | kvm_err("%s: bad MMIO length: %d\n", __func__, | |
1392 | run->mmio.len); | |
1393 | } | |
1394 | run->mmio.phys_addr = | |
1395 | kvm_mips_callbacks->gva_to_gpa(vcpu->arch. | |
1396 | host_cp0_badvaddr); | |
1397 | if (run->mmio.phys_addr == KVM_INVALID_ADDR) { | |
1398 | er = EMULATE_FAIL; | |
1399 | break; | |
1400 | } | |
1401 | run->mmio.len = bytes; | |
1402 | run->mmio.is_write = 1; | |
1403 | vcpu->mmio_needed = 1; | |
1404 | vcpu->mmio_is_write = 1; | |
1405 | *(u8 *) data = vcpu->arch.gprs[rt]; | |
1406 | kvm_debug("OP_SB: eaddr: %#lx, gpr: %#lx, data: %#x\n", | |
1407 | vcpu->arch.host_cp0_badvaddr, vcpu->arch.gprs[rt], | |
8cffd197 | 1408 | *(u8 *) data); |
e685c689 SL |
1409 | |
1410 | break; | |
1411 | ||
1412 | case sw_op: | |
1413 | bytes = 4; | |
1414 | if (bytes > sizeof(run->mmio.data)) { | |
1415 | kvm_err("%s: bad MMIO length: %d\n", __func__, | |
1416 | run->mmio.len); | |
1417 | } | |
1418 | run->mmio.phys_addr = | |
1419 | kvm_mips_callbacks->gva_to_gpa(vcpu->arch. | |
1420 | host_cp0_badvaddr); | |
1421 | if (run->mmio.phys_addr == KVM_INVALID_ADDR) { | |
1422 | er = EMULATE_FAIL; | |
1423 | break; | |
1424 | } | |
1425 | ||
1426 | run->mmio.len = bytes; | |
1427 | run->mmio.is_write = 1; | |
1428 | vcpu->mmio_needed = 1; | |
1429 | vcpu->mmio_is_write = 1; | |
8cffd197 | 1430 | *(u32 *) data = vcpu->arch.gprs[rt]; |
e685c689 SL |
1431 | |
1432 | kvm_debug("[%#lx] OP_SW: eaddr: %#lx, gpr: %#lx, data: %#x\n", | |
1433 | vcpu->arch.pc, vcpu->arch.host_cp0_badvaddr, | |
8cffd197 | 1434 | vcpu->arch.gprs[rt], *(u32 *) data); |
e685c689 SL |
1435 | break; |
1436 | ||
1437 | case sh_op: | |
1438 | bytes = 2; | |
1439 | if (bytes > sizeof(run->mmio.data)) { | |
1440 | kvm_err("%s: bad MMIO length: %d\n", __func__, | |
1441 | run->mmio.len); | |
1442 | } | |
1443 | run->mmio.phys_addr = | |
1444 | kvm_mips_callbacks->gva_to_gpa(vcpu->arch. | |
1445 | host_cp0_badvaddr); | |
1446 | if (run->mmio.phys_addr == KVM_INVALID_ADDR) { | |
1447 | er = EMULATE_FAIL; | |
1448 | break; | |
1449 | } | |
1450 | ||
1451 | run->mmio.len = bytes; | |
1452 | run->mmio.is_write = 1; | |
1453 | vcpu->mmio_needed = 1; | |
1454 | vcpu->mmio_is_write = 1; | |
8cffd197 | 1455 | *(u16 *) data = vcpu->arch.gprs[rt]; |
e685c689 SL |
1456 | |
1457 | kvm_debug("[%#lx] OP_SH: eaddr: %#lx, gpr: %#lx, data: %#x\n", | |
1458 | vcpu->arch.pc, vcpu->arch.host_cp0_badvaddr, | |
8cffd197 | 1459 | vcpu->arch.gprs[rt], *(u32 *) data); |
e685c689 SL |
1460 | break; |
1461 | ||
1462 | default: | |
d86c1ebe | 1463 | kvm_err("Store not yet supported (inst=0x%08x)\n", |
258f3a2e | 1464 | inst.word); |
e685c689 SL |
1465 | er = EMULATE_FAIL; |
1466 | break; | |
1467 | } | |
1468 | ||
d116e812 DCZ |
1469 | /* Rollback PC if emulation was unsuccessful */ |
1470 | if (er == EMULATE_FAIL) | |
e685c689 | 1471 | vcpu->arch.pc = curr_pc; |
e685c689 SL |
1472 | |
1473 | return er; | |
1474 | } | |
1475 | ||
258f3a2e JH |
1476 | enum emulation_result kvm_mips_emulate_load(union mips_instruction inst, |
1477 | u32 cause, struct kvm_run *run, | |
d116e812 | 1478 | struct kvm_vcpu *vcpu) |
e685c689 SL |
1479 | { |
1480 | enum emulation_result er = EMULATE_DO_MMIO; | |
258f3a2e | 1481 | u32 op, rt; |
8cffd197 | 1482 | u32 bytes; |
e685c689 | 1483 | |
258f3a2e JH |
1484 | rt = inst.i_format.rt; |
1485 | op = inst.i_format.opcode; | |
e685c689 SL |
1486 | |
1487 | vcpu->arch.pending_load_cause = cause; | |
1488 | vcpu->arch.io_gpr = rt; | |
1489 | ||
1490 | switch (op) { | |
1491 | case lw_op: | |
1492 | bytes = 4; | |
1493 | if (bytes > sizeof(run->mmio.data)) { | |
1494 | kvm_err("%s: bad MMIO length: %d\n", __func__, | |
1495 | run->mmio.len); | |
1496 | er = EMULATE_FAIL; | |
1497 | break; | |
1498 | } | |
1499 | run->mmio.phys_addr = | |
1500 | kvm_mips_callbacks->gva_to_gpa(vcpu->arch. | |
1501 | host_cp0_badvaddr); | |
1502 | if (run->mmio.phys_addr == KVM_INVALID_ADDR) { | |
1503 | er = EMULATE_FAIL; | |
1504 | break; | |
1505 | } | |
1506 | ||
1507 | run->mmio.len = bytes; | |
1508 | run->mmio.is_write = 0; | |
1509 | vcpu->mmio_needed = 1; | |
1510 | vcpu->mmio_is_write = 0; | |
1511 | break; | |
1512 | ||
1513 | case lh_op: | |
1514 | case lhu_op: | |
1515 | bytes = 2; | |
1516 | if (bytes > sizeof(run->mmio.data)) { | |
1517 | kvm_err("%s: bad MMIO length: %d\n", __func__, | |
1518 | run->mmio.len); | |
1519 | er = EMULATE_FAIL; | |
1520 | break; | |
1521 | } | |
1522 | run->mmio.phys_addr = | |
1523 | kvm_mips_callbacks->gva_to_gpa(vcpu->arch. | |
1524 | host_cp0_badvaddr); | |
1525 | if (run->mmio.phys_addr == KVM_INVALID_ADDR) { | |
1526 | er = EMULATE_FAIL; | |
1527 | break; | |
1528 | } | |
1529 | ||
1530 | run->mmio.len = bytes; | |
1531 | run->mmio.is_write = 0; | |
1532 | vcpu->mmio_needed = 1; | |
1533 | vcpu->mmio_is_write = 0; | |
1534 | ||
1535 | if (op == lh_op) | |
1536 | vcpu->mmio_needed = 2; | |
1537 | else | |
1538 | vcpu->mmio_needed = 1; | |
1539 | ||
1540 | break; | |
1541 | ||
1542 | case lbu_op: | |
1543 | case lb_op: | |
1544 | bytes = 1; | |
1545 | if (bytes > sizeof(run->mmio.data)) { | |
1546 | kvm_err("%s: bad MMIO length: %d\n", __func__, | |
1547 | run->mmio.len); | |
1548 | er = EMULATE_FAIL; | |
1549 | break; | |
1550 | } | |
1551 | run->mmio.phys_addr = | |
1552 | kvm_mips_callbacks->gva_to_gpa(vcpu->arch. | |
1553 | host_cp0_badvaddr); | |
1554 | if (run->mmio.phys_addr == KVM_INVALID_ADDR) { | |
1555 | er = EMULATE_FAIL; | |
1556 | break; | |
1557 | } | |
1558 | ||
1559 | run->mmio.len = bytes; | |
1560 | run->mmio.is_write = 0; | |
1561 | vcpu->mmio_is_write = 0; | |
1562 | ||
1563 | if (op == lb_op) | |
1564 | vcpu->mmio_needed = 2; | |
1565 | else | |
1566 | vcpu->mmio_needed = 1; | |
1567 | ||
1568 | break; | |
1569 | ||
1570 | default: | |
d86c1ebe | 1571 | kvm_err("Load not yet supported (inst=0x%08x)\n", |
258f3a2e | 1572 | inst.word); |
e685c689 SL |
1573 | er = EMULATE_FAIL; |
1574 | break; | |
1575 | } | |
1576 | ||
1577 | return er; | |
1578 | } | |
1579 | ||
258f3a2e JH |
1580 | enum emulation_result kvm_mips_emulate_cache(union mips_instruction inst, |
1581 | u32 *opc, u32 cause, | |
d116e812 DCZ |
1582 | struct kvm_run *run, |
1583 | struct kvm_vcpu *vcpu) | |
e685c689 SL |
1584 | { |
1585 | struct mips_coproc *cop0 = vcpu->arch.cop0; | |
e685c689 | 1586 | enum emulation_result er = EMULATE_DONE; |
8cffd197 JH |
1587 | u32 cache, op_inst, op, base; |
1588 | s16 offset; | |
e685c689 SL |
1589 | struct kvm_vcpu_arch *arch = &vcpu->arch; |
1590 | unsigned long va; | |
1591 | unsigned long curr_pc; | |
1592 | ||
1593 | /* | |
1594 | * Update PC and hold onto current PC in case there is | |
1595 | * an error and we want to rollback the PC | |
1596 | */ | |
1597 | curr_pc = vcpu->arch.pc; | |
1598 | er = update_pc(vcpu, cause); | |
1599 | if (er == EMULATE_FAIL) | |
1600 | return er; | |
1601 | ||
258f3a2e JH |
1602 | base = inst.i_format.rs; |
1603 | op_inst = inst.i_format.rt; | |
5cc4aafc JH |
1604 | if (cpu_has_mips_r6) |
1605 | offset = inst.spec3_format.simmediate; | |
1606 | else | |
1607 | offset = inst.i_format.simmediate; | |
f4956f62 JH |
1608 | cache = op_inst & CacheOp_Cache; |
1609 | op = op_inst & CacheOp_Op; | |
e685c689 SL |
1610 | |
1611 | va = arch->gprs[base] + offset; | |
1612 | ||
1613 | kvm_debug("CACHE (cache: %#x, op: %#x, base[%d]: %#lx, offset: %#x\n", | |
1614 | cache, op, base, arch->gprs[base], offset); | |
1615 | ||
d116e812 DCZ |
1616 | /* |
1617 | * Treat INDEX_INV as a nop, basically issued by Linux on startup to | |
1618 | * invalidate the caches entirely by stepping through all the | |
1619 | * ways/indexes | |
e685c689 | 1620 | */ |
f4956f62 | 1621 | if (op == Index_Writeback_Inv) { |
d116e812 DCZ |
1622 | kvm_debug("@ %#lx/%#lx CACHE (cache: %#x, op: %#x, base[%d]: %#lx, offset: %#x\n", |
1623 | vcpu->arch.pc, vcpu->arch.gprs[31], cache, op, base, | |
1624 | arch->gprs[base], offset); | |
e685c689 | 1625 | |
f4956f62 | 1626 | if (cache == Cache_D) |
e685c689 | 1627 | r4k_blast_dcache(); |
f4956f62 | 1628 | else if (cache == Cache_I) |
e685c689 SL |
1629 | r4k_blast_icache(); |
1630 | else { | |
6ad78a5c DCZ |
1631 | kvm_err("%s: unsupported CACHE INDEX operation\n", |
1632 | __func__); | |
e685c689 SL |
1633 | return EMULATE_FAIL; |
1634 | } | |
1635 | ||
1636 | #ifdef CONFIG_KVM_MIPS_DYN_TRANS | |
1637 | kvm_mips_trans_cache_index(inst, opc, vcpu); | |
1638 | #endif | |
1639 | goto done; | |
1640 | } | |
1641 | ||
1642 | preempt_disable(); | |
1643 | if (KVM_GUEST_KSEGX(va) == KVM_GUEST_KSEG0) { | |
d116e812 | 1644 | if (kvm_mips_host_tlb_lookup(vcpu, va) < 0) |
e685c689 | 1645 | kvm_mips_handle_kseg0_tlb_fault(va, vcpu); |
e685c689 SL |
1646 | } else if ((KVM_GUEST_KSEGX(va) < KVM_GUEST_KSEG0) || |
1647 | KVM_GUEST_KSEGX(va) == KVM_GUEST_KSEG23) { | |
1648 | int index; | |
1649 | ||
1650 | /* If an entry already exists then skip */ | |
d116e812 | 1651 | if (kvm_mips_host_tlb_lookup(vcpu, va) >= 0) |
e685c689 | 1652 | goto skip_fault; |
e685c689 | 1653 | |
d116e812 DCZ |
1654 | /* |
1655 | * If address not in the guest TLB, then give the guest a fault, | |
1656 | * the resulting handler will do the right thing | |
e685c689 SL |
1657 | */ |
1658 | index = kvm_mips_guest_tlb_lookup(vcpu, (va & VPN2_MASK) | | |
48c4ac97 | 1659 | (kvm_read_c0_guest_entryhi |
ca64c2be | 1660 | (cop0) & KVM_ENTRYHI_ASID)); |
e685c689 SL |
1661 | |
1662 | if (index < 0) { | |
e685c689 | 1663 | vcpu->arch.host_cp0_badvaddr = va; |
6df82a7b | 1664 | vcpu->arch.pc = curr_pc; |
e685c689 SL |
1665 | er = kvm_mips_emulate_tlbmiss_ld(cause, NULL, run, |
1666 | vcpu); | |
1667 | preempt_enable(); | |
1668 | goto dont_update_pc; | |
1669 | } else { | |
1670 | struct kvm_mips_tlb *tlb = &vcpu->arch.guest_tlb[index]; | |
d116e812 DCZ |
1671 | /* |
1672 | * Check if the entry is valid, if not then setup a TLB | |
1673 | * invalid exception to the guest | |
1674 | */ | |
e685c689 | 1675 | if (!TLB_IS_VALID(*tlb, va)) { |
6df82a7b JH |
1676 | vcpu->arch.host_cp0_badvaddr = va; |
1677 | vcpu->arch.pc = curr_pc; | |
e685c689 SL |
1678 | er = kvm_mips_emulate_tlbinv_ld(cause, NULL, |
1679 | run, vcpu); | |
1680 | preempt_enable(); | |
1681 | goto dont_update_pc; | |
1682 | } else { | |
d116e812 DCZ |
1683 | /* |
1684 | * We fault an entry from the guest tlb to the | |
1685 | * shadow host TLB | |
1686 | */ | |
26ee17ff | 1687 | kvm_mips_handle_mapped_seg_tlb_fault(vcpu, tlb); |
e685c689 SL |
1688 | } |
1689 | } | |
1690 | } else { | |
6ad78a5c DCZ |
1691 | kvm_err("INVALID CACHE INDEX/ADDRESS (cache: %#x, op: %#x, base[%d]: %#lx, offset: %#x\n", |
1692 | cache, op, base, arch->gprs[base], offset); | |
e685c689 SL |
1693 | er = EMULATE_FAIL; |
1694 | preempt_enable(); | |
cc81e948 | 1695 | goto done; |
e685c689 SL |
1696 | |
1697 | } | |
1698 | ||
1699 | skip_fault: | |
1700 | /* XXXKYMA: Only a subset of cache ops are supported, used by Linux */ | |
f4956f62 | 1701 | if (op_inst == Hit_Writeback_Inv_D || op_inst == Hit_Invalidate_D) { |
e685c689 SL |
1702 | flush_dcache_line(va); |
1703 | ||
1704 | #ifdef CONFIG_KVM_MIPS_DYN_TRANS | |
d116e812 DCZ |
1705 | /* |
1706 | * Replace the CACHE instruction, with a SYNCI, not the same, | |
1707 | * but avoids a trap | |
1708 | */ | |
e685c689 SL |
1709 | kvm_mips_trans_cache_va(inst, opc, vcpu); |
1710 | #endif | |
f4956f62 | 1711 | } else if (op_inst == Hit_Invalidate_I) { |
e685c689 SL |
1712 | flush_dcache_line(va); |
1713 | flush_icache_line(va); | |
1714 | ||
1715 | #ifdef CONFIG_KVM_MIPS_DYN_TRANS | |
1716 | /* Replace the CACHE instruction, with a SYNCI */ | |
1717 | kvm_mips_trans_cache_va(inst, opc, vcpu); | |
1718 | #endif | |
1719 | } else { | |
6ad78a5c DCZ |
1720 | kvm_err("NO-OP CACHE (cache: %#x, op: %#x, base[%d]: %#lx, offset: %#x\n", |
1721 | cache, op, base, arch->gprs[base], offset); | |
e685c689 | 1722 | er = EMULATE_FAIL; |
e685c689 SL |
1723 | } |
1724 | ||
1725 | preempt_enable(); | |
cc81e948 JH |
1726 | done: |
1727 | /* Rollback PC only if emulation was unsuccessful */ | |
1728 | if (er == EMULATE_FAIL) | |
1729 | vcpu->arch.pc = curr_pc; | |
e685c689 | 1730 | |
d116e812 | 1731 | dont_update_pc: |
cc81e948 JH |
1732 | /* |
1733 | * This is for exceptions whose emulation updates the PC, so do not | |
1734 | * overwrite the PC under any circumstances | |
1735 | */ | |
1736 | ||
e685c689 SL |
1737 | return er; |
1738 | } | |
1739 | ||
31cf7498 | 1740 | enum emulation_result kvm_mips_emulate_inst(u32 cause, u32 *opc, |
d116e812 DCZ |
1741 | struct kvm_run *run, |
1742 | struct kvm_vcpu *vcpu) | |
e685c689 | 1743 | { |
258f3a2e | 1744 | union mips_instruction inst; |
e685c689 | 1745 | enum emulation_result er = EMULATE_DONE; |
e685c689 | 1746 | |
d116e812 DCZ |
1747 | /* Fetch the instruction. */ |
1748 | if (cause & CAUSEF_BD) | |
e685c689 | 1749 | opc += 1; |
e685c689 | 1750 | |
258f3a2e | 1751 | inst.word = kvm_get_inst(opc, vcpu); |
e685c689 | 1752 | |
258f3a2e | 1753 | switch (inst.r_format.opcode) { |
e685c689 SL |
1754 | case cop0_op: |
1755 | er = kvm_mips_emulate_CP0(inst, opc, cause, run, vcpu); | |
1756 | break; | |
1757 | case sb_op: | |
1758 | case sh_op: | |
1759 | case sw_op: | |
1760 | er = kvm_mips_emulate_store(inst, cause, run, vcpu); | |
1761 | break; | |
1762 | case lb_op: | |
1763 | case lbu_op: | |
1764 | case lhu_op: | |
1765 | case lh_op: | |
1766 | case lw_op: | |
1767 | er = kvm_mips_emulate_load(inst, cause, run, vcpu); | |
1768 | break; | |
1769 | ||
5cc4aafc | 1770 | #ifndef CONFIG_CPU_MIPSR6 |
e685c689 SL |
1771 | case cache_op: |
1772 | ++vcpu->stat.cache_exits; | |
1e09e86a | 1773 | trace_kvm_exit(vcpu, KVM_TRACE_EXIT_CACHE); |
e685c689 SL |
1774 | er = kvm_mips_emulate_cache(inst, opc, cause, run, vcpu); |
1775 | break; | |
5cc4aafc JH |
1776 | #else |
1777 | case spec3_op: | |
1778 | switch (inst.spec3_format.func) { | |
1779 | case cache6_op: | |
1780 | ++vcpu->stat.cache_exits; | |
1781 | trace_kvm_exit(vcpu, KVM_TRACE_EXIT_CACHE); | |
1782 | er = kvm_mips_emulate_cache(inst, opc, cause, run, | |
1783 | vcpu); | |
1784 | break; | |
1785 | default: | |
1786 | goto unknown; | |
1787 | }; | |
1788 | break; | |
1789 | unknown: | |
1790 | #endif | |
e685c689 SL |
1791 | |
1792 | default: | |
6ad78a5c | 1793 | kvm_err("Instruction emulation not supported (%p/%#x)\n", opc, |
258f3a2e | 1794 | inst.word); |
e685c689 SL |
1795 | kvm_arch_vcpu_dump_regs(vcpu); |
1796 | er = EMULATE_FAIL; | |
1797 | break; | |
1798 | } | |
1799 | ||
1800 | return er; | |
1801 | } | |
1802 | ||
31cf7498 | 1803 | enum emulation_result kvm_mips_emulate_syscall(u32 cause, |
bdb7ed86 | 1804 | u32 *opc, |
d116e812 DCZ |
1805 | struct kvm_run *run, |
1806 | struct kvm_vcpu *vcpu) | |
e685c689 SL |
1807 | { |
1808 | struct mips_coproc *cop0 = vcpu->arch.cop0; | |
1809 | struct kvm_vcpu_arch *arch = &vcpu->arch; | |
1810 | enum emulation_result er = EMULATE_DONE; | |
1811 | ||
1812 | if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) { | |
1813 | /* save old pc */ | |
1814 | kvm_write_c0_guest_epc(cop0, arch->pc); | |
1815 | kvm_set_c0_guest_status(cop0, ST0_EXL); | |
1816 | ||
1817 | if (cause & CAUSEF_BD) | |
1818 | kvm_set_c0_guest_cause(cop0, CAUSEF_BD); | |
1819 | else | |
1820 | kvm_clear_c0_guest_cause(cop0, CAUSEF_BD); | |
1821 | ||
1822 | kvm_debug("Delivering SYSCALL @ pc %#lx\n", arch->pc); | |
1823 | ||
1824 | kvm_change_c0_guest_cause(cop0, (0xff), | |
16d100db | 1825 | (EXCCODE_SYS << CAUSEB_EXCCODE)); |
e685c689 SL |
1826 | |
1827 | /* Set PC to the exception entry point */ | |
1828 | arch->pc = KVM_GUEST_KSEG0 + 0x180; | |
1829 | ||
1830 | } else { | |
6ad78a5c | 1831 | kvm_err("Trying to deliver SYSCALL when EXL is already set\n"); |
e685c689 SL |
1832 | er = EMULATE_FAIL; |
1833 | } | |
1834 | ||
1835 | return er; | |
1836 | } | |
1837 | ||
31cf7498 | 1838 | enum emulation_result kvm_mips_emulate_tlbmiss_ld(u32 cause, |
bdb7ed86 | 1839 | u32 *opc, |
d116e812 DCZ |
1840 | struct kvm_run *run, |
1841 | struct kvm_vcpu *vcpu) | |
e685c689 SL |
1842 | { |
1843 | struct mips_coproc *cop0 = vcpu->arch.cop0; | |
1844 | struct kvm_vcpu_arch *arch = &vcpu->arch; | |
e685c689 | 1845 | unsigned long entryhi = (vcpu->arch. host_cp0_badvaddr & VPN2_MASK) | |
ca64c2be | 1846 | (kvm_read_c0_guest_entryhi(cop0) & KVM_ENTRYHI_ASID); |
e685c689 SL |
1847 | |
1848 | if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) { | |
1849 | /* save old pc */ | |
1850 | kvm_write_c0_guest_epc(cop0, arch->pc); | |
1851 | kvm_set_c0_guest_status(cop0, ST0_EXL); | |
1852 | ||
1853 | if (cause & CAUSEF_BD) | |
1854 | kvm_set_c0_guest_cause(cop0, CAUSEF_BD); | |
1855 | else | |
1856 | kvm_clear_c0_guest_cause(cop0, CAUSEF_BD); | |
1857 | ||
1858 | kvm_debug("[EXL == 0] delivering TLB MISS @ pc %#lx\n", | |
1859 | arch->pc); | |
1860 | ||
1861 | /* set pc to the exception entry point */ | |
1862 | arch->pc = KVM_GUEST_KSEG0 + 0x0; | |
1863 | ||
1864 | } else { | |
1865 | kvm_debug("[EXL == 1] delivering TLB MISS @ pc %#lx\n", | |
1866 | arch->pc); | |
1867 | ||
1868 | arch->pc = KVM_GUEST_KSEG0 + 0x180; | |
1869 | } | |
1870 | ||
1871 | kvm_change_c0_guest_cause(cop0, (0xff), | |
16d100db | 1872 | (EXCCODE_TLBL << CAUSEB_EXCCODE)); |
e685c689 SL |
1873 | |
1874 | /* setup badvaddr, context and entryhi registers for the guest */ | |
1875 | kvm_write_c0_guest_badvaddr(cop0, vcpu->arch.host_cp0_badvaddr); | |
1876 | /* XXXKYMA: is the context register used by linux??? */ | |
1877 | kvm_write_c0_guest_entryhi(cop0, entryhi); | |
1878 | /* Blow away the shadow host TLBs */ | |
1879 | kvm_mips_flush_host_tlb(1); | |
1880 | ||
d98403a5 | 1881 | return EMULATE_DONE; |
e685c689 SL |
1882 | } |
1883 | ||
31cf7498 | 1884 | enum emulation_result kvm_mips_emulate_tlbinv_ld(u32 cause, |
bdb7ed86 | 1885 | u32 *opc, |
d116e812 DCZ |
1886 | struct kvm_run *run, |
1887 | struct kvm_vcpu *vcpu) | |
e685c689 SL |
1888 | { |
1889 | struct mips_coproc *cop0 = vcpu->arch.cop0; | |
1890 | struct kvm_vcpu_arch *arch = &vcpu->arch; | |
e685c689 SL |
1891 | unsigned long entryhi = |
1892 | (vcpu->arch.host_cp0_badvaddr & VPN2_MASK) | | |
ca64c2be | 1893 | (kvm_read_c0_guest_entryhi(cop0) & KVM_ENTRYHI_ASID); |
e685c689 SL |
1894 | |
1895 | if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) { | |
1896 | /* save old pc */ | |
1897 | kvm_write_c0_guest_epc(cop0, arch->pc); | |
1898 | kvm_set_c0_guest_status(cop0, ST0_EXL); | |
1899 | ||
1900 | if (cause & CAUSEF_BD) | |
1901 | kvm_set_c0_guest_cause(cop0, CAUSEF_BD); | |
1902 | else | |
1903 | kvm_clear_c0_guest_cause(cop0, CAUSEF_BD); | |
1904 | ||
1905 | kvm_debug("[EXL == 0] delivering TLB INV @ pc %#lx\n", | |
1906 | arch->pc); | |
1907 | ||
1908 | /* set pc to the exception entry point */ | |
1909 | arch->pc = KVM_GUEST_KSEG0 + 0x180; | |
1910 | ||
1911 | } else { | |
1912 | kvm_debug("[EXL == 1] delivering TLB MISS @ pc %#lx\n", | |
1913 | arch->pc); | |
1914 | arch->pc = KVM_GUEST_KSEG0 + 0x180; | |
1915 | } | |
1916 | ||
1917 | kvm_change_c0_guest_cause(cop0, (0xff), | |
16d100db | 1918 | (EXCCODE_TLBL << CAUSEB_EXCCODE)); |
e685c689 SL |
1919 | |
1920 | /* setup badvaddr, context and entryhi registers for the guest */ | |
1921 | kvm_write_c0_guest_badvaddr(cop0, vcpu->arch.host_cp0_badvaddr); | |
1922 | /* XXXKYMA: is the context register used by linux??? */ | |
1923 | kvm_write_c0_guest_entryhi(cop0, entryhi); | |
1924 | /* Blow away the shadow host TLBs */ | |
1925 | kvm_mips_flush_host_tlb(1); | |
1926 | ||
d98403a5 | 1927 | return EMULATE_DONE; |
e685c689 SL |
1928 | } |
1929 | ||
31cf7498 | 1930 | enum emulation_result kvm_mips_emulate_tlbmiss_st(u32 cause, |
bdb7ed86 | 1931 | u32 *opc, |
d116e812 DCZ |
1932 | struct kvm_run *run, |
1933 | struct kvm_vcpu *vcpu) | |
e685c689 SL |
1934 | { |
1935 | struct mips_coproc *cop0 = vcpu->arch.cop0; | |
1936 | struct kvm_vcpu_arch *arch = &vcpu->arch; | |
e685c689 | 1937 | unsigned long entryhi = (vcpu->arch.host_cp0_badvaddr & VPN2_MASK) | |
ca64c2be | 1938 | (kvm_read_c0_guest_entryhi(cop0) & KVM_ENTRYHI_ASID); |
e685c689 SL |
1939 | |
1940 | if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) { | |
1941 | /* save old pc */ | |
1942 | kvm_write_c0_guest_epc(cop0, arch->pc); | |
1943 | kvm_set_c0_guest_status(cop0, ST0_EXL); | |
1944 | ||
1945 | if (cause & CAUSEF_BD) | |
1946 | kvm_set_c0_guest_cause(cop0, CAUSEF_BD); | |
1947 | else | |
1948 | kvm_clear_c0_guest_cause(cop0, CAUSEF_BD); | |
1949 | ||
1950 | kvm_debug("[EXL == 0] Delivering TLB MISS @ pc %#lx\n", | |
1951 | arch->pc); | |
1952 | ||
1953 | /* Set PC to the exception entry point */ | |
1954 | arch->pc = KVM_GUEST_KSEG0 + 0x0; | |
1955 | } else { | |
1956 | kvm_debug("[EXL == 1] Delivering TLB MISS @ pc %#lx\n", | |
1957 | arch->pc); | |
1958 | arch->pc = KVM_GUEST_KSEG0 + 0x180; | |
1959 | } | |
1960 | ||
1961 | kvm_change_c0_guest_cause(cop0, (0xff), | |
16d100db | 1962 | (EXCCODE_TLBS << CAUSEB_EXCCODE)); |
e685c689 SL |
1963 | |
1964 | /* setup badvaddr, context and entryhi registers for the guest */ | |
1965 | kvm_write_c0_guest_badvaddr(cop0, vcpu->arch.host_cp0_badvaddr); | |
1966 | /* XXXKYMA: is the context register used by linux??? */ | |
1967 | kvm_write_c0_guest_entryhi(cop0, entryhi); | |
1968 | /* Blow away the shadow host TLBs */ | |
1969 | kvm_mips_flush_host_tlb(1); | |
1970 | ||
d98403a5 | 1971 | return EMULATE_DONE; |
e685c689 SL |
1972 | } |
1973 | ||
31cf7498 | 1974 | enum emulation_result kvm_mips_emulate_tlbinv_st(u32 cause, |
bdb7ed86 | 1975 | u32 *opc, |
d116e812 DCZ |
1976 | struct kvm_run *run, |
1977 | struct kvm_vcpu *vcpu) | |
e685c689 SL |
1978 | { |
1979 | struct mips_coproc *cop0 = vcpu->arch.cop0; | |
1980 | struct kvm_vcpu_arch *arch = &vcpu->arch; | |
e685c689 | 1981 | unsigned long entryhi = (vcpu->arch.host_cp0_badvaddr & VPN2_MASK) | |
ca64c2be | 1982 | (kvm_read_c0_guest_entryhi(cop0) & KVM_ENTRYHI_ASID); |
e685c689 SL |
1983 | |
1984 | if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) { | |
1985 | /* save old pc */ | |
1986 | kvm_write_c0_guest_epc(cop0, arch->pc); | |
1987 | kvm_set_c0_guest_status(cop0, ST0_EXL); | |
1988 | ||
1989 | if (cause & CAUSEF_BD) | |
1990 | kvm_set_c0_guest_cause(cop0, CAUSEF_BD); | |
1991 | else | |
1992 | kvm_clear_c0_guest_cause(cop0, CAUSEF_BD); | |
1993 | ||
1994 | kvm_debug("[EXL == 0] Delivering TLB MISS @ pc %#lx\n", | |
1995 | arch->pc); | |
1996 | ||
1997 | /* Set PC to the exception entry point */ | |
1998 | arch->pc = KVM_GUEST_KSEG0 + 0x180; | |
1999 | } else { | |
2000 | kvm_debug("[EXL == 1] Delivering TLB MISS @ pc %#lx\n", | |
2001 | arch->pc); | |
2002 | arch->pc = KVM_GUEST_KSEG0 + 0x180; | |
2003 | } | |
2004 | ||
2005 | kvm_change_c0_guest_cause(cop0, (0xff), | |
16d100db | 2006 | (EXCCODE_TLBS << CAUSEB_EXCCODE)); |
e685c689 SL |
2007 | |
2008 | /* setup badvaddr, context and entryhi registers for the guest */ | |
2009 | kvm_write_c0_guest_badvaddr(cop0, vcpu->arch.host_cp0_badvaddr); | |
2010 | /* XXXKYMA: is the context register used by linux??? */ | |
2011 | kvm_write_c0_guest_entryhi(cop0, entryhi); | |
2012 | /* Blow away the shadow host TLBs */ | |
2013 | kvm_mips_flush_host_tlb(1); | |
2014 | ||
d98403a5 | 2015 | return EMULATE_DONE; |
e685c689 SL |
2016 | } |
2017 | ||
2018 | /* TLBMOD: store into address matching TLB with Dirty bit off */ | |
31cf7498 | 2019 | enum emulation_result kvm_mips_handle_tlbmod(u32 cause, u32 *opc, |
d116e812 DCZ |
2020 | struct kvm_run *run, |
2021 | struct kvm_vcpu *vcpu) | |
e685c689 SL |
2022 | { |
2023 | enum emulation_result er = EMULATE_DONE; | |
e685c689 | 2024 | #ifdef DEBUG |
3d654833 JH |
2025 | struct mips_coproc *cop0 = vcpu->arch.cop0; |
2026 | unsigned long entryhi = (vcpu->arch.host_cp0_badvaddr & VPN2_MASK) | | |
ca64c2be | 2027 | (kvm_read_c0_guest_entryhi(cop0) & KVM_ENTRYHI_ASID); |
3d654833 JH |
2028 | int index; |
2029 | ||
d116e812 | 2030 | /* If address not in the guest TLB, then we are in trouble */ |
e685c689 SL |
2031 | index = kvm_mips_guest_tlb_lookup(vcpu, entryhi); |
2032 | if (index < 0) { | |
2033 | /* XXXKYMA Invalidate and retry */ | |
2034 | kvm_mips_host_tlb_inv(vcpu, vcpu->arch.host_cp0_badvaddr); | |
2035 | kvm_err("%s: host got TLBMOD for %#lx but entry not present in Guest TLB\n", | |
2036 | __func__, entryhi); | |
2037 | kvm_mips_dump_guest_tlbs(vcpu); | |
2038 | kvm_mips_dump_host_tlbs(); | |
2039 | return EMULATE_FAIL; | |
2040 | } | |
2041 | #endif | |
2042 | ||
2043 | er = kvm_mips_emulate_tlbmod(cause, opc, run, vcpu); | |
2044 | return er; | |
2045 | } | |
2046 | ||
31cf7498 | 2047 | enum emulation_result kvm_mips_emulate_tlbmod(u32 cause, |
bdb7ed86 | 2048 | u32 *opc, |
d116e812 DCZ |
2049 | struct kvm_run *run, |
2050 | struct kvm_vcpu *vcpu) | |
e685c689 SL |
2051 | { |
2052 | struct mips_coproc *cop0 = vcpu->arch.cop0; | |
2053 | unsigned long entryhi = (vcpu->arch.host_cp0_badvaddr & VPN2_MASK) | | |
ca64c2be | 2054 | (kvm_read_c0_guest_entryhi(cop0) & KVM_ENTRYHI_ASID); |
e685c689 | 2055 | struct kvm_vcpu_arch *arch = &vcpu->arch; |
e685c689 SL |
2056 | |
2057 | if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) { | |
2058 | /* save old pc */ | |
2059 | kvm_write_c0_guest_epc(cop0, arch->pc); | |
2060 | kvm_set_c0_guest_status(cop0, ST0_EXL); | |
2061 | ||
2062 | if (cause & CAUSEF_BD) | |
2063 | kvm_set_c0_guest_cause(cop0, CAUSEF_BD); | |
2064 | else | |
2065 | kvm_clear_c0_guest_cause(cop0, CAUSEF_BD); | |
2066 | ||
2067 | kvm_debug("[EXL == 0] Delivering TLB MOD @ pc %#lx\n", | |
2068 | arch->pc); | |
2069 | ||
2070 | arch->pc = KVM_GUEST_KSEG0 + 0x180; | |
2071 | } else { | |
2072 | kvm_debug("[EXL == 1] Delivering TLB MOD @ pc %#lx\n", | |
2073 | arch->pc); | |
2074 | arch->pc = KVM_GUEST_KSEG0 + 0x180; | |
2075 | } | |
2076 | ||
16d100db JH |
2077 | kvm_change_c0_guest_cause(cop0, (0xff), |
2078 | (EXCCODE_MOD << CAUSEB_EXCCODE)); | |
e685c689 SL |
2079 | |
2080 | /* setup badvaddr, context and entryhi registers for the guest */ | |
2081 | kvm_write_c0_guest_badvaddr(cop0, vcpu->arch.host_cp0_badvaddr); | |
2082 | /* XXXKYMA: is the context register used by linux??? */ | |
2083 | kvm_write_c0_guest_entryhi(cop0, entryhi); | |
2084 | /* Blow away the shadow host TLBs */ | |
2085 | kvm_mips_flush_host_tlb(1); | |
2086 | ||
d98403a5 | 2087 | return EMULATE_DONE; |
e685c689 SL |
2088 | } |
2089 | ||
31cf7498 | 2090 | enum emulation_result kvm_mips_emulate_fpu_exc(u32 cause, |
bdb7ed86 | 2091 | u32 *opc, |
d116e812 DCZ |
2092 | struct kvm_run *run, |
2093 | struct kvm_vcpu *vcpu) | |
e685c689 SL |
2094 | { |
2095 | struct mips_coproc *cop0 = vcpu->arch.cop0; | |
2096 | struct kvm_vcpu_arch *arch = &vcpu->arch; | |
e685c689 SL |
2097 | |
2098 | if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) { | |
2099 | /* save old pc */ | |
2100 | kvm_write_c0_guest_epc(cop0, arch->pc); | |
2101 | kvm_set_c0_guest_status(cop0, ST0_EXL); | |
2102 | ||
2103 | if (cause & CAUSEF_BD) | |
2104 | kvm_set_c0_guest_cause(cop0, CAUSEF_BD); | |
2105 | else | |
2106 | kvm_clear_c0_guest_cause(cop0, CAUSEF_BD); | |
2107 | ||
2108 | } | |
2109 | ||
2110 | arch->pc = KVM_GUEST_KSEG0 + 0x180; | |
2111 | ||
2112 | kvm_change_c0_guest_cause(cop0, (0xff), | |
16d100db | 2113 | (EXCCODE_CPU << CAUSEB_EXCCODE)); |
e685c689 SL |
2114 | kvm_change_c0_guest_cause(cop0, (CAUSEF_CE), (0x1 << CAUSEB_CE)); |
2115 | ||
d98403a5 | 2116 | return EMULATE_DONE; |
e685c689 SL |
2117 | } |
2118 | ||
31cf7498 | 2119 | enum emulation_result kvm_mips_emulate_ri_exc(u32 cause, |
bdb7ed86 | 2120 | u32 *opc, |
d116e812 DCZ |
2121 | struct kvm_run *run, |
2122 | struct kvm_vcpu *vcpu) | |
e685c689 SL |
2123 | { |
2124 | struct mips_coproc *cop0 = vcpu->arch.cop0; | |
2125 | struct kvm_vcpu_arch *arch = &vcpu->arch; | |
2126 | enum emulation_result er = EMULATE_DONE; | |
2127 | ||
2128 | if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) { | |
2129 | /* save old pc */ | |
2130 | kvm_write_c0_guest_epc(cop0, arch->pc); | |
2131 | kvm_set_c0_guest_status(cop0, ST0_EXL); | |
2132 | ||
2133 | if (cause & CAUSEF_BD) | |
2134 | kvm_set_c0_guest_cause(cop0, CAUSEF_BD); | |
2135 | else | |
2136 | kvm_clear_c0_guest_cause(cop0, CAUSEF_BD); | |
2137 | ||
2138 | kvm_debug("Delivering RI @ pc %#lx\n", arch->pc); | |
2139 | ||
2140 | kvm_change_c0_guest_cause(cop0, (0xff), | |
16d100db | 2141 | (EXCCODE_RI << CAUSEB_EXCCODE)); |
e685c689 SL |
2142 | |
2143 | /* Set PC to the exception entry point */ | |
2144 | arch->pc = KVM_GUEST_KSEG0 + 0x180; | |
2145 | ||
2146 | } else { | |
2147 | kvm_err("Trying to deliver RI when EXL is already set\n"); | |
2148 | er = EMULATE_FAIL; | |
2149 | } | |
2150 | ||
2151 | return er; | |
2152 | } | |
2153 | ||
31cf7498 | 2154 | enum emulation_result kvm_mips_emulate_bp_exc(u32 cause, |
bdb7ed86 | 2155 | u32 *opc, |
d116e812 DCZ |
2156 | struct kvm_run *run, |
2157 | struct kvm_vcpu *vcpu) | |
e685c689 SL |
2158 | { |
2159 | struct mips_coproc *cop0 = vcpu->arch.cop0; | |
2160 | struct kvm_vcpu_arch *arch = &vcpu->arch; | |
2161 | enum emulation_result er = EMULATE_DONE; | |
2162 | ||
2163 | if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) { | |
2164 | /* save old pc */ | |
2165 | kvm_write_c0_guest_epc(cop0, arch->pc); | |
2166 | kvm_set_c0_guest_status(cop0, ST0_EXL); | |
2167 | ||
2168 | if (cause & CAUSEF_BD) | |
2169 | kvm_set_c0_guest_cause(cop0, CAUSEF_BD); | |
2170 | else | |
2171 | kvm_clear_c0_guest_cause(cop0, CAUSEF_BD); | |
2172 | ||
2173 | kvm_debug("Delivering BP @ pc %#lx\n", arch->pc); | |
2174 | ||
2175 | kvm_change_c0_guest_cause(cop0, (0xff), | |
16d100db | 2176 | (EXCCODE_BP << CAUSEB_EXCCODE)); |
e685c689 SL |
2177 | |
2178 | /* Set PC to the exception entry point */ | |
2179 | arch->pc = KVM_GUEST_KSEG0 + 0x180; | |
2180 | ||
2181 | } else { | |
6ad78a5c | 2182 | kvm_err("Trying to deliver BP when EXL is already set\n"); |
e685c689 SL |
2183 | er = EMULATE_FAIL; |
2184 | } | |
2185 | ||
2186 | return er; | |
2187 | } | |
2188 | ||
31cf7498 | 2189 | enum emulation_result kvm_mips_emulate_trap_exc(u32 cause, |
bdb7ed86 | 2190 | u32 *opc, |
0a560427 JH |
2191 | struct kvm_run *run, |
2192 | struct kvm_vcpu *vcpu) | |
2193 | { | |
2194 | struct mips_coproc *cop0 = vcpu->arch.cop0; | |
2195 | struct kvm_vcpu_arch *arch = &vcpu->arch; | |
2196 | enum emulation_result er = EMULATE_DONE; | |
2197 | ||
2198 | if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) { | |
2199 | /* save old pc */ | |
2200 | kvm_write_c0_guest_epc(cop0, arch->pc); | |
2201 | kvm_set_c0_guest_status(cop0, ST0_EXL); | |
2202 | ||
2203 | if (cause & CAUSEF_BD) | |
2204 | kvm_set_c0_guest_cause(cop0, CAUSEF_BD); | |
2205 | else | |
2206 | kvm_clear_c0_guest_cause(cop0, CAUSEF_BD); | |
2207 | ||
2208 | kvm_debug("Delivering TRAP @ pc %#lx\n", arch->pc); | |
2209 | ||
2210 | kvm_change_c0_guest_cause(cop0, (0xff), | |
16d100db | 2211 | (EXCCODE_TR << CAUSEB_EXCCODE)); |
0a560427 JH |
2212 | |
2213 | /* Set PC to the exception entry point */ | |
2214 | arch->pc = KVM_GUEST_KSEG0 + 0x180; | |
2215 | ||
2216 | } else { | |
2217 | kvm_err("Trying to deliver TRAP when EXL is already set\n"); | |
2218 | er = EMULATE_FAIL; | |
2219 | } | |
2220 | ||
2221 | return er; | |
2222 | } | |
2223 | ||
31cf7498 | 2224 | enum emulation_result kvm_mips_emulate_msafpe_exc(u32 cause, |
bdb7ed86 | 2225 | u32 *opc, |
c2537ed9 JH |
2226 | struct kvm_run *run, |
2227 | struct kvm_vcpu *vcpu) | |
2228 | { | |
2229 | struct mips_coproc *cop0 = vcpu->arch.cop0; | |
2230 | struct kvm_vcpu_arch *arch = &vcpu->arch; | |
2231 | enum emulation_result er = EMULATE_DONE; | |
2232 | ||
2233 | if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) { | |
2234 | /* save old pc */ | |
2235 | kvm_write_c0_guest_epc(cop0, arch->pc); | |
2236 | kvm_set_c0_guest_status(cop0, ST0_EXL); | |
2237 | ||
2238 | if (cause & CAUSEF_BD) | |
2239 | kvm_set_c0_guest_cause(cop0, CAUSEF_BD); | |
2240 | else | |
2241 | kvm_clear_c0_guest_cause(cop0, CAUSEF_BD); | |
2242 | ||
2243 | kvm_debug("Delivering MSAFPE @ pc %#lx\n", arch->pc); | |
2244 | ||
2245 | kvm_change_c0_guest_cause(cop0, (0xff), | |
16d100db | 2246 | (EXCCODE_MSAFPE << CAUSEB_EXCCODE)); |
c2537ed9 JH |
2247 | |
2248 | /* Set PC to the exception entry point */ | |
2249 | arch->pc = KVM_GUEST_KSEG0 + 0x180; | |
2250 | ||
2251 | } else { | |
2252 | kvm_err("Trying to deliver MSAFPE when EXL is already set\n"); | |
2253 | er = EMULATE_FAIL; | |
2254 | } | |
2255 | ||
2256 | return er; | |
2257 | } | |
2258 | ||
31cf7498 | 2259 | enum emulation_result kvm_mips_emulate_fpe_exc(u32 cause, |
bdb7ed86 | 2260 | u32 *opc, |
1c0cd66a JH |
2261 | struct kvm_run *run, |
2262 | struct kvm_vcpu *vcpu) | |
2263 | { | |
2264 | struct mips_coproc *cop0 = vcpu->arch.cop0; | |
2265 | struct kvm_vcpu_arch *arch = &vcpu->arch; | |
2266 | enum emulation_result er = EMULATE_DONE; | |
2267 | ||
2268 | if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) { | |
2269 | /* save old pc */ | |
2270 | kvm_write_c0_guest_epc(cop0, arch->pc); | |
2271 | kvm_set_c0_guest_status(cop0, ST0_EXL); | |
2272 | ||
2273 | if (cause & CAUSEF_BD) | |
2274 | kvm_set_c0_guest_cause(cop0, CAUSEF_BD); | |
2275 | else | |
2276 | kvm_clear_c0_guest_cause(cop0, CAUSEF_BD); | |
2277 | ||
2278 | kvm_debug("Delivering FPE @ pc %#lx\n", arch->pc); | |
2279 | ||
2280 | kvm_change_c0_guest_cause(cop0, (0xff), | |
16d100db | 2281 | (EXCCODE_FPE << CAUSEB_EXCCODE)); |
1c0cd66a JH |
2282 | |
2283 | /* Set PC to the exception entry point */ | |
2284 | arch->pc = KVM_GUEST_KSEG0 + 0x180; | |
2285 | ||
2286 | } else { | |
2287 | kvm_err("Trying to deliver FPE when EXL is already set\n"); | |
2288 | er = EMULATE_FAIL; | |
2289 | } | |
2290 | ||
2291 | return er; | |
2292 | } | |
2293 | ||
31cf7498 | 2294 | enum emulation_result kvm_mips_emulate_msadis_exc(u32 cause, |
bdb7ed86 | 2295 | u32 *opc, |
c2537ed9 JH |
2296 | struct kvm_run *run, |
2297 | struct kvm_vcpu *vcpu) | |
2298 | { | |
2299 | struct mips_coproc *cop0 = vcpu->arch.cop0; | |
2300 | struct kvm_vcpu_arch *arch = &vcpu->arch; | |
2301 | enum emulation_result er = EMULATE_DONE; | |
2302 | ||
2303 | if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) { | |
2304 | /* save old pc */ | |
2305 | kvm_write_c0_guest_epc(cop0, arch->pc); | |
2306 | kvm_set_c0_guest_status(cop0, ST0_EXL); | |
2307 | ||
2308 | if (cause & CAUSEF_BD) | |
2309 | kvm_set_c0_guest_cause(cop0, CAUSEF_BD); | |
2310 | else | |
2311 | kvm_clear_c0_guest_cause(cop0, CAUSEF_BD); | |
2312 | ||
2313 | kvm_debug("Delivering MSADIS @ pc %#lx\n", arch->pc); | |
2314 | ||
2315 | kvm_change_c0_guest_cause(cop0, (0xff), | |
16d100db | 2316 | (EXCCODE_MSADIS << CAUSEB_EXCCODE)); |
c2537ed9 JH |
2317 | |
2318 | /* Set PC to the exception entry point */ | |
2319 | arch->pc = KVM_GUEST_KSEG0 + 0x180; | |
2320 | ||
2321 | } else { | |
2322 | kvm_err("Trying to deliver MSADIS when EXL is already set\n"); | |
2323 | er = EMULATE_FAIL; | |
2324 | } | |
2325 | ||
2326 | return er; | |
2327 | } | |
2328 | ||
31cf7498 | 2329 | enum emulation_result kvm_mips_handle_ri(u32 cause, u32 *opc, |
d116e812 DCZ |
2330 | struct kvm_run *run, |
2331 | struct kvm_vcpu *vcpu) | |
e685c689 SL |
2332 | { |
2333 | struct mips_coproc *cop0 = vcpu->arch.cop0; | |
2334 | struct kvm_vcpu_arch *arch = &vcpu->arch; | |
2335 | enum emulation_result er = EMULATE_DONE; | |
2336 | unsigned long curr_pc; | |
258f3a2e | 2337 | union mips_instruction inst; |
e685c689 SL |
2338 | |
2339 | /* | |
2340 | * Update PC and hold onto current PC in case there is | |
2341 | * an error and we want to rollback the PC | |
2342 | */ | |
2343 | curr_pc = vcpu->arch.pc; | |
2344 | er = update_pc(vcpu, cause); | |
2345 | if (er == EMULATE_FAIL) | |
2346 | return er; | |
2347 | ||
d116e812 | 2348 | /* Fetch the instruction. */ |
e685c689 SL |
2349 | if (cause & CAUSEF_BD) |
2350 | opc += 1; | |
2351 | ||
258f3a2e | 2352 | inst.word = kvm_get_inst(opc, vcpu); |
e685c689 | 2353 | |
258f3a2e | 2354 | if (inst.word == KVM_INVALID_INST) { |
6ad78a5c | 2355 | kvm_err("%s: Cannot get inst @ %p\n", __func__, opc); |
e685c689 SL |
2356 | return EMULATE_FAIL; |
2357 | } | |
2358 | ||
258f3a2e JH |
2359 | if (inst.r_format.opcode == spec3_op && |
2360 | inst.r_format.func == rdhwr_op) { | |
26f4f3b5 | 2361 | int usermode = !KVM_GUEST_KERNEL_MODE(vcpu); |
258f3a2e JH |
2362 | int rd = inst.r_format.rd; |
2363 | int rt = inst.r_format.rt; | |
2364 | int sel = inst.r_format.re & 0x7; | |
6398da13 | 2365 | |
26f4f3b5 JH |
2366 | /* If usermode, check RDHWR rd is allowed by guest HWREna */ |
2367 | if (usermode && !(kvm_read_c0_guest_hwrena(cop0) & BIT(rd))) { | |
2368 | kvm_debug("RDHWR %#x disallowed by HWREna @ %p\n", | |
2369 | rd, opc); | |
2370 | goto emulate_ri; | |
2371 | } | |
e685c689 | 2372 | switch (rd) { |
aff565aa | 2373 | case MIPS_HWR_CPUNUM: /* CPU number */ |
cf1fb0f2 | 2374 | arch->gprs[rt] = vcpu->vcpu_id; |
e685c689 | 2375 | break; |
aff565aa | 2376 | case MIPS_HWR_SYNCISTEP: /* SYNCI length */ |
e685c689 SL |
2377 | arch->gprs[rt] = min(current_cpu_data.dcache.linesz, |
2378 | current_cpu_data.icache.linesz); | |
2379 | break; | |
aff565aa | 2380 | case MIPS_HWR_CC: /* Read count register */ |
e30492bb | 2381 | arch->gprs[rt] = kvm_mips_read_count(vcpu); |
e685c689 | 2382 | break; |
aff565aa | 2383 | case MIPS_HWR_CCRES: /* Count register resolution */ |
e685c689 SL |
2384 | switch (current_cpu_data.cputype) { |
2385 | case CPU_20KC: | |
2386 | case CPU_25KF: | |
2387 | arch->gprs[rt] = 1; | |
2388 | break; | |
2389 | default: | |
2390 | arch->gprs[rt] = 2; | |
2391 | } | |
2392 | break; | |
aff565aa | 2393 | case MIPS_HWR_ULR: /* Read UserLocal register */ |
e685c689 | 2394 | arch->gprs[rt] = kvm_read_c0_guest_userlocal(cop0); |
e685c689 SL |
2395 | break; |
2396 | ||
2397 | default: | |
15505679 | 2398 | kvm_debug("RDHWR %#x not supported @ %p\n", rd, opc); |
26f4f3b5 | 2399 | goto emulate_ri; |
e685c689 | 2400 | } |
6398da13 JH |
2401 | |
2402 | trace_kvm_hwr(vcpu, KVM_TRACE_RDHWR, KVM_TRACE_HWR(rd, sel), | |
2403 | vcpu->arch.gprs[rt]); | |
e685c689 | 2404 | } else { |
258f3a2e JH |
2405 | kvm_debug("Emulate RI not supported @ %p: %#x\n", |
2406 | opc, inst.word); | |
26f4f3b5 | 2407 | goto emulate_ri; |
e685c689 SL |
2408 | } |
2409 | ||
26f4f3b5 JH |
2410 | return EMULATE_DONE; |
2411 | ||
2412 | emulate_ri: | |
e685c689 | 2413 | /* |
26f4f3b5 JH |
2414 | * Rollback PC (if in branch delay slot then the PC already points to |
2415 | * branch target), and pass the RI exception to the guest OS. | |
e685c689 | 2416 | */ |
26f4f3b5 JH |
2417 | vcpu->arch.pc = curr_pc; |
2418 | return kvm_mips_emulate_ri_exc(cause, opc, run, vcpu); | |
e685c689 SL |
2419 | } |
2420 | ||
d116e812 DCZ |
2421 | enum emulation_result kvm_mips_complete_mmio_load(struct kvm_vcpu *vcpu, |
2422 | struct kvm_run *run) | |
e685c689 SL |
2423 | { |
2424 | unsigned long *gpr = &vcpu->arch.gprs[vcpu->arch.io_gpr]; | |
2425 | enum emulation_result er = EMULATE_DONE; | |
e685c689 SL |
2426 | |
2427 | if (run->mmio.len > sizeof(*gpr)) { | |
6ad78a5c | 2428 | kvm_err("Bad MMIO length: %d", run->mmio.len); |
e685c689 SL |
2429 | er = EMULATE_FAIL; |
2430 | goto done; | |
2431 | } | |
2432 | ||
e685c689 SL |
2433 | er = update_pc(vcpu, vcpu->arch.pending_load_cause); |
2434 | if (er == EMULATE_FAIL) | |
2435 | return er; | |
2436 | ||
2437 | switch (run->mmio.len) { | |
2438 | case 4: | |
8cffd197 | 2439 | *gpr = *(s32 *) run->mmio.data; |
e685c689 SL |
2440 | break; |
2441 | ||
2442 | case 2: | |
2443 | if (vcpu->mmio_needed == 2) | |
8cffd197 | 2444 | *gpr = *(s16 *) run->mmio.data; |
e685c689 | 2445 | else |
8cffd197 | 2446 | *gpr = *(u16 *)run->mmio.data; |
e685c689 SL |
2447 | |
2448 | break; | |
2449 | case 1: | |
2450 | if (vcpu->mmio_needed == 2) | |
8cffd197 | 2451 | *gpr = *(s8 *) run->mmio.data; |
e685c689 SL |
2452 | else |
2453 | *gpr = *(u8 *) run->mmio.data; | |
2454 | break; | |
2455 | } | |
2456 | ||
2457 | if (vcpu->arch.pending_load_cause & CAUSEF_BD) | |
d116e812 DCZ |
2458 | kvm_debug("[%#lx] Completing %d byte BD Load to gpr %d (0x%08lx) type %d\n", |
2459 | vcpu->arch.pc, run->mmio.len, vcpu->arch.io_gpr, *gpr, | |
2460 | vcpu->mmio_needed); | |
e685c689 SL |
2461 | |
2462 | done: | |
2463 | return er; | |
2464 | } | |
2465 | ||
31cf7498 | 2466 | static enum emulation_result kvm_mips_emulate_exc(u32 cause, |
bdb7ed86 | 2467 | u32 *opc, |
d116e812 DCZ |
2468 | struct kvm_run *run, |
2469 | struct kvm_vcpu *vcpu) | |
e685c689 | 2470 | { |
8cffd197 | 2471 | u32 exccode = (cause >> CAUSEB_EXCCODE) & 0x1f; |
e685c689 SL |
2472 | struct mips_coproc *cop0 = vcpu->arch.cop0; |
2473 | struct kvm_vcpu_arch *arch = &vcpu->arch; | |
2474 | enum emulation_result er = EMULATE_DONE; | |
2475 | ||
2476 | if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) { | |
2477 | /* save old pc */ | |
2478 | kvm_write_c0_guest_epc(cop0, arch->pc); | |
2479 | kvm_set_c0_guest_status(cop0, ST0_EXL); | |
2480 | ||
2481 | if (cause & CAUSEF_BD) | |
2482 | kvm_set_c0_guest_cause(cop0, CAUSEF_BD); | |
2483 | else | |
2484 | kvm_clear_c0_guest_cause(cop0, CAUSEF_BD); | |
2485 | ||
2486 | kvm_change_c0_guest_cause(cop0, (0xff), | |
2487 | (exccode << CAUSEB_EXCCODE)); | |
2488 | ||
2489 | /* Set PC to the exception entry point */ | |
2490 | arch->pc = KVM_GUEST_KSEG0 + 0x180; | |
2491 | kvm_write_c0_guest_badvaddr(cop0, vcpu->arch.host_cp0_badvaddr); | |
2492 | ||
2493 | kvm_debug("Delivering EXC %d @ pc %#lx, badVaddr: %#lx\n", | |
2494 | exccode, kvm_read_c0_guest_epc(cop0), | |
2495 | kvm_read_c0_guest_badvaddr(cop0)); | |
2496 | } else { | |
6ad78a5c | 2497 | kvm_err("Trying to deliver EXC when EXL is already set\n"); |
e685c689 SL |
2498 | er = EMULATE_FAIL; |
2499 | } | |
2500 | ||
2501 | return er; | |
2502 | } | |
2503 | ||
31cf7498 | 2504 | enum emulation_result kvm_mips_check_privilege(u32 cause, |
bdb7ed86 | 2505 | u32 *opc, |
d116e812 DCZ |
2506 | struct kvm_run *run, |
2507 | struct kvm_vcpu *vcpu) | |
e685c689 SL |
2508 | { |
2509 | enum emulation_result er = EMULATE_DONE; | |
8cffd197 | 2510 | u32 exccode = (cause >> CAUSEB_EXCCODE) & 0x1f; |
e685c689 SL |
2511 | unsigned long badvaddr = vcpu->arch.host_cp0_badvaddr; |
2512 | ||
2513 | int usermode = !KVM_GUEST_KERNEL_MODE(vcpu); | |
2514 | ||
2515 | if (usermode) { | |
2516 | switch (exccode) { | |
16d100db JH |
2517 | case EXCCODE_INT: |
2518 | case EXCCODE_SYS: | |
2519 | case EXCCODE_BP: | |
2520 | case EXCCODE_RI: | |
2521 | case EXCCODE_TR: | |
2522 | case EXCCODE_MSAFPE: | |
2523 | case EXCCODE_FPE: | |
2524 | case EXCCODE_MSADIS: | |
e685c689 SL |
2525 | break; |
2526 | ||
16d100db | 2527 | case EXCCODE_CPU: |
e685c689 SL |
2528 | if (((cause & CAUSEF_CE) >> CAUSEB_CE) == 0) |
2529 | er = EMULATE_PRIV_FAIL; | |
2530 | break; | |
2531 | ||
16d100db | 2532 | case EXCCODE_MOD: |
e685c689 SL |
2533 | break; |
2534 | ||
16d100db | 2535 | case EXCCODE_TLBL: |
d116e812 DCZ |
2536 | /* |
2537 | * We we are accessing Guest kernel space, then send an | |
2538 | * address error exception to the guest | |
2539 | */ | |
e685c689 | 2540 | if (badvaddr >= (unsigned long) KVM_GUEST_KSEG0) { |
6ad78a5c DCZ |
2541 | kvm_debug("%s: LD MISS @ %#lx\n", __func__, |
2542 | badvaddr); | |
e685c689 | 2543 | cause &= ~0xff; |
16d100db | 2544 | cause |= (EXCCODE_ADEL << CAUSEB_EXCCODE); |
e685c689 SL |
2545 | er = EMULATE_PRIV_FAIL; |
2546 | } | |
2547 | break; | |
2548 | ||
16d100db | 2549 | case EXCCODE_TLBS: |
d116e812 DCZ |
2550 | /* |
2551 | * We we are accessing Guest kernel space, then send an | |
2552 | * address error exception to the guest | |
2553 | */ | |
e685c689 | 2554 | if (badvaddr >= (unsigned long) KVM_GUEST_KSEG0) { |
6ad78a5c DCZ |
2555 | kvm_debug("%s: ST MISS @ %#lx\n", __func__, |
2556 | badvaddr); | |
e685c689 | 2557 | cause &= ~0xff; |
16d100db | 2558 | cause |= (EXCCODE_ADES << CAUSEB_EXCCODE); |
e685c689 SL |
2559 | er = EMULATE_PRIV_FAIL; |
2560 | } | |
2561 | break; | |
2562 | ||
16d100db | 2563 | case EXCCODE_ADES: |
6ad78a5c DCZ |
2564 | kvm_debug("%s: address error ST @ %#lx\n", __func__, |
2565 | badvaddr); | |
e685c689 SL |
2566 | if ((badvaddr & PAGE_MASK) == KVM_GUEST_COMMPAGE_ADDR) { |
2567 | cause &= ~0xff; | |
16d100db | 2568 | cause |= (EXCCODE_TLBS << CAUSEB_EXCCODE); |
e685c689 SL |
2569 | } |
2570 | er = EMULATE_PRIV_FAIL; | |
2571 | break; | |
16d100db | 2572 | case EXCCODE_ADEL: |
6ad78a5c DCZ |
2573 | kvm_debug("%s: address error LD @ %#lx\n", __func__, |
2574 | badvaddr); | |
e685c689 SL |
2575 | if ((badvaddr & PAGE_MASK) == KVM_GUEST_COMMPAGE_ADDR) { |
2576 | cause &= ~0xff; | |
16d100db | 2577 | cause |= (EXCCODE_TLBL << CAUSEB_EXCCODE); |
e685c689 SL |
2578 | } |
2579 | er = EMULATE_PRIV_FAIL; | |
2580 | break; | |
2581 | default: | |
2582 | er = EMULATE_PRIV_FAIL; | |
2583 | break; | |
2584 | } | |
2585 | } | |
2586 | ||
d116e812 | 2587 | if (er == EMULATE_PRIV_FAIL) |
e685c689 | 2588 | kvm_mips_emulate_exc(cause, opc, run, vcpu); |
d116e812 | 2589 | |
e685c689 SL |
2590 | return er; |
2591 | } | |
2592 | ||
d116e812 DCZ |
2593 | /* |
2594 | * User Address (UA) fault, this could happen if | |
e685c689 SL |
2595 | * (1) TLB entry not present/valid in both Guest and shadow host TLBs, in this |
2596 | * case we pass on the fault to the guest kernel and let it handle it. | |
2597 | * (2) TLB entry is present in the Guest TLB but not in the shadow, in this | |
2598 | * case we inject the TLB from the Guest TLB into the shadow host TLB | |
2599 | */ | |
31cf7498 | 2600 | enum emulation_result kvm_mips_handle_tlbmiss(u32 cause, |
bdb7ed86 | 2601 | u32 *opc, |
d116e812 DCZ |
2602 | struct kvm_run *run, |
2603 | struct kvm_vcpu *vcpu) | |
e685c689 SL |
2604 | { |
2605 | enum emulation_result er = EMULATE_DONE; | |
8cffd197 | 2606 | u32 exccode = (cause >> CAUSEB_EXCCODE) & 0x1f; |
e685c689 SL |
2607 | unsigned long va = vcpu->arch.host_cp0_badvaddr; |
2608 | int index; | |
2609 | ||
e4e94c0f JH |
2610 | kvm_debug("kvm_mips_handle_tlbmiss: badvaddr: %#lx\n", |
2611 | vcpu->arch.host_cp0_badvaddr); | |
e685c689 | 2612 | |
d116e812 DCZ |
2613 | /* |
2614 | * KVM would not have got the exception if this entry was valid in the | |
2615 | * shadow host TLB. Check the Guest TLB, if the entry is not there then | |
2616 | * send the guest an exception. The guest exc handler should then inject | |
2617 | * an entry into the guest TLB. | |
e685c689 SL |
2618 | */ |
2619 | index = kvm_mips_guest_tlb_lookup(vcpu, | |
caa1faa7 | 2620 | (va & VPN2_MASK) | |
ca64c2be PB |
2621 | (kvm_read_c0_guest_entryhi(vcpu->arch.cop0) & |
2622 | KVM_ENTRYHI_ASID)); | |
e685c689 | 2623 | if (index < 0) { |
16d100db | 2624 | if (exccode == EXCCODE_TLBL) { |
e685c689 | 2625 | er = kvm_mips_emulate_tlbmiss_ld(cause, opc, run, vcpu); |
16d100db | 2626 | } else if (exccode == EXCCODE_TLBS) { |
e685c689 SL |
2627 | er = kvm_mips_emulate_tlbmiss_st(cause, opc, run, vcpu); |
2628 | } else { | |
6ad78a5c DCZ |
2629 | kvm_err("%s: invalid exc code: %d\n", __func__, |
2630 | exccode); | |
e685c689 SL |
2631 | er = EMULATE_FAIL; |
2632 | } | |
2633 | } else { | |
2634 | struct kvm_mips_tlb *tlb = &vcpu->arch.guest_tlb[index]; | |
2635 | ||
d116e812 DCZ |
2636 | /* |
2637 | * Check if the entry is valid, if not then setup a TLB invalid | |
2638 | * exception to the guest | |
2639 | */ | |
e685c689 | 2640 | if (!TLB_IS_VALID(*tlb, va)) { |
16d100db | 2641 | if (exccode == EXCCODE_TLBL) { |
e685c689 SL |
2642 | er = kvm_mips_emulate_tlbinv_ld(cause, opc, run, |
2643 | vcpu); | |
16d100db | 2644 | } else if (exccode == EXCCODE_TLBS) { |
e685c689 SL |
2645 | er = kvm_mips_emulate_tlbinv_st(cause, opc, run, |
2646 | vcpu); | |
2647 | } else { | |
6ad78a5c DCZ |
2648 | kvm_err("%s: invalid exc code: %d\n", __func__, |
2649 | exccode); | |
e685c689 SL |
2650 | er = EMULATE_FAIL; |
2651 | } | |
2652 | } else { | |
d116e812 | 2653 | kvm_debug("Injecting hi: %#lx, lo0: %#lx, lo1: %#lx into shadow host TLB\n", |
9fbfb06a | 2654 | tlb->tlb_hi, tlb->tlb_lo[0], tlb->tlb_lo[1]); |
d116e812 DCZ |
2655 | /* |
2656 | * OK we have a Guest TLB entry, now inject it into the | |
2657 | * shadow host TLB | |
2658 | */ | |
26ee17ff | 2659 | kvm_mips_handle_mapped_seg_tlb_fault(vcpu, tlb); |
e685c689 SL |
2660 | } |
2661 | } | |
2662 | ||
2663 | return er; | |
2664 | } |