[deliverable/linux.git] / arch / mips / kvm / stats.c

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * KVM/MIPS: COP0 access histogram
 *
 * Copyright (C) 2012  MIPS Technologies, Inc.  All rights reserved.
 * Authors: Sanjay Lal <sanjayl@kymasys.com>
 */

#include <linux/kvm_host.h>

char *kvm_mips_exit_types_str[MAX_KVM_MIPS_EXIT_TYPES] = {
	"WAIT",
	"CACHE",
	"Signal",
	"Interrupt",
	"COP0/1 Unusable",
	"TLB Mod",
	"TLB Miss (LD)",
	"TLB Miss (ST)",
	"Address Err (ST)",
	"Address Error (LD)",
	"System Call",
	"Reserved Inst",
	"Break Inst",
	"Trap Inst",
	"D-Cache Flushes",
};

char *kvm_cop0_str[N_MIPS_COPROC_REGS] = {
	"Index",
	"Random",
	"EntryLo0",
	"EntryLo1",
	"Context",
	"PG Mask",
	"Wired",
	"HWREna",
	"BadVAddr",
	"Count",
	"EntryHI",
	"Compare",
	"Status",
	"Cause",
	"EXC PC",
	"PRID",
	"Config",
	"LLAddr",
	"Watch Lo",
	"Watch Hi",
	"X Context",
	"Reserved",
	"Impl Dep",
	"Debug",
	"DEPC",
	"PerfCnt",
	"ErrCtl",
	"CacheErr",
	"TagLo",
	"TagHi",
	"ErrorEPC",
	"DESAVE"
};

void kvm_mips_dump_stats(struct kvm_vcpu *vcpu)
{
#ifdef CONFIG_KVM_MIPS_DEBUG_COP0_COUNTERS
	int i, j;

	kvm_info("\nKVM VCPU[%d] COP0 Access Profile:\n", vcpu->vcpu_id);
	for (i = 0; i < N_MIPS_COPROC_REGS; i++) {
		for (j = 0; j < N_MIPS_COPROC_SEL; j++) {
			if (vcpu->arch.cop0->stat[i][j])
				kvm_info("%s[%d]: %lu\n", kvm_cop0_str[i], j,
					 vcpu->arch.cop0->stat[i][j]);
		}
	}
#endif
}
Commit	Line	Data
3c20ef52	1	/*
d116e812 DCZ	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* KVM/MIPS: COP0 access histogram
	7	*
	8	* Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
	9	* Authors: Sanjay Lal <sanjayl@kymasys.com>
	10	*/
3c20ef52 SL	11
	12	#include <linux/kvm_host.h>
	13
	14	char *kvm_mips_exit_types_str[MAX_KVM_MIPS_EXIT_TYPES] = {
	15	"WAIT",
	16	"CACHE",
	17	"Signal",
	18	"Interrupt",
	19	"COP0/1 Unusable",
	20	"TLB Mod",
	21	"TLB Miss (LD)",
	22	"TLB Miss (ST)",
	23	"Address Err (ST)",
	24	"Address Error (LD)",
	25	"System Call",
	26	"Reserved Inst",
	27	"Break Inst",
0a560427	28	"Trap Inst",
3c20ef52 SL	29	"D-Cache Flushes",
	30	};
	31
	32	char *kvm_cop0_str[N_MIPS_COPROC_REGS] = {
	33	"Index",
	34	"Random",
	35	"EntryLo0",
	36	"EntryLo1",
	37	"Context",
	38	"PG Mask",
	39	"Wired",
	40	"HWREna",
	41	"BadVAddr",
	42	"Count",
	43	"EntryHI",
	44	"Compare",
	45	"Status",
	46	"Cause",
	47	"EXC PC",
	48	"PRID",
	49	"Config",
	50	"LLAddr",
	51	"Watch Lo",
	52	"Watch Hi",
	53	"X Context",
	54	"Reserved",
	55	"Impl Dep",
	56	"Debug",
	57	"DEPC",
	58	"PerfCnt",
	59	"ErrCtl",
	60	"CacheErr",
	61	"TagLo",
	62	"TagHi",
	63	"ErrorEPC",
	64	"DESAVE"
	65	};
	66
d98403a5	67	void kvm_mips_dump_stats(struct kvm_vcpu *vcpu)
3c20ef52 SL	68	{
	69	#ifdef CONFIG_KVM_MIPS_DEBUG_COP0_COUNTERS
	70	int i, j;
	71
6ad78a5c	72	kvm_info("\nKVM VCPU[%d] COP0 Access Profile:\n", vcpu->vcpu_id);
3c20ef52 SL	73	for (i = 0; i < N_MIPS_COPROC_REGS; i++) {
	74	for (j = 0; j < N_MIPS_COPROC_SEL; j++) {
	75	if (vcpu->arch.cop0->stat[i][j])
6ad78a5c DCZ	76	kvm_info("%s[%d]: %lu\n", kvm_cop0_str[i], j,
6ad78a5c DCZ	77	vcpu->arch.cop0->stat[i][j]);
3c20ef52 SL	78	}
	79	}
	80	#endif
3c20ef52	81	}