[deliverable/linux.git] / arch / mips / lantiq / irq.c

/*
 *  This program is free software; you can redistribute it and/or modify it
 *  under the terms of the GNU General Public License version 2 as published
 *  by the Free Software Foundation.
 *
 * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
 * Copyright (C) 2010 Thomas Langer <thomas.langer@lantiq.com>
 */

#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/sched.h>
#include <linux/irqdomain.h>
#include <linux/of_platform.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>

#include <asm/bootinfo.h>
#include <asm/irq_cpu.h>

#include <lantiq_soc.h>
#include <irq.h>

/* register definitions - internal irqs */
#define LTQ_ICU_IM0_ISR		0x0000
#define LTQ_ICU_IM0_IER		0x0008
#define LTQ_ICU_IM0_IOSR	0x0010
#define LTQ_ICU_IM0_IRSR	0x0018
#define LTQ_ICU_IM0_IMR		0x0020
#define LTQ_ICU_IM1_ISR		0x0028
#define LTQ_ICU_OFFSET		(LTQ_ICU_IM1_ISR - LTQ_ICU_IM0_ISR)

/* register definitions - external irqs */
#define LTQ_EIU_EXIN_C		0x0000
#define LTQ_EIU_EXIN_INIC	0x0004
#define LTQ_EIU_EXIN_INEN	0x000C

/* irq numbers used by the external interrupt unit (EIU) */
#define LTQ_EIU_IR0		(INT_NUM_IM4_IRL0 + 30)
#define LTQ_EIU_IR1		(INT_NUM_IM3_IRL0 + 31)
#define LTQ_EIU_IR2		(INT_NUM_IM1_IRL0 + 26)
#define LTQ_EIU_IR3		INT_NUM_IM1_IRL0
#define LTQ_EIU_IR4		(INT_NUM_IM1_IRL0 + 1)
#define LTQ_EIU_IR5		(INT_NUM_IM1_IRL0 + 2)
#define LTQ_EIU_IR6		(INT_NUM_IM2_IRL0 + 30)
#define XWAY_EXIN_COUNT		3
#define MAX_EIU			6

/* the performance counter */
#define LTQ_PERF_IRQ		(INT_NUM_IM4_IRL0 + 31)

/*
 * irqs generated by devices attached to the EBU need to be acked in
 * a special manner
 */
#define LTQ_ICU_EBU_IRQ		22

#define ltq_icu_w32(m, x, y)	ltq_w32((x), ltq_icu_membase[m] + (y))
#define ltq_icu_r32(m, x)	ltq_r32(ltq_icu_membase[m] + (x))

#define ltq_eiu_w32(x, y)	ltq_w32((x), ltq_eiu_membase + (y))
#define ltq_eiu_r32(x)		ltq_r32(ltq_eiu_membase + (x))

/* our 2 ipi interrupts for VSMP */
#define MIPS_CPU_IPI_RESCHED_IRQ	0
#define MIPS_CPU_IPI_CALL_IRQ		1

/* we have a cascade of 8 irqs */
#define MIPS_CPU_IRQ_CASCADE		8

#if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC)
int gic_present;
#endif

static unsigned short ltq_eiu_irq[MAX_EIU] = {
	LTQ_EIU_IR0,
	LTQ_EIU_IR1,
	LTQ_EIU_IR2,
	LTQ_EIU_IR3,
	LTQ_EIU_IR4,
	LTQ_EIU_IR5,
};

static int exin_avail;
static void __iomem *ltq_icu_membase[MAX_IM];
static void __iomem *ltq_eiu_membase;
static struct irq_domain *ltq_domain;

void ltq_disable_irq(struct irq_data *d)
{
	u32 ier = LTQ_ICU_IM0_IER;
	int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
	int im = offset / INT_NUM_IM_OFFSET;

	offset %= INT_NUM_IM_OFFSET;
	ltq_icu_w32(im, ltq_icu_r32(im, ier) & ~BIT(offset), ier);
}

void ltq_mask_and_ack_irq(struct irq_data *d)
{
	u32 ier = LTQ_ICU_IM0_IER;
	u32 isr = LTQ_ICU_IM0_ISR;
	int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
	int im = offset / INT_NUM_IM_OFFSET;

	offset %= INT_NUM_IM_OFFSET;
	ltq_icu_w32(im, ltq_icu_r32(im, ier) & ~BIT(offset), ier);
	ltq_icu_w32(im, BIT(offset), isr);
}

static void ltq_ack_irq(struct irq_data *d)
{
	u32 isr = LTQ_ICU_IM0_ISR;
	int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
	int im = offset / INT_NUM_IM_OFFSET;

	offset %= INT_NUM_IM_OFFSET;
	ltq_icu_w32(im, BIT(offset), isr);
}

void ltq_enable_irq(struct irq_data *d)
{
	u32 ier = LTQ_ICU_IM0_IER;
	int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
	int im = offset / INT_NUM_IM_OFFSET;

	offset %= INT_NUM_IM_OFFSET;
	ltq_icu_w32(im, ltq_icu_r32(im, ier) | BIT(offset), ier);
}

static unsigned int ltq_startup_eiu_irq(struct irq_data *d)
{
	int i;

	ltq_enable_irq(d);
	for (i = 0; i < MAX_EIU; i++) {
		if (d->hwirq == ltq_eiu_irq[i]) {
			/* low level - we should really handle set_type */
			ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_C) |
				(0x6 << (i * 4)), LTQ_EIU_EXIN_C);
			/* clear all pending */
			ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INIC) & ~BIT(i),
				LTQ_EIU_EXIN_INIC);
			/* enable */
			ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN) | BIT(i),
				LTQ_EIU_EXIN_INEN);
			break;
		}
	}

	return 0;
}

static void ltq_shutdown_eiu_irq(struct irq_data *d)
{
	int i;

	ltq_disable_irq(d);
	for (i = 0; i < MAX_EIU; i++) {
		if (d->hwirq == ltq_eiu_irq[i]) {
			/* disable */
			ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN) & ~BIT(i),
				LTQ_EIU_EXIN_INEN);
			break;
		}
	}
}

static struct irq_chip ltq_irq_type = {
	"icu",
	.irq_enable = ltq_enable_irq,
	.irq_disable = ltq_disable_irq,
	.irq_unmask = ltq_enable_irq,
	.irq_ack = ltq_ack_irq,
	.irq_mask = ltq_disable_irq,
	.irq_mask_ack = ltq_mask_and_ack_irq,
};

static struct irq_chip ltq_eiu_type = {
	"eiu",
	.irq_startup = ltq_startup_eiu_irq,
	.irq_shutdown = ltq_shutdown_eiu_irq,
	.irq_enable = ltq_enable_irq,
	.irq_disable = ltq_disable_irq,
	.irq_unmask = ltq_enable_irq,
	.irq_ack = ltq_ack_irq,
	.irq_mask = ltq_disable_irq,
	.irq_mask_ack = ltq_mask_and_ack_irq,
};

static void ltq_hw_irqdispatch(int module)
{
	u32 irq;

	irq = ltq_icu_r32(module, LTQ_ICU_IM0_IOSR);
	if (irq == 0)
		return;

	/*
	 * silicon bug causes only the msb set to 1 to be valid. all
	 * other bits might be bogus
	 */
	irq = __fls(irq);
	do_IRQ((int)irq + MIPS_CPU_IRQ_CASCADE + (INT_NUM_IM_OFFSET * module));

	/* if this is a EBU irq, we need to ack it or get a deadlock */
	if ((irq == LTQ_ICU_EBU_IRQ) && (module == 0) && LTQ_EBU_PCC_ISTAT)
		ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_ISTAT) | 0x10,
			LTQ_EBU_PCC_ISTAT);
}

#define DEFINE_HWx_IRQDISPATCH(x)					\
	static void ltq_hw ## x ## _irqdispatch(void)			\
	{								\
		ltq_hw_irqdispatch(x);					\
	}
DEFINE_HWx_IRQDISPATCH(0)
DEFINE_HWx_IRQDISPATCH(1)
DEFINE_HWx_IRQDISPATCH(2)
DEFINE_HWx_IRQDISPATCH(3)
DEFINE_HWx_IRQDISPATCH(4)

#if MIPS_CPU_TIMER_IRQ == 7
static void ltq_hw5_irqdispatch(void)
{
	do_IRQ(MIPS_CPU_TIMER_IRQ);
}
#else
DEFINE_HWx_IRQDISPATCH(5)
#endif

#ifdef CONFIG_MIPS_MT_SMP
void __init arch_init_ipiirq(int irq, struct irqaction *action)
{
	setup_irq(irq, action);
	irq_set_handler(irq, handle_percpu_irq);
}

static void ltq_sw0_irqdispatch(void)
{
	do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ);
}

static void ltq_sw1_irqdispatch(void)
{
	do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ);
}
static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id)
{
	scheduler_ipi();
	return IRQ_HANDLED;
}

static irqreturn_t ipi_call_interrupt(int irq, void *dev_id)
{
	smp_call_function_interrupt();
	return IRQ_HANDLED;
}

static struct irqaction irq_resched = {
	.handler	= ipi_resched_interrupt,
	.flags		= IRQF_PERCPU,
	.name		= "IPI_resched"
};

static struct irqaction irq_call = {
	.handler	= ipi_call_interrupt,
	.flags		= IRQF_PERCPU,
	.name		= "IPI_call"
};
#endif

asmlinkage void plat_irq_dispatch(void)
{
	unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
	unsigned int i;

	if ((MIPS_CPU_TIMER_IRQ == 7) && (pending & CAUSEF_IP7)) {
		do_IRQ(MIPS_CPU_TIMER_IRQ);
		goto out;
	} else {
		for (i = 0; i < MAX_IM; i++) {
			if (pending & (CAUSEF_IP2 << i)) {
				ltq_hw_irqdispatch(i);
				goto out;
			}
		}
	}
	pr_alert("Spurious IRQ: CAUSE=0x%08x\n", read_c0_status());

out:
	return;
}

static int icu_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
{
	struct irq_chip *chip = &ltq_irq_type;
	int i;

	if (hw < MIPS_CPU_IRQ_CASCADE)
		return 0;

	for (i = 0; i < exin_avail; i++)
		if (hw == ltq_eiu_irq[i])
			chip = &ltq_eiu_type;

	irq_set_chip_and_handler(hw, chip, handle_level_irq);

	return 0;
}

static const struct irq_domain_ops irq_domain_ops = {
	.xlate = irq_domain_xlate_onetwocell,
	.map = icu_map,
};

static struct irqaction cascade = {
	.handler = no_action,
	.name = "cascade",
};

int __init icu_of_init(struct device_node *node, struct device_node *parent)
{
	struct device_node *eiu_node;
	struct resource res;
	int i;

	for (i = 0; i < MAX_IM; i++) {
		if (of_address_to_resource(node, i, &res))
			panic("Failed to get icu memory range");

		if (request_mem_region(res.start, resource_size(&res),
					res.name) < 0)
			pr_err("Failed to request icu memory");

		ltq_icu_membase[i] = ioremap_nocache(res.start,
					resource_size(&res));
		if (!ltq_icu_membase[i])
			panic("Failed to remap icu memory");
	}

	/* the external interrupts are optional and xway only */
	eiu_node = of_find_compatible_node(NULL, NULL, "lantiq,eiu");
	if (eiu_node && !of_address_to_resource(eiu_node, 0, &res)) {
		/* find out how many external irq sources we have */
		const __be32 *count = of_get_property(node,
							"lantiq,count",	NULL);

		if (count)
			exin_avail = *count;
		if (exin_avail > MAX_EIU)
			exin_avail = MAX_EIU;

		if (request_mem_region(res.start, resource_size(&res),
							res.name) < 0)
			pr_err("Failed to request eiu memory");

		ltq_eiu_membase = ioremap_nocache(res.start,
							resource_size(&res));
		if (!ltq_eiu_membase)
			panic("Failed to remap eiu memory");
	}

	/* turn off all irqs by default */
	for (i = 0; i < MAX_IM; i++) {
		/* make sure all irqs are turned off by default */
		ltq_icu_w32(i, 0, LTQ_ICU_IM0_IER);
		/* clear all possibly pending interrupts */
		ltq_icu_w32(i, ~0, LTQ_ICU_IM0_ISR);
	}

	mips_cpu_irq_init();

	for (i = 0; i < MAX_IM; i++)
		setup_irq(i + 2, &cascade);

	if (cpu_has_vint) {
		pr_info("Setting up vectored interrupts\n");
		set_vi_handler(2, ltq_hw0_irqdispatch);
		set_vi_handler(3, ltq_hw1_irqdispatch);
		set_vi_handler(4, ltq_hw2_irqdispatch);
		set_vi_handler(5, ltq_hw3_irqdispatch);
		set_vi_handler(6, ltq_hw4_irqdispatch);
		set_vi_handler(7, ltq_hw5_irqdispatch);
	}

	ltq_domain = irq_domain_add_linear(node,
		(MAX_IM * INT_NUM_IM_OFFSET) + MIPS_CPU_IRQ_CASCADE,
		&irq_domain_ops, 0);

#if defined(CONFIG_MIPS_MT_SMP)
	if (cpu_has_vint) {
		pr_info("Setting up IPI vectored interrupts\n");
		set_vi_handler(MIPS_CPU_IPI_RESCHED_IRQ, ltq_sw0_irqdispatch);
		set_vi_handler(MIPS_CPU_IPI_CALL_IRQ, ltq_sw1_irqdispatch);
	}
	arch_init_ipiirq(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ,
		&irq_resched);
	arch_init_ipiirq(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ, &irq_call);
#endif

#if !defined(CONFIG_MIPS_MT_SMP) && !defined(CONFIG_MIPS_MT_SMTC)
	set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 |
		IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
#else
	set_c0_status(IE_SW0 | IE_SW1 | IE_IRQ0 | IE_IRQ1 |
		IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
#endif

	/* tell oprofile which irq to use */
	cp0_perfcount_irq = LTQ_PERF_IRQ;

	/*
	 * if the timer irq is not one of the mips irqs we need to
	 * create a mapping
	 */
	if (MIPS_CPU_TIMER_IRQ != 7)
		irq_create_mapping(ltq_domain, MIPS_CPU_TIMER_IRQ);

	return 0;
}

unsigned int __cpuinit get_c0_compare_int(void)
{
	return MIPS_CPU_TIMER_IRQ;
}

static struct of_device_id __initdata of_irq_ids[] = {
	{ .compatible = "lantiq,icu", .data = icu_of_init },
	{},
};

void __init arch_init_irq(void)
{
	of_irq_init(of_irq_ids);
}
Commit	Line	Data
171bb2f1 JC	1	/*
	2	* This program is free software; you can redistribute it and/or modify it
	3	* under the terms of the GNU General Public License version 2 as published
	4	* by the Free Software Foundation.
	5	*
	6	* Copyright (C) 2010 John Crispin <blogic@openwrt.org>
	7	* Copyright (C) 2010 Thomas Langer <thomas.langer@lantiq.com>
	8	*/
	9
	10	#include <linux/interrupt.h>
	11	#include <linux/ioport.h>
3645da02 JC	12	#include <linux/sched.h>
	13	#include <linux/irqdomain.h>
	14	#include <linux/of_platform.h>
	15	#include <linux/of_address.h>
	16	#include <linux/of_irq.h>
171bb2f1 JC	17
	18	#include <asm/bootinfo.h>
	19	#include <asm/irq_cpu.h>
	20
	21	#include <lantiq_soc.h>
	22	#include <irq.h>
	23
3645da02	24	/* register definitions - internal irqs */
171bb2f1 JC	25	#define LTQ_ICU_IM0_ISR 0x0000
	26	#define LTQ_ICU_IM0_IER 0x0008
	27	#define LTQ_ICU_IM0_IOSR 0x0010
	28	#define LTQ_ICU_IM0_IRSR 0x0018
	29	#define LTQ_ICU_IM0_IMR 0x0020
	30	#define LTQ_ICU_IM1_ISR 0x0028
	31	#define LTQ_ICU_OFFSET (LTQ_ICU_IM1_ISR - LTQ_ICU_IM0_ISR)
	32
3645da02	33	/* register definitions - external irqs */
171bb2f1 JC	34	#define LTQ_EIU_EXIN_C 0x0000
	35	#define LTQ_EIU_EXIN_INIC 0x0004
	36	#define LTQ_EIU_EXIN_INEN 0x000C
	37
	38	/* irq numbers used by the external interrupt unit (EIU) */
	39	#define LTQ_EIU_IR0 (INT_NUM_IM4_IRL0 + 30)
	40	#define LTQ_EIU_IR1 (INT_NUM_IM3_IRL0 + 31)
	41	#define LTQ_EIU_IR2 (INT_NUM_IM1_IRL0 + 26)
	42	#define LTQ_EIU_IR3 INT_NUM_IM1_IRL0
	43	#define LTQ_EIU_IR4 (INT_NUM_IM1_IRL0 + 1)
	44	#define LTQ_EIU_IR5 (INT_NUM_IM1_IRL0 + 2)
	45	#define LTQ_EIU_IR6 (INT_NUM_IM2_IRL0 + 30)
3645da02	46	#define XWAY_EXIN_COUNT 3
171bb2f1 JC	47	#define MAX_EIU 6
171bb2f1 JC	48
59c11579 JC	49	/* the performance counter */
	50	#define LTQ_PERF_IRQ (INT_NUM_IM4_IRL0 + 31)
	51
3645da02 JC	52	/*
3645da02 JC	53	* irqs generated by devices attached to the EBU need to be acked in
171bb2f1 JC	54	* a special manner
	55	*/
	56	#define LTQ_ICU_EBU_IRQ 22
	57
61fa969f JC	58	#define ltq_icu_w32(m, x, y) ltq_w32((x), ltq_icu_membase[m] + (y))
61fa969f JC	59	#define ltq_icu_r32(m, x) ltq_r32(ltq_icu_membase[m] + (x))
171bb2f1 JC	60
	61	#define ltq_eiu_w32(x, y) ltq_w32((x), ltq_eiu_membase + (y))
	62	#define ltq_eiu_r32(x) ltq_r32(ltq_eiu_membase + (x))
	63
a8d096ef JC	64	/* our 2 ipi interrupts for VSMP */
	65	#define MIPS_CPU_IPI_RESCHED_IRQ 0
	66	#define MIPS_CPU_IPI_CALL_IRQ 1
	67
3645da02 JC	68	/* we have a cascade of 8 irqs */
	69	#define MIPS_CPU_IRQ_CASCADE 8
	70
a8d096ef JC	71	#if defined(CONFIG_MIPS_MT_SMP) \|\| defined(CONFIG_MIPS_MT_SMTC)
	72	int gic_present;
	73	#endif
	74
171bb2f1 JC	75	static unsigned short ltq_eiu_irq[MAX_EIU] = {
	76	LTQ_EIU_IR0,
	77	LTQ_EIU_IR1,
	78	LTQ_EIU_IR2,
	79	LTQ_EIU_IR3,
	80	LTQ_EIU_IR4,
	81	LTQ_EIU_IR5,
	82	};
	83
3645da02	84	static int exin_avail;
61fa969f	85	static void __iomem *ltq_icu_membase[MAX_IM];
171bb2f1	86	static void __iomem *ltq_eiu_membase;
c2c9c788	87	static struct irq_domain *ltq_domain;
171bb2f1 JC	88
	89	void ltq_disable_irq(struct irq_data *d)
	90	{
	91	u32 ier = LTQ_ICU_IM0_IER;
3645da02	92	int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
61fa969f	93	int im = offset / INT_NUM_IM_OFFSET;
171bb2f1	94
3645da02	95	offset %= INT_NUM_IM_OFFSET;
61fa969f	96	ltq_icu_w32(im, ltq_icu_r32(im, ier) & ~BIT(offset), ier);
171bb2f1 JC	97	}
	98
	99	void ltq_mask_and_ack_irq(struct irq_data *d)
	100	{
	101	u32 ier = LTQ_ICU_IM0_IER;
	102	u32 isr = LTQ_ICU_IM0_ISR;
3645da02	103	int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
61fa969f	104	int im = offset / INT_NUM_IM_OFFSET;
171bb2f1	105
3645da02	106	offset %= INT_NUM_IM_OFFSET;
61fa969f JC	107	ltq_icu_w32(im, ltq_icu_r32(im, ier) & ~BIT(offset), ier);
61fa969f JC	108	ltq_icu_w32(im, BIT(offset), isr);
171bb2f1 JC	109	}
	110
	111	static void ltq_ack_irq(struct irq_data *d)
	112	{
	113	u32 isr = LTQ_ICU_IM0_ISR;
3645da02	114	int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
61fa969f	115	int im = offset / INT_NUM_IM_OFFSET;
171bb2f1	116
3645da02	117	offset %= INT_NUM_IM_OFFSET;
61fa969f	118	ltq_icu_w32(im, BIT(offset), isr);
171bb2f1 JC	119	}
	120
	121	void ltq_enable_irq(struct irq_data *d)
	122	{
	123	u32 ier = LTQ_ICU_IM0_IER;
3645da02	124	int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
61fa969f	125	int im = offset / INT_NUM_IM_OFFSET;
171bb2f1	126
3645da02	127	offset %= INT_NUM_IM_OFFSET;
61fa969f	128	ltq_icu_w32(im, ltq_icu_r32(im, ier) \| BIT(offset), ier);
171bb2f1 JC	129	}
	130
	131	static unsigned int ltq_startup_eiu_irq(struct irq_data *d)
	132	{
	133	int i;
171bb2f1 JC	134
	135	ltq_enable_irq(d);
	136	for (i = 0; i < MAX_EIU; i++) {
3645da02	137	if (d->hwirq == ltq_eiu_irq[i]) {
171bb2f1 JC	138	/* low level - we should really handle set_type */
	139	ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_C) \|
	140	(0x6 << (i * 4)), LTQ_EIU_EXIN_C);
	141	/* clear all pending */
3645da02	142	ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INIC) & ~BIT(i),
171bb2f1 JC	143	LTQ_EIU_EXIN_INIC);
171bb2f1 JC	144	/* enable */
3645da02	145	ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN) \| BIT(i),
171bb2f1 JC	146	LTQ_EIU_EXIN_INEN);
	147	break;
	148	}
	149	}
	150
	151	return 0;
	152	}
	153
	154	static void ltq_shutdown_eiu_irq(struct irq_data *d)
	155	{
	156	int i;
171bb2f1 JC	157
	158	ltq_disable_irq(d);
	159	for (i = 0; i < MAX_EIU; i++) {
3645da02	160	if (d->hwirq == ltq_eiu_irq[i]) {
171bb2f1	161	/* disable */
3645da02	162	ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN) & ~BIT(i),
171bb2f1 JC	163	LTQ_EIU_EXIN_INEN);
	164	break;
	165	}
	166	}
	167	}
	168
	169	static struct irq_chip ltq_irq_type = {
	170	"icu",
	171	.irq_enable = ltq_enable_irq,
	172	.irq_disable = ltq_disable_irq,
	173	.irq_unmask = ltq_enable_irq,
	174	.irq_ack = ltq_ack_irq,
	175	.irq_mask = ltq_disable_irq,
	176	.irq_mask_ack = ltq_mask_and_ack_irq,
	177	};
	178
	179	static struct irq_chip ltq_eiu_type = {
	180	"eiu",
	181	.irq_startup = ltq_startup_eiu_irq,
	182	.irq_shutdown = ltq_shutdown_eiu_irq,
	183	.irq_enable = ltq_enable_irq,
	184	.irq_disable = ltq_disable_irq,
	185	.irq_unmask = ltq_enable_irq,
	186	.irq_ack = ltq_ack_irq,
	187	.irq_mask = ltq_disable_irq,
	188	.irq_mask_ack = ltq_mask_and_ack_irq,
	189	};
	190
	191	static void ltq_hw_irqdispatch(int module)
	192	{
	193	u32 irq;
	194
61fa969f	195	irq = ltq_icu_r32(module, LTQ_ICU_IM0_IOSR);
171bb2f1 JC	196	if (irq == 0)
	197	return;
	198
3645da02 JC	199	/*
3645da02 JC	200	* silicon bug causes only the msb set to 1 to be valid. all
171bb2f1 JC	201	* other bits might be bogus
	202	*/
	203	irq = __fls(irq);
3645da02	204	do_IRQ((int)irq + MIPS_CPU_IRQ_CASCADE + (INT_NUM_IM_OFFSET * module));
171bb2f1 JC	205
171bb2f1 JC	206	/* if this is a EBU irq, we need to ack it or get a deadlock */
3645da02	207	if ((irq == LTQ_ICU_EBU_IRQ) && (module == 0) && LTQ_EBU_PCC_ISTAT)
171bb2f1 JC	208	ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_ISTAT) \| 0x10,
	209	LTQ_EBU_PCC_ISTAT);
	210	}
	211
	212	#define DEFINE_HWx_IRQDISPATCH(x) \
	213	static void ltq_hw ## x ## _irqdispatch(void) \
	214	{ \
	215	ltq_hw_irqdispatch(x); \
	216	}
	217	DEFINE_HWx_IRQDISPATCH(0)
	218	DEFINE_HWx_IRQDISPATCH(1)
	219	DEFINE_HWx_IRQDISPATCH(2)
	220	DEFINE_HWx_IRQDISPATCH(3)
	221	DEFINE_HWx_IRQDISPATCH(4)
	222
c2c9c788	223	#if MIPS_CPU_TIMER_IRQ == 7
171bb2f1 JC	224	static void ltq_hw5_irqdispatch(void)
	225	{
	226	do_IRQ(MIPS_CPU_TIMER_IRQ);
	227	}
c2c9c788 JC	228	#else
	229	DEFINE_HWx_IRQDISPATCH(5)
	230	#endif
171bb2f1	231
a8d096ef JC	232	#ifdef CONFIG_MIPS_MT_SMP
	233	void __init arch_init_ipiirq(int irq, struct irqaction *action)
	234	{
	235	setup_irq(irq, action);
	236	irq_set_handler(irq, handle_percpu_irq);
	237	}
	238
	239	static void ltq_sw0_irqdispatch(void)
	240	{
	241	do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ);
	242	}
	243
	244	static void ltq_sw1_irqdispatch(void)
	245	{
	246	do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ);
	247	}
	248	static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id)
	249	{
	250	scheduler_ipi();
	251	return IRQ_HANDLED;
	252	}
	253
	254	static irqreturn_t ipi_call_interrupt(int irq, void *dev_id)
	255	{
	256	smp_call_function_interrupt();
	257	return IRQ_HANDLED;
	258	}
	259
	260	static struct irqaction irq_resched = {
	261	.handler = ipi_resched_interrupt,
	262	.flags = IRQF_PERCPU,
	263	.name = "IPI_resched"
	264	};
	265
	266	static struct irqaction irq_call = {
	267	.handler = ipi_call_interrupt,
	268	.flags = IRQF_PERCPU,
	269	.name = "IPI_call"
	270	};
	271	#endif
	272
171bb2f1 JC	273	asmlinkage void plat_irq_dispatch(void)
	274	{
	275	unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
	276	unsigned int i;
	277
c2c9c788	278	if ((MIPS_CPU_TIMER_IRQ == 7) && (pending & CAUSEF_IP7)) {
171bb2f1 JC	279	do_IRQ(MIPS_CPU_TIMER_IRQ);
	280	goto out;
	281	} else {
61fa969f	282	for (i = 0; i < MAX_IM; i++) {
171bb2f1 JC	283	if (pending & (CAUSEF_IP2 << i)) {
	284	ltq_hw_irqdispatch(i);
	285	goto out;
	286	}
	287	}
	288	}
	289	pr_alert("Spurious IRQ: CAUSE=0x%08x\n", read_c0_status());
	290
	291	out:
	292	return;
	293	}
	294
3645da02 JC	295	static int icu_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
	296	{
	297	struct irq_chip *chip = &ltq_irq_type;
	298	int i;
	299
9c1628b6 JC	300	if (hw < MIPS_CPU_IRQ_CASCADE)
	301	return 0;
	302
3645da02 JC	303	for (i = 0; i < exin_avail; i++)
	304	if (hw == ltq_eiu_irq[i])
	305	chip = &ltq_eiu_type;
	306
	307	irq_set_chip_and_handler(hw, chip, handle_level_irq);
	308
	309	return 0;
	310	}
	311
	312	static const struct irq_domain_ops irq_domain_ops = {
	313	.xlate = irq_domain_xlate_onetwocell,
	314	.map = icu_map,
	315	};
	316
171bb2f1 JC	317	static struct irqaction cascade = {
171bb2f1 JC	318	.handler = no_action,
171bb2f1 JC	319	.name = "cascade",
	320	};
	321
3645da02	322	int __init icu_of_init(struct device_node node, struct device_node parent)
171bb2f1	323	{
3645da02 JC	324	struct device_node *eiu_node;
3645da02 JC	325	struct resource res;
171bb2f1 JC	326	int i;
171bb2f1 JC	327
61fa969f JC	328	for (i = 0; i < MAX_IM; i++) {
	329	if (of_address_to_resource(node, i, &res))
	330	panic("Failed to get icu memory range");
171bb2f1	331
61fa969f JC	332	if (request_mem_region(res.start, resource_size(&res),
	333	res.name) < 0)
	334	pr_err("Failed to request icu memory");
171bb2f1	335
61fa969f JC	336	ltq_icu_membase[i] = ioremap_nocache(res.start,
	337	resource_size(&res));
	338	if (!ltq_icu_membase[i])
	339	panic("Failed to remap icu memory");
	340	}
171bb2f1	341
3645da02 JC	342	/* the external interrupts are optional and xway only */
3645da02 JC	343	eiu_node = of_find_compatible_node(NULL, NULL, "lantiq,eiu");
70ec9054	344	if (eiu_node && !of_address_to_resource(eiu_node, 0, &res)) {
3645da02 JC	345	/* find out how many external irq sources we have */
	346	const __be32 *count = of_get_property(node,
	347	"lantiq,count", NULL);
	348
	349	if (count)
	350	exin_avail = *count;
	351	if (exin_avail > MAX_EIU)
	352	exin_avail = MAX_EIU;
	353
	354	if (request_mem_region(res.start, resource_size(&res),
	355	res.name) < 0)
	356	pr_err("Failed to request eiu memory");
	357
	358	ltq_eiu_membase = ioremap_nocache(res.start,
	359	resource_size(&res));
	360	if (!ltq_eiu_membase)
	361	panic("Failed to remap eiu memory");
	362	}
171bb2f1	363
16f70b56	364	/* turn off all irqs by default */
61fa969f	365	for (i = 0; i < MAX_IM; i++) {
16f70b56	366	/* make sure all irqs are turned off by default */
61fa969f	367	ltq_icu_w32(i, 0, LTQ_ICU_IM0_IER);
16f70b56	368	/* clear all possibly pending interrupts */
61fa969f	369	ltq_icu_w32(i, ~0, LTQ_ICU_IM0_ISR);
16f70b56	370	}
171bb2f1 JC	371
	372	mips_cpu_irq_init();
	373
61fa969f JC	374	for (i = 0; i < MAX_IM; i++)
61fa969f JC	375	setup_irq(i + 2, &cascade);
171bb2f1 JC	376
	377	if (cpu_has_vint) {
	378	pr_info("Setting up vectored interrupts\n");
	379	set_vi_handler(2, ltq_hw0_irqdispatch);
	380	set_vi_handler(3, ltq_hw1_irqdispatch);
	381	set_vi_handler(4, ltq_hw2_irqdispatch);
	382	set_vi_handler(5, ltq_hw3_irqdispatch);
	383	set_vi_handler(6, ltq_hw4_irqdispatch);
	384	set_vi_handler(7, ltq_hw5_irqdispatch);
	385	}
	386
c2c9c788	387	ltq_domain = irq_domain_add_linear(node,
61fa969f	388	(MAX_IM * INT_NUM_IM_OFFSET) + MIPS_CPU_IRQ_CASCADE,
3645da02	389	&irq_domain_ops, 0);
171bb2f1	390
a8d096ef JC	391	#if defined(CONFIG_MIPS_MT_SMP)
	392	if (cpu_has_vint) {
	393	pr_info("Setting up IPI vectored interrupts\n");
	394	set_vi_handler(MIPS_CPU_IPI_RESCHED_IRQ, ltq_sw0_irqdispatch);
	395	set_vi_handler(MIPS_CPU_IPI_CALL_IRQ, ltq_sw1_irqdispatch);
	396	}
	397	arch_init_ipiirq(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ,
	398	&irq_resched);
	399	arch_init_ipiirq(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ, &irq_call);
	400	#endif
	401
171bb2f1 JC	402	#if !defined(CONFIG_MIPS_MT_SMP) && !defined(CONFIG_MIPS_MT_SMTC)
	403	set_c0_status(IE_IRQ0 \| IE_IRQ1 \| IE_IRQ2 \|
	404	IE_IRQ3 \| IE_IRQ4 \| IE_IRQ5);
	405	#else
	406	set_c0_status(IE_SW0 \| IE_SW1 \| IE_IRQ0 \| IE_IRQ1 \|
	407	IE_IRQ2 \| IE_IRQ3 \| IE_IRQ4 \| IE_IRQ5);
	408	#endif
59c11579 JC	409
	410	/* tell oprofile which irq to use */
	411	cp0_perfcount_irq = LTQ_PERF_IRQ;
c2c9c788 JC	412
	413	/*
	414	* if the timer irq is not one of the mips irqs we need to
	415	* create a mapping
	416	*/
	417	if (MIPS_CPU_TIMER_IRQ != 7)
	418	irq_create_mapping(ltq_domain, MIPS_CPU_TIMER_IRQ);
	419
3645da02	420	return 0;
171bb2f1 JC	421	}
	422
	423	unsigned int __cpuinit get_c0_compare_int(void)
	424	{
c2c9c788	425	return MIPS_CPU_TIMER_IRQ;
171bb2f1	426	}
3645da02 JC	427
	428	static struct of_device_id __initdata of_irq_ids[] = {
	429	{ .compatible = "lantiq,icu", .data = icu_of_init },
	430	{},
	431	};
	432
	433	void __init arch_init_irq(void)
	434	{
	435	of_irq_init(of_irq_ids);
	436	}