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1 | /* |
2 | * CS5536 General timer functions | |
3 | * | |
4 | * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology | |
5 | * Author: Yanhua, yanh@lemote.com | |
6 | * | |
7 | * Copyright (C) 2009 Lemote Inc. | |
f7a904df | 8 | * Author: Wu zhangjin, wuzhangjin@gmail.com |
916daba8 WZ |
9 | * |
10 | * Reference: AMD Geode(TM) CS5536 Companion Device Data Book | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify it | |
13 | * under the terms of the GNU General Public License as published by the | |
14 | * Free Software Foundation; either version 2 of the License, or (at your | |
15 | * option) any later version. | |
16 | */ | |
17 | ||
18 | #include <linux/io.h> | |
19 | #include <linux/init.h> | |
20 | #include <linux/module.h> | |
21 | #include <linux/jiffies.h> | |
22 | #include <linux/spinlock.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/clockchips.h> | |
25 | ||
26 | #include <asm/time.h> | |
27 | ||
28 | #include <cs5536/cs5536_mfgpt.h> | |
29 | ||
30 | DEFINE_SPINLOCK(mfgpt_lock); | |
31 | EXPORT_SYMBOL(mfgpt_lock); | |
32 | ||
33 | static u32 mfgpt_base; | |
34 | ||
35 | /* | |
36 | * Initialize the MFGPT timer. | |
37 | * | |
38 | * This is also called after resume to bring the MFGPT into operation again. | |
39 | */ | |
40 | ||
41 | /* disable counter */ | |
42 | void disable_mfgpt0_counter(void) | |
43 | { | |
44 | outw(inw(MFGPT0_SETUP) & 0x7fff, MFGPT0_SETUP); | |
45 | } | |
46 | EXPORT_SYMBOL(disable_mfgpt0_counter); | |
47 | ||
48 | /* enable counter, comparator2 to event mode, 14.318MHz clock */ | |
49 | void enable_mfgpt0_counter(void) | |
50 | { | |
51 | outw(0xe310, MFGPT0_SETUP); | |
52 | } | |
53 | EXPORT_SYMBOL(enable_mfgpt0_counter); | |
54 | ||
55 | static void init_mfgpt_timer(enum clock_event_mode mode, | |
56 | struct clock_event_device *evt) | |
57 | { | |
58 | spin_lock(&mfgpt_lock); | |
59 | ||
60 | switch (mode) { | |
61 | case CLOCK_EVT_MODE_PERIODIC: | |
62 | outw(COMPARE, MFGPT0_CMP2); /* set comparator2 */ | |
63 | outw(0, MFGPT0_CNT); /* set counter to 0 */ | |
64 | enable_mfgpt0_counter(); | |
65 | break; | |
66 | ||
67 | case CLOCK_EVT_MODE_SHUTDOWN: | |
68 | case CLOCK_EVT_MODE_UNUSED: | |
69 | if (evt->mode == CLOCK_EVT_MODE_PERIODIC || | |
70 | evt->mode == CLOCK_EVT_MODE_ONESHOT) | |
71 | disable_mfgpt0_counter(); | |
72 | break; | |
73 | ||
74 | case CLOCK_EVT_MODE_ONESHOT: | |
75 | /* The oneshot mode have very high deviation, Not use it! */ | |
76 | break; | |
77 | ||
78 | case CLOCK_EVT_MODE_RESUME: | |
79 | /* Nothing to do here */ | |
80 | break; | |
81 | } | |
82 | spin_unlock(&mfgpt_lock); | |
83 | } | |
84 | ||
85 | static struct clock_event_device mfgpt_clockevent = { | |
86 | .name = "mfgpt", | |
87 | .features = CLOCK_EVT_FEAT_PERIODIC, | |
88 | .set_mode = init_mfgpt_timer, | |
89 | .irq = CS5536_MFGPT_INTR, | |
90 | }; | |
91 | ||
92 | static irqreturn_t timer_interrupt(int irq, void *dev_id) | |
93 | { | |
94 | u32 basehi; | |
95 | ||
96 | /* | |
97 | * get MFGPT base address | |
98 | * | |
99 | * NOTE: do not remove me, it's need for the value of mfgpt_base is | |
100 | * variable | |
101 | */ | |
102 | _rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_MFGPT), &basehi, &mfgpt_base); | |
103 | ||
104 | /* ack */ | |
105 | outw(inw(MFGPT0_SETUP) | 0x4000, MFGPT0_SETUP); | |
106 | ||
107 | mfgpt_clockevent.event_handler(&mfgpt_clockevent); | |
108 | ||
109 | return IRQ_HANDLED; | |
110 | } | |
111 | ||
112 | static struct irqaction irq5 = { | |
113 | .handler = timer_interrupt, | |
8b5690f8 | 114 | .flags = IRQF_NOBALANCING | IRQF_TIMER, |
916daba8 WZ |
115 | .name = "timer" |
116 | }; | |
117 | ||
118 | /* | |
119 | * Initialize the conversion factor and the min/max deltas of the clock event | |
120 | * structure and register the clock event source with the framework. | |
121 | */ | |
122 | void __init setup_mfgpt0_timer(void) | |
123 | { | |
124 | u32 basehi; | |
125 | struct clock_event_device *cd = &mfgpt_clockevent; | |
126 | unsigned int cpu = smp_processor_id(); | |
127 | ||
128 | cd->cpumask = cpumask_of(cpu); | |
129 | clockevent_set_clock(cd, MFGPT_TICK_RATE); | |
130 | cd->max_delta_ns = clockevent_delta2ns(0xffff, cd); | |
131 | cd->min_delta_ns = clockevent_delta2ns(0xf, cd); | |
132 | ||
133 | /* Enable MFGPT0 Comparator 2 Output to the Interrupt Mapper */ | |
134 | _wrmsr(DIVIL_MSR_REG(MFGPT_IRQ), 0, 0x100); | |
135 | ||
136 | /* Enable Interrupt Gate 5 */ | |
137 | _wrmsr(DIVIL_MSR_REG(PIC_ZSEL_LOW), 0, 0x50000); | |
138 | ||
139 | /* get MFGPT base address */ | |
140 | _rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_MFGPT), &basehi, &mfgpt_base); | |
141 | ||
142 | clockevents_register_device(cd); | |
143 | ||
144 | setup_irq(CS5536_MFGPT_INTR, &irq5); | |
145 | } | |
146 | ||
147 | /* | |
148 | * Since the MFGPT overflows every tick, its not very useful | |
149 | * to just read by itself. So use jiffies to emulate a free | |
150 | * running counter: | |
151 | */ | |
152 | static cycle_t mfgpt_read(struct clocksource *cs) | |
153 | { | |
154 | unsigned long flags; | |
155 | int count; | |
156 | u32 jifs; | |
157 | static int old_count; | |
158 | static u32 old_jifs; | |
159 | ||
160 | spin_lock_irqsave(&mfgpt_lock, flags); | |
161 | /* | |
162 | * Although our caller may have the read side of xtime_lock, | |
163 | * this is now a seqlock, and we are cheating in this routine | |
164 | * by having side effects on state that we cannot undo if | |
165 | * there is a collision on the seqlock and our caller has to | |
166 | * retry. (Namely, old_jifs and old_count.) So we must treat | |
167 | * jiffies as volatile despite the lock. We read jiffies | |
168 | * before latching the timer count to guarantee that although | |
169 | * the jiffies value might be older than the count (that is, | |
170 | * the counter may underflow between the last point where | |
171 | * jiffies was incremented and the point where we latch the | |
172 | * count), it cannot be newer. | |
173 | */ | |
174 | jifs = jiffies; | |
175 | /* read the count */ | |
176 | count = inw(MFGPT0_CNT); | |
177 | ||
178 | /* | |
179 | * It's possible for count to appear to go the wrong way for this | |
180 | * reason: | |
181 | * | |
182 | * The timer counter underflows, but we haven't handled the resulting | |
183 | * interrupt and incremented jiffies yet. | |
184 | * | |
185 | * Previous attempts to handle these cases intelligently were buggy, so | |
186 | * we just do the simple thing now. | |
187 | */ | |
188 | if (count < old_count && jifs == old_jifs) | |
189 | count = old_count; | |
190 | ||
191 | old_count = count; | |
192 | old_jifs = jifs; | |
193 | ||
194 | spin_unlock_irqrestore(&mfgpt_lock, flags); | |
195 | ||
196 | return (cycle_t) (jifs * COMPARE) + count; | |
197 | } | |
198 | ||
199 | static struct clocksource clocksource_mfgpt = { | |
200 | .name = "mfgpt", | |
201 | .rating = 120, /* Functional for real use, but not desired */ | |
202 | .read = mfgpt_read, | |
203 | .mask = CLOCKSOURCE_MASK(32), | |
916daba8 WZ |
204 | }; |
205 | ||
206 | int __init init_mfgpt_clocksource(void) | |
207 | { | |
208 | if (num_possible_cpus() > 1) /* MFGPT does not scale! */ | |
209 | return 0; | |
210 | ||
75c4fd8c | 211 | return clocksource_register_hz(&clocksource_mfgpt, MFGPT_TICK_RATE); |
916daba8 WZ |
212 | } |
213 | ||
214 | arch_initcall(init_mfgpt_clocksource); |