projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| d788bfa9 HC |
1 | #include <loongson.h> |
| 2 | #include <irq.h> | |
| 3 | #include <linux/interrupt.h> | |
| 4 | #include <linux/module.h> | |
| 5 | ||
| 6 | #include <asm/irq_cpu.h> | |
| 7 | #include <asm/i8259.h> | |
| 8 | #include <asm/mipsregs.h> | |
| 9 | ||
| e7841be5 HC |
10 | #include "smp.h" |
| 11 | ||
| e292ccde | 12 | unsigned int ht_irq[] = {0, 1, 3, 4, 5, 6, 7, 8, 12, 14, 15}; |
| d788bfa9 HC |
13 | |
| 14 | static void ht_irqdispatch(void) | |
| 15 | { | |
| 16 | unsigned int i, irq; | |
| 17 | ||
| 18 | irq = LOONGSON_HT1_INT_VECTOR(0); | |
| 19 | LOONGSON_HT1_INT_VECTOR(0) = irq; /* Acknowledge the IRQs */ | |
| 20 | ||
| 21 | for (i = 0; i < ARRAY_SIZE(ht_irq); i++) { | |
| 22 | if (irq & (0x1 << ht_irq[i])) | |
| 23 | do_IRQ(ht_irq[i]); | |
| 24 | } | |
| 25 | } | |
| 26 | ||
| 27 | void mach_irq_dispatch(unsigned int pending) | |
| 28 | { | |
| 29 | if (pending & CAUSEF_IP7) | |
| 30 | do_IRQ(LOONGSON_TIMER_IRQ); | |
| 300459d5 HC |
31 | #if defined(CONFIG_SMP) |
| 32 | else if (pending & CAUSEF_IP6) | |
| 33 | loongson3_ipi_interrupt(NULL); | |
| 34 | #endif | |
| d788bfa9 HC |
35 | else if (pending & CAUSEF_IP3) |
| 36 | ht_irqdispatch(); | |
| 37 | else if (pending & CAUSEF_IP2) | |
| 38 | do_IRQ(LOONGSON_UART_IRQ); | |
| 39 | else { | |
| 40 | pr_err("%s : spurious interrupt\n", __func__); | |
| 41 | spurious_interrupt(); | |
| 42 | } | |
| 43 | } | |
| 44 | ||
| 45 | static struct irqaction cascade_irqaction = { | |
| 46 | .handler = no_action, | |
| 47 | .name = "cascade", | |
| 48 | }; | |
| 49 | ||
| 50 | static inline void mask_loongson_irq(struct irq_data *d) | |
| 51 | { | |
| 52 | clear_c0_status(0x100 << (d->irq - MIPS_CPU_IRQ_BASE)); | |
| 53 | irq_disable_hazard(); | |
| 300459d5 HC |
54 | |
| 55 | /* Workaround: UART IRQ may deliver to any core */ | |
| 56 | if (d->irq == LOONGSON_UART_IRQ) { | |
| 57 | int cpu = smp_processor_id(); | |
| ec0f8d3f HC |
58 | int node_id = cpu_logical_map(cpu) / loongson_sysconf.cores_per_node; |
| 59 | int core_id = cpu_logical_map(cpu) % loongson_sysconf.cores_per_node; | |
| e7841be5 HC |
60 | u64 intenclr_addr = smp_group[node_id] | |
| 61 | (u64)(&LOONGSON_INT_ROUTER_INTENCLR); | |
| 62 | u64 introuter_lpc_addr = smp_group[node_id] | | |
| 63 | (u64)(&LOONGSON_INT_ROUTER_LPC); | |
| 300459d5 | 64 | |
| e7841be5 HC |
65 | *(volatile u32 *)intenclr_addr = 1 << 10; |
| 66 | *(volatile u8 *)introuter_lpc_addr = 0x10 + (1<<core_id); | |
| 300459d5 | 67 | } |
| d788bfa9 HC |
68 | } |
| 69 | ||
| 70 | static inline void unmask_loongson_irq(struct irq_data *d) | |
| 71 | { | |
| 300459d5 HC |
72 | /* Workaround: UART IRQ may deliver to any core */ |
| 73 | if (d->irq == LOONGSON_UART_IRQ) { | |
| 74 | int cpu = smp_processor_id(); | |
| ec0f8d3f HC |
75 | int node_id = cpu_logical_map(cpu) / loongson_sysconf.cores_per_node; |
| 76 | int core_id = cpu_logical_map(cpu) % loongson_sysconf.cores_per_node; | |
| e7841be5 HC |
77 | u64 intenset_addr = smp_group[node_id] | |
| 78 | (u64)(&LOONGSON_INT_ROUTER_INTENSET); | |
| 79 | u64 introuter_lpc_addr = smp_group[node_id] | | |
| 80 | (u64)(&LOONGSON_INT_ROUTER_LPC); | |
| 300459d5 | 81 | |
| e7841be5 HC |
82 | *(volatile u32 *)intenset_addr = 1 << 10; |
| 83 | *(volatile u8 *)introuter_lpc_addr = 0x10 + (1<<core_id); | |
| 300459d5 HC |
84 | } |
| 85 | ||
| d788bfa9 HC |
86 | set_c0_status(0x100 << (d->irq - MIPS_CPU_IRQ_BASE)); |
| 87 | irq_enable_hazard(); | |
| 88 | } | |
| 89 | ||
| 90 | /* For MIPS IRQs which shared by all cores */ | |
| 91 | static struct irq_chip loongson_irq_chip = { | |
| 92 | .name = "Loongson", | |
| 93 | .irq_ack = mask_loongson_irq, | |
| 94 | .irq_mask = mask_loongson_irq, | |
| 95 | .irq_mask_ack = mask_loongson_irq, | |
| 96 | .irq_unmask = unmask_loongson_irq, | |
| 97 | .irq_eoi = unmask_loongson_irq, | |
| 98 | }; | |
| 99 | ||
| 100 | void irq_router_init(void) | |
| 101 | { | |
| 102 | int i; | |
| 103 | ||
| 104 | /* route LPC int to cpu core0 int 0 */ | |
| ec0f8d3f HC |
105 | LOONGSON_INT_ROUTER_LPC = |
| 106 | LOONGSON_INT_COREx_INTy(loongson_sysconf.boot_cpu_id, 0); | |
| d788bfa9 HC |
107 | /* route HT1 int0 ~ int7 to cpu core0 INT1*/ |
| 108 | for (i = 0; i < 8; i++) | |
| ec0f8d3f HC |
109 | LOONGSON_INT_ROUTER_HT1(i) = |
| 110 | LOONGSON_INT_COREx_INTy(loongson_sysconf.boot_cpu_id, 1); | |
| d788bfa9 HC |
111 | /* enable HT1 interrupt */ |
| 112 | LOONGSON_HT1_INTN_EN(0) = 0xffffffff; | |
| 113 | /* enable router interrupt intenset */ | |
| 114 | LOONGSON_INT_ROUTER_INTENSET = | |
| 115 | LOONGSON_INT_ROUTER_INTEN | (0xffff << 16) | 0x1 << 10; | |
| 116 | } | |
| 117 | ||
| 118 | void __init mach_init_irq(void) | |
| 119 | { | |
| 120 | clear_c0_status(ST0_IM | ST0_BEV); | |
| 121 | ||
| 122 | irq_router_init(); | |
| 123 | mips_cpu_irq_init(); | |
| 124 | init_i8259_irqs(); | |
| 125 | irq_set_chip_and_handler(LOONGSON_UART_IRQ, | |
| 126 | &loongson_irq_chip, handle_level_irq); | |
| 127 | ||
| 128 | /* setup HT1 irq */ | |
| 129 | setup_irq(LOONGSON_HT1_IRQ, &cascade_irqaction); | |
| 130 | ||
| 131 | set_c0_status(STATUSF_IP2 | STATUSF_IP6); | |
| 132 | } | |
| c4a987db HC |
133 | |
| 134 | #ifdef CONFIG_HOTPLUG_CPU | |
| 135 | ||
| 136 | void fixup_irqs(void) | |
| 137 | { | |
| 138 | irq_cpu_offline(); | |
| 139 | clear_c0_status(ST0_IM); | |
| 140 | } | |
| 141 | ||
| 142 | #endif |