Merge tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm...
[deliverable/linux.git] / arch / mips / math-emu / dp_add.c
CommitLineData
1da177e4
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1/* IEEE754 floating point arithmetic
2 * double precision: common utilities
3 */
4/*
5 * MIPS floating point support
6 * Copyright (C) 1994-2000 Algorithmics Ltd.
1da177e4 7 *
1da177e4
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8 * This program is free software; you can distribute it and/or modify it
9 * under the terms of the GNU General Public License (Version 2) as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 * for more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
3f7cac41 19 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
1da177e4
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20 */
21
1da177e4
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22#include "ieee754dp.h"
23
2209bcb1 24union ieee754dp ieee754dp_add(union ieee754dp x, union ieee754dp y)
1da177e4 25{
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26 int s;
27
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28 COMPXDP;
29 COMPYDP;
30
31 EXPLODEXDP;
32 EXPLODEYDP;
33
9e8bad1f 34 ieee754_clearcx();
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35
36 FLUSHXDP;
37 FLUSHYDP;
38
39 switch (CLPAIR(xc, yc)) {
1da177e4 40 case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_SNAN):
1da177e4
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41 case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_SNAN):
42 case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_SNAN):
43 case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_SNAN):
44 case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_SNAN):
d5afa7e9
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45 return ieee754dp_nanxcpt(y);
46
47 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_SNAN):
48 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_QNAN):
1da177e4
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49 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_ZERO):
50 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_NORM):
51 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_DNORM):
52 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_INF):
d5afa7e9 53 return ieee754dp_nanxcpt(x);
1da177e4
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54
55 case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_QNAN):
56 case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_QNAN):
57 case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_QNAN):
58 case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_QNAN):
59 return y;
60
61 case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_QNAN):
62 case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_ZERO):
63 case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_NORM):
64 case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_DNORM):
65 case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_INF):
66 return x;
67
68
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69 /*
70 * Infinity handling
71 */
1da177e4
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72 case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_INF):
73 if (xs == ys)
74 return x;
9e8bad1f 75 ieee754_setcx(IEEE754_INVALID_OPERATION);
90efba36 76 return ieee754dp_indef();
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77
78 case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_INF):
79 case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_INF):
80 case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_INF):
81 return y;
82
83 case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_ZERO):
84 case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_NORM):
85 case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_DNORM):
86 return x;
87
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88 /*
89 * Zero handling
90 */
1da177e4
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91 case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_ZERO):
92 if (xs == ys)
93 return x;
94 else
56a64733 95 return ieee754dp_zero(ieee754_csr.rm == FPU_CSR_RD);
1da177e4
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96
97 case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_ZERO):
98 case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_ZERO):
99 return x;
100
101 case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_NORM):
102 case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_DNORM):
103 return y;
104
105 case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_DNORM):
106 DPDNORMX;
107
108 /* FALL THROUGH */
109
110 case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_DNORM):
111 DPDNORMY;
112 break;
113
114 case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_NORM):
115 DPDNORMX;
116 break;
117
118 case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_NORM):
119 break;
120 }
121 assert(xm & DP_HIDDEN_BIT);
122 assert(ym & DP_HIDDEN_BIT);
123
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124 /*
125 * Provide guard,round and stick bit space.
126 */
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127 xm <<= 3;
128 ym <<= 3;
129
130 if (xe > ye) {
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131 /*
132 * Have to shift y fraction right to align.
1da177e4 133 */
3f7cac41 134 s = xe - ye;
1da177e4
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135 ym = XDPSRS(ym, s);
136 ye += s;
137 } else if (ye > xe) {
3f7cac41
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138 /*
139 * Have to shift x fraction right to align.
1da177e4 140 */
3f7cac41 141 s = ye - xe;
1da177e4
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142 xm = XDPSRS(xm, s);
143 xe += s;
144 }
145 assert(xe == ye);
146 assert(xe <= DP_EMAX);
147
148 if (xs == ys) {
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149 /*
150 * Generate 28 bit result of adding two 27 bit numbers
151 * leaving result in xm, xs and xe.
1da177e4
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152 */
153 xm = xm + ym;
1da177e4 154
ad8fb553 155 if (xm >> (DP_FBITS + 1 + 3)) { /* carry out */
1da177e4
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156 xm = XDPSRS1(xm);
157 xe++;
158 }
159 } else {
160 if (xm >= ym) {
161 xm = xm - ym;
1da177e4
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162 } else {
163 xm = ym - xm;
1da177e4
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164 xs = ys;
165 }
166 if (xm == 0)
56a64733 167 return ieee754dp_zero(ieee754_csr.rm == FPU_CSR_RD);
1da177e4 168
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169 /*
170 * Normalize to rounding precision.
171 */
ad8fb553 172 while ((xm >> (DP_FBITS + 3)) == 0) {
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173 xm <<= 1;
174 xe--;
175 }
1da177e4 176 }
90efba36
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177
178 return ieee754dp_format(xs, xe, xm);
1da177e4 179}
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