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MIPS: math-emu: Add support for the MIPS R6 SELNEZ FPU instruction
[deliverable/linux.git] / arch / mips / math-emu / ieee754.h
CommitLineData
1da177e4
LT		 1/*
2 * MIPS floating point support
3 * Copyright (C) 1994-2000 Algorithmics Ltd.
1da177e4 4 *
1da177e4
LT		 5 * This program is free software; you can distribute it and/or modify it
6 * under the terms of the GNU General Public License (Version 2) as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
3f7cac41 16 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
1da177e4 17 *
1da177e4
LT		 18 * Nov 7, 2000
19 * Modification to allow integration with Linux kernel
20 *
21 * Kevin D. Kissell, kevink@mips.com and Carsten Langgard, carstenl@mips.com
22 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
cd21dfcf 23 */
a663bf90
RB		 24#ifndef __ARCH_MIPS_MATH_EMU_IEEE754_H
25#define __ARCH_MIPS_MATH_EMU_IEEE754_H
1da177e4 26
cae55066 27#include <linux/compiler.h>
cd21dfcf 28#include <asm/byteorder.h>
e812a739 29#include <linux/kernel.h>
1da177e4 30#include <linux/types.h>
cd21dfcf 31#include <linux/sched.h>
f80cc08d 32#include <asm/bitfield.h>
1da177e4 33
2209bcb1 34union ieee754dp {
1da177e4 35 struct {
f80cc08d
RB		 36 __BITFIELD_FIELD(unsigned int sign:1,
37 __BITFIELD_FIELD(unsigned int bexp:11,
38 __BITFIELD_FIELD(u64 mant:52,
39 ;)))
49548b09 40 };
1da177e4 41 u64 bits;
2209bcb1 42};
1da177e4 43
2209bcb1 44union ieee754sp {
49548b09
RB		 45 struct {
46 __BITFIELD_FIELD(unsigned sign:1,
47 __BITFIELD_FIELD(unsigned bexp:8,
48 __BITFIELD_FIELD(unsigned mant:23,
49 ;)))
50 };
1da177e4 51 u32 bits;
2209bcb1 52};
1da177e4
LT		 53
54/*
55 * single precision (often aka float)
56*/
2209bcb1 57int ieee754sp_class(union ieee754sp x);
1da177e4 58
2209bcb1
RB		 59union ieee754sp ieee754sp_abs(union ieee754sp x);
60union ieee754sp ieee754sp_neg(union ieee754sp x);
1da177e4 61
2209bcb1
RB		 62union ieee754sp ieee754sp_add(union ieee754sp x, union ieee754sp y);
63union ieee754sp ieee754sp_sub(union ieee754sp x, union ieee754sp y);
64union ieee754sp ieee754sp_mul(union ieee754sp x, union ieee754sp y);
65union ieee754sp ieee754sp_div(union ieee754sp x, union ieee754sp y);
1da177e4 66
2209bcb1 67union ieee754sp ieee754sp_fint(int x);
2209bcb1 68union ieee754sp ieee754sp_flong(s64 x);
2209bcb1 69union ieee754sp ieee754sp_fdp(union ieee754dp x);
1da177e4 70
2209bcb1 71int ieee754sp_tint(union ieee754sp x);
2209bcb1 72s64 ieee754sp_tlong(union ieee754sp x);
1da177e4 73
2209bcb1 74int ieee754sp_cmp(union ieee754sp x, union ieee754sp y, int cop, int sig);
1da177e4 75
2209bcb1 76union ieee754sp ieee754sp_sqrt(union ieee754sp x);
1da177e4
LT		 77
78/*
79 * double precision (often aka double)
80*/
2209bcb1 81int ieee754dp_class(union ieee754dp x);
1da177e4 82
2209bcb1
RB		 83union ieee754dp ieee754dp_add(union ieee754dp x, union ieee754dp y);
84union ieee754dp ieee754dp_sub(union ieee754dp x, union ieee754dp y);
85union ieee754dp ieee754dp_mul(union ieee754dp x, union ieee754dp y);
86union ieee754dp ieee754dp_div(union ieee754dp x, union ieee754dp y);
1da177e4 87
2209bcb1
RB		 88union ieee754dp ieee754dp_abs(union ieee754dp x);
89union ieee754dp ieee754dp_neg(union ieee754dp x);
1da177e4 90
2209bcb1 91union ieee754dp ieee754dp_fint(int x);
2209bcb1 92union ieee754dp ieee754dp_flong(s64 x);
2209bcb1 93union ieee754dp ieee754dp_fsp(union ieee754sp x);
1da177e4 94
2209bcb1 95int ieee754dp_tint(union ieee754dp x);
2209bcb1 96s64 ieee754dp_tlong(union ieee754dp x);
1da177e4 97
2209bcb1 98int ieee754dp_cmp(union ieee754dp x, union ieee754dp y, int cop, int sig);
1da177e4 99
2209bcb1 100union ieee754dp ieee754dp_sqrt(union ieee754dp x);
1da177e4
LT		 101
102
103
104/* 5 types of floating point number
105*/
9e8bad1f
RB		 106enum {
107 IEEE754_CLASS_NORM = 0x00,
108 IEEE754_CLASS_ZERO = 0x01,
109 IEEE754_CLASS_DNORM = 0x02,
110 IEEE754_CLASS_INF = 0x03,
111 IEEE754_CLASS_SNAN = 0x04,
112 IEEE754_CLASS_QNAN = 0x05,
113};
1da177e4
LT		 114
115/* exception numbers */
116#define IEEE754_INEXACT 0x01
117#define IEEE754_UNDERFLOW 0x02
118#define IEEE754_OVERFLOW 0x04
119#define IEEE754_ZERO_DIVIDE 0x08
120#define IEEE754_INVALID_OPERATION 0x10
121
122/* cmp operators
123*/
124#define IEEE754_CLT 0x01
125#define IEEE754_CEQ 0x02
126#define IEEE754_CGT 0x04
127#define IEEE754_CUN 0x08
128
cd21dfcf
RB		 129/*
130 * The control status register
131 */
132struct _ieee754_csr {
f1f3b7eb
MR		 133 __BITFIELD_FIELD(unsigned fcc:7, /* condition[7:1] */
134 __BITFIELD_FIELD(unsigned nod:1, /* set 1 for no denormals */
135 __BITFIELD_FIELD(unsigned c:1, /* condition[0] */
136 __BITFIELD_FIELD(unsigned pad0:3,
137 __BITFIELD_FIELD(unsigned abs2008:1, /* IEEE 754-2008 ABS/NEG.fmt */
138 __BITFIELD_FIELD(unsigned nan2008:1, /* IEEE 754-2008 NaN mode */
f80cc08d
RB		 139 __BITFIELD_FIELD(unsigned cx:6, /* exceptions this operation */
140 __BITFIELD_FIELD(unsigned mx:5, /* exception enable mask */
141 __BITFIELD_FIELD(unsigned sx:5, /* exceptions total */
142 __BITFIELD_FIELD(unsigned rm:2, /* current rounding mode */
f1f3b7eb 143 ;))))))))))
1da177e4 144};
eae89076 145#define ieee754_csr (*(struct _ieee754_csr *)(&current->thread.fpu.fcr31))
1da177e4 146
cd21dfcf 147static inline unsigned ieee754_getrm(void)
1da177e4
LT		 148{
149 return (ieee754_csr.rm);
150}
cd21dfcf 151static inline unsigned ieee754_setrm(unsigned rm)
1da177e4
LT		 152{
153 return (ieee754_csr.rm = rm);
154}
155
156/*
157 * get current exceptions
158 */
cd21dfcf 159static inline unsigned ieee754_getcx(void)
1da177e4
LT		 160{
161 return (ieee754_csr.cx);
162}
163
164/* test for current exception condition
165 */
cd21dfcf 166static inline int ieee754_cxtest(unsigned n)
1da177e4
LT		 167{
168 return (ieee754_csr.cx & n);
169}
170
171/*
172 * get sticky exceptions
173 */
cd21dfcf 174static inline unsigned ieee754_getsx(void)
1da177e4
LT		 175{
176 return (ieee754_csr.sx);
177}
178
179/* clear sticky conditions
180*/
cd21dfcf 181static inline unsigned ieee754_clrsx(void)
1da177e4
LT		 182{
183 return (ieee754_csr.sx = 0);
184}
185
186/* test for sticky exception condition
187 */
cd21dfcf 188static inline int ieee754_sxtest(unsigned n)
1da177e4
LT		 189{
190 return (ieee754_csr.sx & n);
191}
192
193/* debugging */
2209bcb1
RB		 194union ieee754sp ieee754sp_dump(char *s, union ieee754sp x);
195union ieee754dp ieee754dp_dump(char *s, union ieee754dp x);
1da177e4 196
1796ec77
MR		 197#define IEEE754_SPCVAL_PZERO 0 /* +0.0 */
198#define IEEE754_SPCVAL_NZERO 1 /* -0.0 */
199#define IEEE754_SPCVAL_PONE 2 /* +1.0 */
200#define IEEE754_SPCVAL_NONE 3 /* -1.0 */
201#define IEEE754_SPCVAL_PTEN 4 /* +10.0 */
202#define IEEE754_SPCVAL_NTEN 5 /* -10.0 */
203#define IEEE754_SPCVAL_PINFINITY 6 /* +inf */
204#define IEEE754_SPCVAL_NINFINITY 7 /* -inf */
205#define IEEE754_SPCVAL_INDEF 8 /* quiet NaN */
206#define IEEE754_SPCVAL_PMAX 9 /* +max norm */
207#define IEEE754_SPCVAL_NMAX 10 /* -max norm */
208#define IEEE754_SPCVAL_PMIN 11 /* +min norm */
209#define IEEE754_SPCVAL_NMIN 12 /* -min norm */
210#define IEEE754_SPCVAL_PMIND 13 /* +min denorm */
211#define IEEE754_SPCVAL_NMIND 14 /* -min denorm */
212#define IEEE754_SPCVAL_P1E31 15 /* + 1.0e31 */
213#define IEEE754_SPCVAL_P1E63 16 /* + 1.0e63 */
1da177e4 214
49548b09
RB		 215extern const union ieee754dp __ieee754dp_spcvals[];
216extern const union ieee754sp __ieee754sp_spcvals[];
2209bcb1
RB		 217#define ieee754dp_spcvals ((const union ieee754dp *)__ieee754dp_spcvals)
218#define ieee754sp_spcvals ((const union ieee754sp *)__ieee754sp_spcvals)
1da177e4 219
cd21dfcf
RB		 220/*
221 * Return infinity with given sign
222 */
223#define ieee754dp_inf(sn) (ieee754dp_spcvals[IEEE754_SPCVAL_PINFINITY+(sn)])
224#define ieee754dp_zero(sn) (ieee754dp_spcvals[IEEE754_SPCVAL_PZERO+(sn)])
225#define ieee754dp_one(sn) (ieee754dp_spcvals[IEEE754_SPCVAL_PONE+(sn)])
226#define ieee754dp_ten(sn) (ieee754dp_spcvals[IEEE754_SPCVAL_PTEN+(sn)])
227#define ieee754dp_indef() (ieee754dp_spcvals[IEEE754_SPCVAL_INDEF])
228#define ieee754dp_max(sn) (ieee754dp_spcvals[IEEE754_SPCVAL_PMAX+(sn)])
229#define ieee754dp_min(sn) (ieee754dp_spcvals[IEEE754_SPCVAL_PMIN+(sn)])
230#define ieee754dp_mind(sn) (ieee754dp_spcvals[IEEE754_SPCVAL_PMIND+(sn)])
231#define ieee754dp_1e31() (ieee754dp_spcvals[IEEE754_SPCVAL_P1E31])
232#define ieee754dp_1e63() (ieee754dp_spcvals[IEEE754_SPCVAL_P1E63])
233
234#define ieee754sp_inf(sn) (ieee754sp_spcvals[IEEE754_SPCVAL_PINFINITY+(sn)])
235#define ieee754sp_zero(sn) (ieee754sp_spcvals[IEEE754_SPCVAL_PZERO+(sn)])
236#define ieee754sp_one(sn) (ieee754sp_spcvals[IEEE754_SPCVAL_PONE+(sn)])
237#define ieee754sp_ten(sn) (ieee754sp_spcvals[IEEE754_SPCVAL_PTEN+(sn)])
238#define ieee754sp_indef() (ieee754sp_spcvals[IEEE754_SPCVAL_INDEF])
239#define ieee754sp_max(sn) (ieee754sp_spcvals[IEEE754_SPCVAL_PMAX+(sn)])
240#define ieee754sp_min(sn) (ieee754sp_spcvals[IEEE754_SPCVAL_PMIN+(sn)])
241#define ieee754sp_mind(sn) (ieee754sp_spcvals[IEEE754_SPCVAL_PMIND+(sn)])
242#define ieee754sp_1e31() (ieee754sp_spcvals[IEEE754_SPCVAL_P1E31])
243#define ieee754sp_1e63() (ieee754sp_spcvals[IEEE754_SPCVAL_P1E63])
244
245/*
246 * Indefinite integer value
247 */
e812a739
RB		 248static inline int ieee754si_indef(void)
249{
250 return INT_MAX;
251}
252
253static inline s64 ieee754di_indef(void)
254{
255 return S64_MAX;
256}
1da177e4 257
1da177e4
LT		 258/* result types for xctx.rt */
259#define IEEE754_RT_SP 0
260#define IEEE754_RT_DP 1
261#define IEEE754_RT_XP 2
262#define IEEE754_RT_SI 3
263#define IEEE754_RT_DI 4
264
1da177e4
LT		 265/* compat */
266#define ieee754dp_fix(x) ieee754dp_tint(x)
267#define ieee754sp_fix(x) ieee754sp_tint(x)
a663bf90
RB		 268
269#endif /* __ARCH_MIPS_MATH_EMU_IEEE754_H */
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