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1da177e4 LT |
1 | /* |
2 | * Carsten Langgaard, carstenl@mips.com | |
3 | * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. | |
4 | * | |
5 | * This program is free software; you can distribute it and/or modify it | |
6 | * under the terms of the GNU General Public License (Version 2) as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 | * for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along | |
15 | * with this program; if not, write to the Free Software Foundation, Inc., | |
16 | * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. | |
17 | * | |
18 | * Setting up the clock on the MIPS boards. | |
19 | */ | |
20 | ||
21 | #include <linux/types.h> | |
22 | #include <linux/config.h> | |
23 | #include <linux/init.h> | |
24 | #include <linux/kernel_stat.h> | |
25 | #include <linux/sched.h> | |
26 | #include <linux/spinlock.h> | |
27 | #include <linux/interrupt.h> | |
28 | #include <linux/time.h> | |
29 | #include <linux/timex.h> | |
30 | #include <linux/mc146818rtc.h> | |
31 | ||
32 | #include <asm/mipsregs.h> | |
41c594ab | 33 | #include <asm/mipsmtregs.h> |
1da177e4 | 34 | #include <asm/ptrace.h> |
e01402b1 RB |
35 | #include <asm/hardirq.h> |
36 | #include <asm/irq.h> | |
1da177e4 LT |
37 | #include <asm/div64.h> |
38 | #include <asm/cpu.h> | |
39 | #include <asm/time.h> | |
40 | #include <asm/mc146818-time.h> | |
e01402b1 | 41 | #include <asm/msc01_ic.h> |
1da177e4 LT |
42 | |
43 | #include <asm/mips-boards/generic.h> | |
44 | #include <asm/mips-boards/prom.h> | |
e01402b1 RB |
45 | #include <asm/mips-boards/maltaint.h> |
46 | #include <asm/mc146818-time.h> | |
1da177e4 LT |
47 | |
48 | unsigned long cpu_khz; | |
49 | ||
1da177e4 LT |
50 | #if defined(CONFIG_MIPS_ATLAS) |
51 | static char display_string[] = " LINUX ON ATLAS "; | |
52 | #endif | |
53 | #if defined(CONFIG_MIPS_MALTA) | |
41c594ab RB |
54 | #if defined(CONFIG_MIPS_MT_SMTC) |
55 | static char display_string[] = " SMTC LINUX ON MALTA "; | |
56 | #else | |
1da177e4 | 57 | static char display_string[] = " LINUX ON MALTA "; |
41c594ab | 58 | #endif /* CONFIG_MIPS_MT_SMTC */ |
1da177e4 LT |
59 | #endif |
60 | #if defined(CONFIG_MIPS_SEAD) | |
61 | static char display_string[] = " LINUX ON SEAD "; | |
62 | #endif | |
41c594ab | 63 | static unsigned int display_count; |
1da177e4 LT |
64 | #define MAX_DISPLAY_COUNT (sizeof(display_string) - 8) |
65 | ||
41c594ab RB |
66 | #define CPUCTR_IMASKBIT (0x100 << MIPSCPU_INT_CPUCTR) |
67 | ||
68 | static unsigned int timer_tick_count; | |
e01402b1 | 69 | static int mips_cpu_timer_irq; |
41c594ab | 70 | extern void smtc_timer_broadcast(int); |
1da177e4 | 71 | |
340ee4b9 RB |
72 | static inline void scroll_display_message(void) |
73 | { | |
74 | if ((timer_tick_count++ % HZ) == 0) { | |
75 | mips_display_message(&display_string[display_count++]); | |
76 | if (display_count == MAX_DISPLAY_COUNT) | |
77 | display_count = 0; | |
78 | } | |
79 | } | |
80 | ||
e01402b1 | 81 | static void mips_timer_dispatch (struct pt_regs *regs) |
1da177e4 | 82 | { |
e01402b1 RB |
83 | do_IRQ (mips_cpu_timer_irq, regs); |
84 | } | |
85 | ||
41c594ab RB |
86 | /* |
87 | * Redeclare until I get around mopping the timer code insanity on MIPS. | |
88 | */ | |
ba339c03 RB |
89 | extern int null_perf_irq(struct pt_regs *regs); |
90 | ||
91 | extern int (*perf_irq)(struct pt_regs *regs); | |
92 | ||
e01402b1 RB |
93 | irqreturn_t mips_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs) |
94 | { | |
340ee4b9 | 95 | int cpu = smp_processor_id(); |
41c594ab RB |
96 | int r2 = cpu_has_mips_r2; |
97 | ||
98 | #ifdef CONFIG_MIPS_MT_SMTC | |
99 | /* | |
100 | * In an SMTC system, one Count/Compare set exists per VPE. | |
101 | * Which TC within a VPE gets the interrupt is essentially | |
102 | * random - we only know that it shouldn't be one with | |
103 | * IXMT set. Whichever TC gets the interrupt needs to | |
104 | * send special interprocessor interrupts to the other | |
105 | * TCs to make sure that they schedule, etc. | |
106 | * | |
107 | * That code is specific to the SMTC kernel, not to | |
108 | * the a particular platform, so it's invoked from | |
109 | * the general MIPS timer_interrupt routine. | |
110 | */ | |
111 | ||
112 | /* | |
113 | * DVPE is necessary so long as cross-VPE interrupts | |
114 | * are done via read-modify-write of Cause register. | |
115 | */ | |
116 | int vpflags = dvpe(); | |
117 | write_c0_compare (read_c0_count() - 1); | |
118 | clear_c0_cause(CPUCTR_IMASKBIT); | |
119 | evpe(vpflags); | |
120 | ||
121 | if (cpu_data[cpu].vpe_id == 0) { | |
122 | timer_interrupt(irq, dev_id, regs); | |
123 | scroll_display_message(); | |
124 | } else | |
125 | write_c0_compare (read_c0_count() + ( mips_hpt_frequency/HZ)); | |
126 | smtc_timer_broadcast(cpu_data[cpu].vpe_id); | |
340ee4b9 | 127 | |
41c594ab RB |
128 | if (cpu != 0) |
129 | /* | |
130 | * Other CPUs should do profiling and process accounting | |
131 | */ | |
132 | local_timer_interrupt(irq, dev_id, regs); | |
133 | ||
134 | #else /* CONFIG_MIPS_MT_SMTC */ | |
340ee4b9 RB |
135 | if (cpu == 0) { |
136 | /* | |
ba339c03 RB |
137 | * CPU 0 handles the global timer interrupt job and process |
138 | * accounting resets count/compare registers to trigger next | |
139 | * timer int. | |
340ee4b9 | 140 | */ |
ba339c03 RB |
141 | if (!r2 || (read_c0_cause() & (1 << 26))) |
142 | if (perf_irq(regs)) | |
143 | goto out; | |
144 | ||
145 | /* we keep interrupt disabled all the time */ | |
146 | if (!r2 || (read_c0_cause() & (1 << 30))) | |
147 | timer_interrupt(irq, NULL, regs); | |
148 | ||
340ee4b9 | 149 | scroll_display_message(); |
11e6df65 | 150 | } else { |
340ee4b9 RB |
151 | /* Everyone else needs to reset the timer int here as |
152 | ll_local_timer_interrupt doesn't */ | |
153 | /* | |
154 | * FIXME: need to cope with counter underflow. | |
155 | * More support needs to be added to kernel/time for | |
156 | * counter/timer interrupts on multiple CPU's | |
157 | */ | |
41c594ab RB |
158 | write_c0_compare(read_c0_count() + (mips_hpt_frequency/HZ)); |
159 | ||
340ee4b9 | 160 | /* |
41c594ab | 161 | * Other CPUs should do profiling and process accounting |
340ee4b9 | 162 | */ |
41c594ab | 163 | local_timer_interrupt(irq, dev_id, regs); |
340ee4b9 | 164 | } |
41c594ab | 165 | #endif /* CONFIG_MIPS_MT_SMTC */ |
340ee4b9 | 166 | |
ba339c03 | 167 | out: |
340ee4b9 | 168 | return IRQ_HANDLED; |
1da177e4 LT |
169 | } |
170 | ||
171 | /* | |
172 | * Estimate CPU frequency. Sets mips_counter_frequency as a side-effect | |
173 | */ | |
174 | static unsigned int __init estimate_cpu_frequency(void) | |
175 | { | |
176 | unsigned int prid = read_c0_prid() & 0xffff00; | |
177 | unsigned int count; | |
178 | ||
41c594ab | 179 | #if defined(CONFIG_MIPS_SEAD) || defined(CONFIG_MIPS_SIM) |
1da177e4 LT |
180 | /* |
181 | * The SEAD board doesn't have a real time clock, so we can't | |
182 | * really calculate the timer frequency | |
183 | * For now we hardwire the SEAD board frequency to 12MHz. | |
184 | */ | |
42a3b4f2 | 185 | |
1da177e4 LT |
186 | if ((prid == (PRID_COMP_MIPS | PRID_IMP_20KC)) || |
187 | (prid == (PRID_COMP_MIPS | PRID_IMP_25KF))) | |
188 | count = 12000000; | |
189 | else | |
190 | count = 6000000; | |
191 | #endif | |
192 | #if defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_MALTA) | |
193 | unsigned int flags; | |
194 | ||
195 | local_irq_save(flags); | |
196 | ||
197 | /* Start counter exactly on falling edge of update flag */ | |
198 | while (CMOS_READ(RTC_REG_A) & RTC_UIP); | |
199 | while (!(CMOS_READ(RTC_REG_A) & RTC_UIP)); | |
200 | ||
201 | /* Start r4k counter. */ | |
202 | write_c0_count(0); | |
203 | ||
204 | /* Read counter exactly on falling edge of update flag */ | |
205 | while (CMOS_READ(RTC_REG_A) & RTC_UIP); | |
206 | while (!(CMOS_READ(RTC_REG_A) & RTC_UIP)); | |
207 | ||
208 | count = read_c0_count(); | |
209 | ||
210 | /* restore interrupts */ | |
211 | local_irq_restore(flags); | |
212 | #endif | |
213 | ||
214 | mips_hpt_frequency = count; | |
215 | if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) && | |
216 | (prid != (PRID_COMP_MIPS | PRID_IMP_25KF))) | |
217 | count *= 2; | |
218 | ||
219 | count += 5000; /* round */ | |
220 | count -= count%10000; | |
221 | ||
222 | return count; | |
223 | } | |
224 | ||
225 | unsigned long __init mips_rtc_get_time(void) | |
226 | { | |
227 | return mc146818_get_cmos_time(); | |
228 | } | |
229 | ||
230 | void __init mips_time_init(void) | |
231 | { | |
232 | unsigned int est_freq, flags; | |
233 | ||
234 | local_irq_save(flags); | |
235 | ||
1da177e4 LT |
236 | /* Set Data mode - binary. */ |
237 | CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL); | |
1da177e4 LT |
238 | |
239 | est_freq = estimate_cpu_frequency (); | |
240 | ||
241 | printk("CPU frequency %d.%02d MHz\n", est_freq/1000000, | |
242 | (est_freq%1000000)*100/1000000); | |
243 | ||
244 | cpu_khz = est_freq / 1000; | |
245 | ||
246 | local_irq_restore(flags); | |
247 | } | |
248 | ||
249 | void __init mips_timer_setup(struct irqaction *irq) | |
250 | { | |
e01402b1 RB |
251 | if (cpu_has_veic) { |
252 | set_vi_handler (MSC01E_INT_CPUCTR, mips_timer_dispatch); | |
253 | mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR; | |
254 | } | |
255 | else { | |
256 | if (cpu_has_vint) | |
257 | set_vi_handler (MIPSCPU_INT_CPUCTR, mips_timer_dispatch); | |
258 | mips_cpu_timer_irq = MIPSCPU_INT_BASE + MIPSCPU_INT_CPUCTR; | |
259 | } | |
260 | ||
261 | ||
1da177e4 | 262 | /* we are using the cpu counter for timer interrupts */ |
e01402b1 | 263 | irq->handler = mips_timer_interrupt; /* we use our own handler */ |
41c594ab RB |
264 | #ifdef CONFIG_MIPS_MT_SMTC |
265 | setup_irq_smtc(mips_cpu_timer_irq, irq, CPUCTR_IMASKBIT); | |
266 | #else | |
e01402b1 | 267 | setup_irq(mips_cpu_timer_irq, irq); |
41c594ab | 268 | #endif /* CONFIG_MIPS_MT_SMTC */ |
e01402b1 | 269 | |
340ee4b9 RB |
270 | #ifdef CONFIG_SMP |
271 | /* irq_desc(riptor) is a global resource, when the interrupt overlaps | |
272 | on seperate cpu's the first one tries to handle the second interrupt. | |
273 | The effect is that the int remains disabled on the second cpu. | |
274 | Mark the interrupt with IRQ_PER_CPU to avoid any confusion */ | |
275 | irq_desc[mips_cpu_timer_irq].status |= IRQ_PER_CPU; | |
276 | #endif | |
1da177e4 LT |
277 | |
278 | /* to generate the first timer interrupt */ | |
279 | write_c0_compare (read_c0_count() + mips_hpt_frequency/HZ); | |
1da177e4 | 280 | } |