[deliverable/linux.git] / arch / mips / mips-boards / malta / malta_int.c

/*
 * Carsten Langgaard, carstenl@mips.com
 * Copyright (C) 2000, 2001, 2004 MIPS Technologies, Inc.
 * Copyright (C) 2001 Ralf Baechle
 *
 *  This program is free software; you can distribute it and/or modify it
 *  under the terms of the GNU General Public License (Version 2) as
 *  published by the Free Software Foundation.
 *
 *  This program is distributed in the hope it will be useful, but WITHOUT
 *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 *  for more details.
 *
 *  You should have received a copy of the GNU General Public License along
 *  with this program; if not, write to the Free Software Foundation, Inc.,
 *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
 *
 * Routines for generic manipulation of the interrupts found on the MIPS
 * Malta board.
 * The interrupt controller is located in the South Bridge a PIIX4 device
 * with two internal 82C95 interrupt controllers.
 */
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/sched.h>
#include <linux/slab.h>
#include <linux/interrupt.h>
#include <linux/kernel_stat.h>
#include <linux/random.h>

#include <asm/i8259.h>
#include <asm/irq_cpu.h>
#include <asm/io.h>
#include <asm/mips-boards/malta.h>
#include <asm/mips-boards/maltaint.h>
#include <asm/mips-boards/piix4.h>
#include <asm/gt64120.h>
#include <asm/mips-boards/generic.h>
#include <asm/mips-boards/msc01_pci.h>
#include <asm/msc01_ic.h>

extern void mips_timer_interrupt(void);

static DEFINE_SPINLOCK(mips_irq_lock);

static inline int mips_pcibios_iack(void)
{
	int irq;
        u32 dummy;

	/*
	 * Determine highest priority pending interrupt by performing
	 * a PCI Interrupt Acknowledge cycle.
	 */
	switch(mips_revision_corid) {
	case MIPS_REVISION_CORID_CORE_MSC:
	case MIPS_REVISION_CORID_CORE_FPGA2:
	case MIPS_REVISION_CORID_CORE_FPGA3:
	case MIPS_REVISION_CORID_CORE_EMUL_MSC:
	        MSC_READ(MSC01_PCI_IACK, irq);
		irq &= 0xff;
		break;
	case MIPS_REVISION_CORID_QED_RM5261:
	case MIPS_REVISION_CORID_CORE_LV:
	case MIPS_REVISION_CORID_CORE_FPGA:
	case MIPS_REVISION_CORID_CORE_FPGAR2:
		irq = GT_READ(GT_PCI0_IACK_OFS);
		irq &= 0xff;
		break;
	case MIPS_REVISION_CORID_BONITO64:
	case MIPS_REVISION_CORID_CORE_20K:
	case MIPS_REVISION_CORID_CORE_EMUL_BON:
		/* The following will generate a PCI IACK cycle on the
		 * Bonito controller. It's a little bit kludgy, but it
		 * was the easiest way to implement it in hardware at
		 * the given time.
		 */
		BONITO_PCIMAP_CFG = 0x20000;

		/* Flush Bonito register block */
		dummy = BONITO_PCIMAP_CFG;
		iob();    /* sync */

		irq = *(volatile u32 *)(_pcictrl_bonito_pcicfg);
		iob();    /* sync */
		irq &= 0xff;
		BONITO_PCIMAP_CFG = 0;
		break;
	default:
	        printk("Unknown Core card, don't know the system controller.\n");
		return -1;
	}
	return irq;
}

static inline int get_int(void)
{
	unsigned long flags;
	int irq;
	spin_lock_irqsave(&mips_irq_lock, flags);

	irq = mips_pcibios_iack();

	/*
	 * The only way we can decide if an interrupt is spurious
	 * is by checking the 8259 registers.  This needs a spinlock
	 * on an SMP system,  so leave it up to the generic code...
	 */

	spin_unlock_irqrestore(&mips_irq_lock, flags);

	return irq;
}

static void malta_hw0_irqdispatch(struct pt_regs *regs)
{
	int irq;

	irq = get_int();
	if (irq < 0)
		return;  /* interrupt has already been cleared */

	do_IRQ(MALTA_INT_BASE+irq, regs);
}

void corehi_irqdispatch(struct pt_regs *regs)
{
	unsigned int intrcause,datalo,datahi;
        unsigned int pcimstat, intisr, inten, intpol, intedge, intsteer, pcicmd, pcibadaddr;

        printk("CoreHI interrupt, shouldn't happen, so we die here!!!\n");
        printk("epc   : %08lx\nStatus: %08lx\nCause : %08lx\nbadVaddr : %08lx\n"
, regs->cp0_epc, regs->cp0_status, regs->cp0_cause, regs->cp0_badvaddr);

	/* Read all the registers and then print them as there is a
	   problem with interspersed printk's upsetting the Bonito controller.
	   Do it for the others too.
	*/

        switch(mips_revision_corid) {
        case MIPS_REVISION_CORID_CORE_MSC:
        case MIPS_REVISION_CORID_CORE_FPGA2:
        case MIPS_REVISION_CORID_CORE_FPGA3:
        case MIPS_REVISION_CORID_CORE_EMUL_MSC:
                ll_msc_irq(regs);
                break;
        case MIPS_REVISION_CORID_QED_RM5261:
        case MIPS_REVISION_CORID_CORE_LV:
        case MIPS_REVISION_CORID_CORE_FPGA:
        case MIPS_REVISION_CORID_CORE_FPGAR2:
                intrcause = GT_READ(GT_INTRCAUSE_OFS);
                datalo = GT_READ(GT_CPUERR_ADDRLO_OFS);
                datahi = GT_READ(GT_CPUERR_ADDRHI_OFS);
                printk("GT_INTRCAUSE = %08x\n", intrcause);
                printk("GT_CPUERR_ADDR = %02x%08x\n", datahi, datalo);
                break;
        case MIPS_REVISION_CORID_BONITO64:
        case MIPS_REVISION_CORID_CORE_20K:
        case MIPS_REVISION_CORID_CORE_EMUL_BON:
                pcibadaddr = BONITO_PCIBADADDR;
                pcimstat = BONITO_PCIMSTAT;
                intisr = BONITO_INTISR;
                inten = BONITO_INTEN;
                intpol = BONITO_INTPOL;
                intedge = BONITO_INTEDGE;
                intsteer = BONITO_INTSTEER;
                pcicmd = BONITO_PCICMD;
                printk("BONITO_INTISR = %08x\n", intisr);
                printk("BONITO_INTEN = %08x\n", inten);
                printk("BONITO_INTPOL = %08x\n", intpol);
                printk("BONITO_INTEDGE = %08x\n", intedge);
                printk("BONITO_INTSTEER = %08x\n", intsteer);
                printk("BONITO_PCICMD = %08x\n", pcicmd);
                printk("BONITO_PCIBADADDR = %08x\n", pcibadaddr);
                printk("BONITO_PCIMSTAT = %08x\n", pcimstat);
                break;
        }

        /* We die here*/
        die("CoreHi interrupt", regs);
}

static inline int clz(unsigned long x)
{
	__asm__ (
	"	.set	push					\n"
	"	.set	mips32					\n"
	"	clz	%0, %1					\n"
	"	.set	pop					\n"
	: "=r" (x)
	: "r" (x));

	return x;
}

/*
 * Version of ffs that only looks at bits 12..15.
 */
static inline unsigned int irq_ffs(unsigned int pending)
{
#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
	return -clz(pending) + 31 - CAUSEB_IP;
#else
	unsigned int a0 = 7;
	unsigned int t0;

	t0 = s0 & 0xf000;
	t0 = t0 < 1;
	t0 = t0 << 2;
	a0 = a0 - t0;
	s0 = s0 << t0;

	t0 = s0 & 0xc000;
	t0 = t0 < 1;
	t0 = t0 << 1;
	a0 = a0 - t0;
	s0 = s0 << t0;

	t0 = s0 & 0x8000;
	t0 = t0 < 1;
	//t0 = t0 << 2;
	a0 = a0 - t0;
	//s0 = s0 << t0;

	return a0;
#endif
}

/*
 * IRQs on the Malta board look basically (barring software IRQs which we
 * don't use at all and all external interrupt sources are combined together
 * on hardware interrupt 0 (MIPS IRQ 2)) like:
 *
 *	MIPS IRQ	Source
 *      --------        ------
 *             0	Software (ignored)
 *             1        Software (ignored)
 *             2        Combined hardware interrupt (hw0)
 *             3        Hardware (ignored)
 *             4        Hardware (ignored)
 *             5        Hardware (ignored)
 *             6        Hardware (ignored)
 *             7        R4k timer (what we use)
 *
 * We handle the IRQ according to _our_ priority which is:
 *
 * Highest ----     R4k Timer
 * Lowest  ----     Combined hardware interrupt
 *
 * then we just return, if multiple IRQs are pending then we will just take
 * another exception, big deal.
 */

asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
{
	unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
	int irq;

	irq = irq_ffs(pending);

	if (irq == MIPSCPU_INT_I8259A)
		malta_hw0_irqdispatch(regs);
	else if (irq > 0)
		do_IRQ(MIPSCPU_INT_BASE + irq, regs);
	else
		spurious_interrupt(regs);
}

static struct irqaction i8259irq = {
	.handler = no_action,
	.name = "XT-PIC cascade"
};

static struct irqaction corehi_irqaction = {
	.handler = no_action,
	.name = "CoreHi"
};

msc_irqmap_t __initdata msc_irqmap[] = {
	{MSC01C_INT_TMR,		MSC01_IRQ_EDGE, 0},
	{MSC01C_INT_PCI,		MSC01_IRQ_LEVEL, 0},
};
int __initdata msc_nr_irqs = sizeof(msc_irqmap)/sizeof(msc_irqmap_t);

msc_irqmap_t __initdata msc_eicirqmap[] = {
	{MSC01E_INT_SW0,		MSC01_IRQ_LEVEL, 0},
	{MSC01E_INT_SW1,		MSC01_IRQ_LEVEL, 0},
	{MSC01E_INT_I8259A,		MSC01_IRQ_LEVEL, 0},
	{MSC01E_INT_SMI,		MSC01_IRQ_LEVEL, 0},
	{MSC01E_INT_COREHI,		MSC01_IRQ_LEVEL, 0},
	{MSC01E_INT_CORELO,		MSC01_IRQ_LEVEL, 0},
	{MSC01E_INT_TMR,		MSC01_IRQ_EDGE, 0},
	{MSC01E_INT_PCI,		MSC01_IRQ_LEVEL, 0},
	{MSC01E_INT_PERFCTR,		MSC01_IRQ_LEVEL, 0},
	{MSC01E_INT_CPUCTR,		MSC01_IRQ_LEVEL, 0}
};
int __initdata msc_nr_eicirqs = sizeof(msc_eicirqmap)/sizeof(msc_irqmap_t);

void __init arch_init_irq(void)
{
	init_i8259_irqs();

	if (!cpu_has_veic)
		mips_cpu_irq_init (MIPSCPU_INT_BASE);

        switch(mips_revision_corid) {
        case MIPS_REVISION_CORID_CORE_MSC:
        case MIPS_REVISION_CORID_CORE_FPGA2:
        case MIPS_REVISION_CORID_CORE_FPGA3:
        case MIPS_REVISION_CORID_CORE_EMUL_MSC:
		if (cpu_has_veic)
			init_msc_irqs (MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs);
		else
			init_msc_irqs (MSC01C_INT_BASE, msc_irqmap, msc_nr_irqs);
	}

	if (cpu_has_veic) {
		set_vi_handler (MSC01E_INT_I8259A, malta_hw0_irqdispatch);
		set_vi_handler (MSC01E_INT_COREHI, corehi_irqdispatch);
		setup_irq (MSC01E_INT_BASE+MSC01E_INT_I8259A, &i8259irq);
		setup_irq (MSC01E_INT_BASE+MSC01E_INT_COREHI, &corehi_irqaction);
	}
	else if (cpu_has_vint) {
		set_vi_handler (MIPSCPU_INT_I8259A, malta_hw0_irqdispatch);
		set_vi_handler (MIPSCPU_INT_COREHI, corehi_irqdispatch);

		setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_I8259A, &i8259irq);
		setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction);
	}
	else {
		setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_I8259A, &i8259irq);
		setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction);
	}
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Carsten Langgaard, carstenl@mips.com
	3	* Copyright (C) 2000, 2001, 2004 MIPS Technologies, Inc.
	4	* Copyright (C) 2001 Ralf Baechle
	5	*
	6	* This program is free software; you can distribute it and/or modify it
	7	* under the terms of the GNU General Public License (Version 2) as
	8	* published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope it will be useful, but WITHOUT
	11	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
	13	* for more details.
	14	*
	15	* You should have received a copy of the GNU General Public License along
	16	* with this program; if not, write to the Free Software Foundation, Inc.,
	17	* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
	18	*
	19	* Routines for generic manipulation of the interrupts found on the MIPS
	20	* Malta board.
	21	* The interrupt controller is located in the South Bridge a PIIX4 device
	22	* with two internal 82C95 interrupt controllers.
	23	*/
	24	#include <linux/init.h>
	25	#include <linux/irq.h>
	26	#include <linux/sched.h>
	27	#include <linux/slab.h>
	28	#include <linux/interrupt.h>
	29	#include <linux/kernel_stat.h>
	30	#include <linux/random.h>
	31
	32	#include <asm/i8259.h>
e01402b1	33	#include <asm/irq_cpu.h>
1da177e4 LT	34	#include <asm/io.h>
	35	#include <asm/mips-boards/malta.h>
	36	#include <asm/mips-boards/maltaint.h>
	37	#include <asm/mips-boards/piix4.h>
	38	#include <asm/gt64120.h>
	39	#include <asm/mips-boards/generic.h>
	40	#include <asm/mips-boards/msc01_pci.h>
e01402b1	41	#include <asm/msc01_ic.h>
1da177e4	42
e01402b1	43	extern void mips_timer_interrupt(void);
1da177e4 LT	44
	45	static DEFINE_SPINLOCK(mips_irq_lock);
	46
	47	static inline int mips_pcibios_iack(void)
	48	{
	49	int irq;
	50	u32 dummy;
	51
	52	/*
	53	* Determine highest priority pending interrupt by performing
	54	* a PCI Interrupt Acknowledge cycle.
	55	*/
	56	switch(mips_revision_corid) {
	57	case MIPS_REVISION_CORID_CORE_MSC:
	58	case MIPS_REVISION_CORID_CORE_FPGA2:
479a0e3e	59	case MIPS_REVISION_CORID_CORE_FPGA3:
1da177e4 LT	60	case MIPS_REVISION_CORID_CORE_EMUL_MSC:
	61	MSC_READ(MSC01_PCI_IACK, irq);
	62	irq &= 0xff;
	63	break;
	64	case MIPS_REVISION_CORID_QED_RM5261:
	65	case MIPS_REVISION_CORID_CORE_LV:
	66	case MIPS_REVISION_CORID_CORE_FPGA:
	67	case MIPS_REVISION_CORID_CORE_FPGAR2:
	68	irq = GT_READ(GT_PCI0_IACK_OFS);
	69	irq &= 0xff;
	70	break;
	71	case MIPS_REVISION_CORID_BONITO64:
	72	case MIPS_REVISION_CORID_CORE_20K:
	73	case MIPS_REVISION_CORID_CORE_EMUL_BON:
	74	/* The following will generate a PCI IACK cycle on the
	75	* Bonito controller. It's a little bit kludgy, but it
	76	* was the easiest way to implement it in hardware at
	77	* the given time.
	78	*/
	79	BONITO_PCIMAP_CFG = 0x20000;
	80
	81	/* Flush Bonito register block */
	82	dummy = BONITO_PCIMAP_CFG;
	83	iob(); /* sync */
	84
	85	irq = (volatile u32 )(_pcictrl_bonito_pcicfg);
	86	iob(); /* sync */
	87	irq &= 0xff;
	88	BONITO_PCIMAP_CFG = 0;
	89	break;
	90	default:
	91	printk("Unknown Core card, don't know the system controller.\n");
	92	return -1;
	93	}
	94	return irq;
	95	}
	96
e01402b1	97	static inline int get_int(void)
1da177e4 LT	98	{
1da177e4 LT	99	unsigned long flags;
e01402b1	100	int irq;
1da177e4 LT	101	spin_lock_irqsave(&mips_irq_lock, flags);
1da177e4 LT	102
e01402b1	103	irq = mips_pcibios_iack();
1da177e4 LT	104
1da177e4 LT	105	/*
479a0e3e RB	106	* The only way we can decide if an interrupt is spurious
	107	* is by checking the 8259 registers. This needs a spinlock
	108	* on an SMP system, so leave it up to the generic code...
1da177e4	109	*/
1da177e4 LT	110
	111	spin_unlock_irqrestore(&mips_irq_lock, flags);
	112
e01402b1	113	return irq;
1da177e4 LT	114	}
1da177e4 LT	115
e4ac58af	116	static void malta_hw0_irqdispatch(struct pt_regs *regs)
1da177e4 LT	117	{
	118	int irq;
	119
e01402b1 RB	120	irq = get_int();
	121	if (irq < 0)
	122	return; /* interrupt has already been cleared */
1da177e4	123
e01402b1	124	do_IRQ(MALTA_INT_BASE+irq, regs);
1da177e4 LT	125	}
	126
	127	void corehi_irqdispatch(struct pt_regs *regs)
	128	{
e01402b1 RB	129	unsigned int intrcause,datalo,datahi;
e01402b1 RB	130	unsigned int pcimstat, intisr, inten, intpol, intedge, intsteer, pcicmd, pcibadaddr;
1da177e4 LT	131
	132	printk("CoreHI interrupt, shouldn't happen, so we die here!!!\n");
	133	printk("epc : %08lx\nStatus: %08lx\nCause : %08lx\nbadVaddr : %08lx\n"
	134	, regs->cp0_epc, regs->cp0_status, regs->cp0_cause, regs->cp0_badvaddr);
e01402b1 RB	135
	136	/* Read all the registers and then print them as there is a
	137	problem with interspersed printk's upsetting the Bonito controller.
	138	Do it for the others too.
	139	*/
	140
1da177e4 LT	141	switch(mips_revision_corid) {
	142	case MIPS_REVISION_CORID_CORE_MSC:
	143	case MIPS_REVISION_CORID_CORE_FPGA2:
479a0e3e	144	case MIPS_REVISION_CORID_CORE_FPGA3:
e01402b1 RB	145	case MIPS_REVISION_CORID_CORE_EMUL_MSC:
e01402b1 RB	146	ll_msc_irq(regs);
1da177e4 LT	147	break;
	148	case MIPS_REVISION_CORID_QED_RM5261:
	149	case MIPS_REVISION_CORID_CORE_LV:
	150	case MIPS_REVISION_CORID_CORE_FPGA:
	151	case MIPS_REVISION_CORID_CORE_FPGAR2:
e01402b1 RB	152	intrcause = GT_READ(GT_INTRCAUSE_OFS);
e01402b1 RB	153	datalo = GT_READ(GT_CPUERR_ADDRLO_OFS);
1da177e4	154	datahi = GT_READ(GT_CPUERR_ADDRHI_OFS);
e01402b1 RB	155	printk("GT_INTRCAUSE = %08x\n", intrcause);
e01402b1 RB	156	printk("GT_CPUERR_ADDR = %02x%08x\n", datahi, datalo);
1da177e4 LT	157	break;
	158	case MIPS_REVISION_CORID_BONITO64:
	159	case MIPS_REVISION_CORID_CORE_20K:
	160	case MIPS_REVISION_CORID_CORE_EMUL_BON:
e01402b1 RB	161	pcibadaddr = BONITO_PCIBADADDR;
	162	pcimstat = BONITO_PCIMSTAT;
	163	intisr = BONITO_INTISR;
	164	inten = BONITO_INTEN;
	165	intpol = BONITO_INTPOL;
	166	intedge = BONITO_INTEDGE;
	167	intsteer = BONITO_INTSTEER;
	168	pcicmd = BONITO_PCICMD;
	169	printk("BONITO_INTISR = %08x\n", intisr);
	170	printk("BONITO_INTEN = %08x\n", inten);
	171	printk("BONITO_INTPOL = %08x\n", intpol);
	172	printk("BONITO_INTEDGE = %08x\n", intedge);
	173	printk("BONITO_INTSTEER = %08x\n", intsteer);
	174	printk("BONITO_PCICMD = %08x\n", pcicmd);
	175	printk("BONITO_PCIBADADDR = %08x\n", pcibadaddr);
	176	printk("BONITO_PCIMSTAT = %08x\n", pcimstat);
1da177e4 LT	177	break;
	178	}
	179
	180	/* We die here*/
	181	die("CoreHi interrupt", regs);
	182	}
	183
e4ac58af RB	184	static inline int clz(unsigned long x)
	185	{
	186	__asm__ (
	187	" .set push \n"
	188	" .set mips32 \n"
	189	" clz %0, %1 \n"
	190	" .set pop \n"
	191	: "=r" (x)
	192	: "r" (x));
	193
	194	return x;
	195	}
	196
	197	/*
	198	* Version of ffs that only looks at bits 12..15.
	199	*/
	200	static inline unsigned int irq_ffs(unsigned int pending)
	201	{
	202	#if defined(CONFIG_CPU_MIPS32) \|\| defined(CONFIG_CPU_MIPS64)
	203	return -clz(pending) + 31 - CAUSEB_IP;
	204	#else
	205	unsigned int a0 = 7;
	206	unsigned int t0;
	207
	208	t0 = s0 & 0xf000;
	209	t0 = t0 < 1;
	210	t0 = t0 << 2;
	211	a0 = a0 - t0;
	212	s0 = s0 << t0;
	213
	214	t0 = s0 & 0xc000;
	215	t0 = t0 < 1;
	216	t0 = t0 << 1;
	217	a0 = a0 - t0;
	218	s0 = s0 << t0;
	219
	220	t0 = s0 & 0x8000;
	221	t0 = t0 < 1;
	222	//t0 = t0 << 2;
	223	a0 = a0 - t0;
	224	//s0 = s0 << t0;
	225
	226	return a0;
	227	#endif
	228	}
	229
	230	/*
	231	* IRQs on the Malta board look basically (barring software IRQs which we
	232	* don't use at all and all external interrupt sources are combined together
	233	* on hardware interrupt 0 (MIPS IRQ 2)) like:
	234	*
	235	* MIPS IRQ Source
	236	* -------- ------
	237	* 0 Software (ignored)
	238	* 1 Software (ignored)
	239	* 2 Combined hardware interrupt (hw0)
	240	* 3 Hardware (ignored)
	241	* 4 Hardware (ignored)
	242	* 5 Hardware (ignored)
	243	* 6 Hardware (ignored)
	244	* 7 R4k timer (what we use)
	245	*
	246	* We handle the IRQ according to _our_ priority which is:
	247	*
248	* Highest ---- R4k Timer
249	* Lowest ---- Combined hardware interrupt
250	*
251	* then we just return, if multiple IRQs are pending then we will just take
252	* another exception, big deal.
253	*/
254
255	asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
256	{
257	unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
258	int irq;
259
260	irq = irq_ffs(pending);
261
262	if (irq == MIPSCPU_INT_I8259A)
263	malta_hw0_irqdispatch(regs);
264	else if (irq > 0)
265	do_IRQ(MIPSCPU_INT_BASE + irq, regs);
266	else
267	spurious_interrupt(regs);
268	}
269
e01402b1 RB	270	static struct irqaction i8259irq = {
	271	.handler = no_action,
	272	.name = "XT-PIC cascade"
	273	};
	274
	275	static struct irqaction corehi_irqaction = {
	276	.handler = no_action,
	277	.name = "CoreHi"
	278	};
	279
	280	msc_irqmap_t __initdata msc_irqmap[] = {
	281	{MSC01C_INT_TMR, MSC01_IRQ_EDGE, 0},
	282	{MSC01C_INT_PCI, MSC01_IRQ_LEVEL, 0},
	283	};
	284	int __initdata msc_nr_irqs = sizeof(msc_irqmap)/sizeof(msc_irqmap_t);
	285
	286	msc_irqmap_t __initdata msc_eicirqmap[] = {
	287	{MSC01E_INT_SW0, MSC01_IRQ_LEVEL, 0},
	288	{MSC01E_INT_SW1, MSC01_IRQ_LEVEL, 0},
	289	{MSC01E_INT_I8259A, MSC01_IRQ_LEVEL, 0},
	290	{MSC01E_INT_SMI, MSC01_IRQ_LEVEL, 0},
	291	{MSC01E_INT_COREHI, MSC01_IRQ_LEVEL, 0},
	292	{MSC01E_INT_CORELO, MSC01_IRQ_LEVEL, 0},
	293	{MSC01E_INT_TMR, MSC01_IRQ_EDGE, 0},
	294	{MSC01E_INT_PCI, MSC01_IRQ_LEVEL, 0},
	295	{MSC01E_INT_PERFCTR, MSC01_IRQ_LEVEL, 0},
	296	{MSC01E_INT_CPUCTR, MSC01_IRQ_LEVEL, 0}
	297	};
	298	int __initdata msc_nr_eicirqs = sizeof(msc_eicirqmap)/sizeof(msc_irqmap_t);
	299
1da177e4 LT	300	void __init arch_init_irq(void)
1da177e4 LT	301	{
1da177e4	302	init_i8259_irqs();
e01402b1 RB	303
	304	if (!cpu_has_veic)
	305	mips_cpu_irq_init (MIPSCPU_INT_BASE);
	306
	307	switch(mips_revision_corid) {
	308	case MIPS_REVISION_CORID_CORE_MSC:
	309	case MIPS_REVISION_CORID_CORE_FPGA2:
479a0e3e	310	case MIPS_REVISION_CORID_CORE_FPGA3:
e01402b1 RB	311	case MIPS_REVISION_CORID_CORE_EMUL_MSC:
	312	if (cpu_has_veic)
	313	init_msc_irqs (MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs);
	314	else
	315	init_msc_irqs (MSC01C_INT_BASE, msc_irqmap, msc_nr_irqs);
	316	}
	317
	318	if (cpu_has_veic) {
	319	set_vi_handler (MSC01E_INT_I8259A, malta_hw0_irqdispatch);
	320	set_vi_handler (MSC01E_INT_COREHI, corehi_irqdispatch);
	321	setup_irq (MSC01E_INT_BASE+MSC01E_INT_I8259A, &i8259irq);
	322	setup_irq (MSC01E_INT_BASE+MSC01E_INT_COREHI, &corehi_irqaction);
	323	}
	324	else if (cpu_has_vint) {
	325	set_vi_handler (MIPSCPU_INT_I8259A, malta_hw0_irqdispatch);
	326	set_vi_handler (MIPSCPU_INT_COREHI, corehi_irqdispatch);
	327
	328	setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_I8259A, &i8259irq);
	329	setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction);
	330	}
	331	else {
e01402b1 RB	332	setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_I8259A, &i8259irq);
	333	setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction);
	334	}
1da177e4	335	}