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1da177e4 LT |
1 | /* |
2 | * Carsten Langgaard, carstenl@mips.com | |
3 | * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. | |
4 | * | |
5 | * This program is free software; you can distribute it and/or modify it | |
6 | * under the terms of the GNU General Public License (Version 2) as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 | * for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along | |
15 | * with this program; if not, write to the Free Software Foundation, Inc., | |
16 | * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. | |
17 | */ | |
1da177e4 LT |
18 | #include <linux/init.h> |
19 | #include <linux/sched.h> | |
20 | #include <linux/ioport.h> | |
21 | #include <linux/pci.h> | |
894673ee | 22 | #include <linux/screen_info.h> |
1da177e4 | 23 | |
1da177e4 LT |
24 | #include <asm/cpu.h> |
25 | #include <asm/bootinfo.h> | |
26 | #include <asm/irq.h> | |
27 | #include <asm/mips-boards/generic.h> | |
28 | #include <asm/mips-boards/prom.h> | |
29 | #include <asm/mips-boards/malta.h> | |
30 | #include <asm/mips-boards/maltaint.h> | |
31 | #include <asm/dma.h> | |
32 | #include <asm/time.h> | |
33 | #include <asm/traps.h> | |
34 | #ifdef CONFIG_VT | |
35 | #include <linux/console.h> | |
36 | #endif | |
37 | ||
38 | extern void mips_reboot_setup(void); | |
1da177e4 LT |
39 | extern unsigned long mips_rtc_get_time(void); |
40 | ||
41 | #ifdef CONFIG_KGDB | |
42 | extern void kgdb_config(void); | |
43 | #endif | |
44 | ||
45 | struct resource standard_io_resources[] = { | |
4ca76513 DV |
46 | { |
47 | .name = "dma1", | |
48 | .start = 0x00, | |
49 | .end = 0x1f, | |
50 | .flags = IORESOURCE_BUSY | |
51 | }, | |
52 | { | |
53 | .name = "timer", | |
54 | .start = 0x40, | |
55 | .end = 0x5f, | |
56 | .flags = IORESOURCE_BUSY | |
57 | }, | |
58 | { | |
59 | .name = "keyboard", | |
60 | .start = 0x60, | |
61 | .end = 0x6f, | |
62 | .flags = IORESOURCE_BUSY | |
63 | }, | |
64 | { | |
65 | .name = "dma page reg", | |
66 | .start = 0x80, | |
67 | .end = 0x8f, | |
68 | .flags = IORESOURCE_BUSY | |
69 | }, | |
70 | { | |
71 | .name = "dma2", | |
72 | .start = 0xc0, | |
73 | .end = 0xdf, | |
74 | .flags = IORESOURCE_BUSY | |
75 | }, | |
1da177e4 LT |
76 | }; |
77 | ||
1da177e4 LT |
78 | const char *get_system_type(void) |
79 | { | |
80 | return "MIPS Malta"; | |
81 | } | |
82 | ||
79894c7b RB |
83 | #if defined(CONFIG_MIPS_MT_SMTC) |
84 | const char display_string[] = " SMTC LINUX ON MALTA "; | |
85 | #else | |
86 | const char display_string[] = " LINUX ON MALTA "; | |
87 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
88 | ||
1da177e4 LT |
89 | #ifdef CONFIG_BLK_DEV_FD |
90 | void __init fd_activate(void) | |
91 | { | |
92 | /* | |
93 | * Activate Floppy Controller in the SMSC FDC37M817 Super I/O | |
94 | * Controller. | |
95 | * Done by YAMON 2.00 onwards | |
96 | */ | |
97 | /* Entering config state. */ | |
98 | SMSC_WRITE(SMSC_CONFIG_ENTER, SMSC_CONFIG_REG); | |
99 | ||
100 | /* Activate floppy controller. */ | |
101 | SMSC_WRITE(SMSC_CONFIG_DEVNUM, SMSC_CONFIG_REG); | |
102 | SMSC_WRITE(SMSC_CONFIG_DEVNUM_FLOPPY, SMSC_DATA_REG); | |
103 | SMSC_WRITE(SMSC_CONFIG_ACTIVATE, SMSC_CONFIG_REG); | |
104 | SMSC_WRITE(SMSC_CONFIG_ACTIVATE_ENABLE, SMSC_DATA_REG); | |
105 | ||
106 | /* Exit config state. */ | |
107 | SMSC_WRITE(SMSC_CONFIG_EXIT, SMSC_CONFIG_REG); | |
108 | } | |
109 | #endif | |
110 | ||
2925aba4 | 111 | void __init plat_mem_setup(void) |
1da177e4 LT |
112 | { |
113 | unsigned int i; | |
114 | ||
c83cfc9c RB |
115 | mips_pcibios_init(); |
116 | ||
1da177e4 LT |
117 | /* Request I/O space for devices used on the Malta board. */ |
118 | for (i = 0; i < ARRAY_SIZE(standard_io_resources); i++) | |
119 | request_resource(&ioport_resource, standard_io_resources+i); | |
120 | ||
121 | /* | |
122 | * Enable DMA channel 4 (cascade channel) in the PIIX4 south bridge. | |
123 | */ | |
124 | enable_dma(4); | |
125 | ||
126 | #ifdef CONFIG_KGDB | |
49a89efb | 127 | kgdb_config(); |
1da177e4 LT |
128 | #endif |
129 | ||
b72c0526 | 130 | if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO) { |
1da177e4 LT |
131 | char *argptr; |
132 | ||
133 | argptr = prom_getcmdline(); | |
134 | if (strstr(argptr, "debug")) { | |
135 | BONITO_BONGENCFG |= BONITO_BONGENCFG_DEBUGMODE; | |
49a89efb | 136 | printk("Enabled Bonito debug mode\n"); |
1da177e4 LT |
137 | } |
138 | else | |
139 | BONITO_BONGENCFG &= ~BONITO_BONGENCFG_DEBUGMODE; | |
140 | ||
141 | #ifdef CONFIG_DMA_COHERENT | |
142 | if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) { | |
143 | BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_CPUCOH_EN; | |
144 | printk("Enabled Bonito CPU coherency\n"); | |
145 | ||
146 | argptr = prom_getcmdline(); | |
147 | if (strstr(argptr, "iobcuncached")) { | |
148 | BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN; | |
42a3b4f2 | 149 | BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG & |
1da177e4 LT |
150 | ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | |
151 | BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); | |
152 | printk("Disabled Bonito IOBC coherency\n"); | |
153 | } | |
154 | else { | |
155 | BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_IOBCCOH_EN; | |
42a3b4f2 RB |
156 | BONITO_PCIMEMBASECFG |= |
157 | (BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | | |
1da177e4 | 158 | BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); |
177b2927 | 159 | printk("Enabled Bonito IOBC coherency\n"); |
1da177e4 LT |
160 | } |
161 | } | |
162 | else | |
163 | panic("Hardware DMA cache coherency not supported"); | |
164 | ||
165 | #endif | |
166 | } | |
167 | #ifdef CONFIG_DMA_COHERENT | |
168 | else { | |
169 | panic("Hardware DMA cache coherency not supported"); | |
170 | } | |
171 | #endif | |
172 | ||
173 | #ifdef CONFIG_BLK_DEV_IDE | |
174 | /* Check PCI clock */ | |
175 | { | |
f1974653 | 176 | unsigned int __iomem *jmpr_p = (unsigned int *) ioremap(MALTA_JMPRS_REG, sizeof(unsigned int)); |
0487de91 | 177 | int jmpr = (__raw_readl(jmpr_p) >> 2) & 0x07; |
1da177e4 LT |
178 | static const int pciclocks[] __initdata = { |
179 | 33, 20, 25, 30, 12, 16, 37, 10 | |
180 | }; | |
181 | int pciclock = pciclocks[jmpr]; | |
182 | char *argptr = prom_getcmdline(); | |
183 | ||
184 | if (pciclock != 33 && !strstr (argptr, "idebus=")) { | |
185 | printk("WARNING: PCI clock is %dMHz, setting idebus\n", pciclock); | |
186 | argptr += strlen(argptr); | |
49a89efb | 187 | sprintf(argptr, " idebus=%d", pciclock); |
1da177e4 | 188 | if (pciclock < 20 || pciclock > 66) |
49a89efb | 189 | printk("WARNING: IDE timing calculations will be incorrect\n"); |
1da177e4 LT |
190 | } |
191 | } | |
192 | #endif | |
193 | #ifdef CONFIG_BLK_DEV_FD | |
49a89efb | 194 | fd_activate(); |
1da177e4 LT |
195 | #endif |
196 | #ifdef CONFIG_VT | |
197 | #if defined(CONFIG_VGA_CONSOLE) | |
198 | screen_info = (struct screen_info) { | |
4ca76513 DV |
199 | .orig_x = 0, |
200 | .orig_y = 25, | |
201 | .ext_mem_k = 0, | |
202 | .orig_video_page = 0, | |
203 | .orig_video_mode = 0, | |
204 | .orig_video_cols = 80, | |
205 | .unused2 = 0, | |
206 | .orig_video_ega_bx = 0, | |
207 | .unused3 = 0, | |
208 | .orig_video_lines = 25, | |
209 | .orig_video_isVGA = VIDEO_TYPE_VGAC, | |
210 | .orig_video_points = 16 | |
1da177e4 LT |
211 | }; |
212 | #endif | |
213 | #endif | |
1da177e4 | 214 | mips_reboot_setup(); |
1da177e4 | 215 | } |