Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
79add627 | 6 | * Copyright (C) 1996 David S. Miller (davem@davemloft.net) |
1da177e4 LT |
7 | * Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002 Ralf Baechle (ralf@gnu.org) |
8 | * Copyright (C) 1999, 2000 Silicon Graphics, Inc. | |
9 | */ | |
61d73044 | 10 | #include <linux/cpu_pm.h> |
a754f708 | 11 | #include <linux/hardirq.h> |
1da177e4 | 12 | #include <linux/init.h> |
db813fe5 | 13 | #include <linux/highmem.h> |
1da177e4 | 14 | #include <linux/kernel.h> |
641e97f3 | 15 | #include <linux/linkage.h> |
ff522058 | 16 | #include <linux/preempt.h> |
1da177e4 | 17 | #include <linux/sched.h> |
631330f5 | 18 | #include <linux/smp.h> |
1da177e4 | 19 | #include <linux/mm.h> |
35133692 | 20 | #include <linux/module.h> |
1da177e4 LT |
21 | #include <linux/bitops.h> |
22 | ||
23 | #include <asm/bcache.h> | |
24 | #include <asm/bootinfo.h> | |
ec74e361 | 25 | #include <asm/cache.h> |
1da177e4 LT |
26 | #include <asm/cacheops.h> |
27 | #include <asm/cpu.h> | |
28 | #include <asm/cpu-features.h> | |
69f24d17 | 29 | #include <asm/cpu-type.h> |
1da177e4 LT |
30 | #include <asm/io.h> |
31 | #include <asm/page.h> | |
32 | #include <asm/pgtable.h> | |
33 | #include <asm/r4kcache.h> | |
e001e528 | 34 | #include <asm/sections.h> |
1da177e4 LT |
35 | #include <asm/mmu_context.h> |
36 | #include <asm/war.h> | |
ba5187db | 37 | #include <asm/cacheflush.h> /* for run_uncached() */ |
9cd9669b | 38 | #include <asm/traps.h> |
b6d92b4a | 39 | #include <asm/dma-coherence.h> |
cccf34e9 | 40 | #include <asm/mips-cm.h> |
7f3f1d01 RB |
41 | |
42 | /* | |
43 | * Special Variant of smp_call_function for use by cache functions: | |
44 | * | |
45 | * o No return value | |
46 | * o collapses to normal function call on UP kernels | |
47 | * o collapses to normal function call on systems with a single shared | |
48 | * primary cache. | |
c8c5f3fd | 49 | * o doesn't disable interrupts on the local CPU |
7f3f1d01 | 50 | */ |
48a26e60 | 51 | static inline void r4k_on_each_cpu(void (*func) (void *info), void *info) |
7f3f1d01 RB |
52 | { |
53 | preempt_disable(); | |
54 | ||
cccf34e9 MC |
55 | /* |
56 | * The Coherent Manager propagates address-based cache ops to other | |
57 | * cores but not index-based ops. However, r4k_on_each_cpu is used | |
58 | * in both cases so there is no easy way to tell what kind of op is | |
59 | * executed to the other cores. The best we can probably do is | |
60 | * to restrict that call when a CM is not present because both | |
61 | * CM-based SMP protocols (CMP & CPS) restrict index-based cache ops. | |
62 | */ | |
63 | if (!mips_cm_present()) | |
64 | smp_call_function_many(&cpu_foreign_map, func, info, 1); | |
7f3f1d01 RB |
65 | func(info); |
66 | preempt_enable(); | |
67 | } | |
68 | ||
0ee958e1 | 69 | #if defined(CONFIG_MIPS_CMP) || defined(CONFIG_MIPS_CPS) |
39b8d525 RB |
70 | #define cpu_has_safe_index_cacheops 0 |
71 | #else | |
72 | #define cpu_has_safe_index_cacheops 1 | |
73 | #endif | |
74 | ||
ec74e361 RB |
75 | /* |
76 | * Must die. | |
77 | */ | |
78 | static unsigned long icache_size __read_mostly; | |
79 | static unsigned long dcache_size __read_mostly; | |
80 | static unsigned long scache_size __read_mostly; | |
1da177e4 LT |
81 | |
82 | /* | |
83 | * Dummy cache handling routines for machines without boardcaches | |
84 | */ | |
73f40352 | 85 | static void cache_noop(void) {} |
1da177e4 LT |
86 | |
87 | static struct bcache_ops no_sc_ops = { | |
73f40352 CD |
88 | .bc_enable = (void *)cache_noop, |
89 | .bc_disable = (void *)cache_noop, | |
90 | .bc_wback_inv = (void *)cache_noop, | |
91 | .bc_inv = (void *)cache_noop | |
1da177e4 LT |
92 | }; |
93 | ||
94 | struct bcache_ops *bcops = &no_sc_ops; | |
95 | ||
330cfe01 TS |
96 | #define cpu_is_r4600_v1_x() ((read_c0_prid() & 0xfffffff0) == 0x00002010) |
97 | #define cpu_is_r4600_v2_x() ((read_c0_prid() & 0xfffffff0) == 0x00002020) | |
1da177e4 LT |
98 | |
99 | #define R4600_HIT_CACHEOP_WAR_IMPL \ | |
100 | do { \ | |
101 | if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x()) \ | |
102 | *(volatile unsigned long *)CKSEG1; \ | |
103 | if (R4600_V1_HIT_CACHEOP_WAR) \ | |
104 | __asm__ __volatile__("nop;nop;nop;nop"); \ | |
105 | } while (0) | |
106 | ||
107 | static void (*r4k_blast_dcache_page)(unsigned long addr); | |
108 | ||
109 | static inline void r4k_blast_dcache_page_dc32(unsigned long addr) | |
110 | { | |
111 | R4600_HIT_CACHEOP_WAR_IMPL; | |
112 | blast_dcache32_page(addr); | |
113 | } | |
114 | ||
605b7ef7 KC |
115 | static inline void r4k_blast_dcache_page_dc64(unsigned long addr) |
116 | { | |
605b7ef7 KC |
117 | blast_dcache64_page(addr); |
118 | } | |
119 | ||
18a8cd63 DD |
120 | static inline void r4k_blast_dcache_page_dc128(unsigned long addr) |
121 | { | |
122 | blast_dcache128_page(addr); | |
123 | } | |
124 | ||
078a55fc | 125 | static void r4k_blast_dcache_page_setup(void) |
1da177e4 LT |
126 | { |
127 | unsigned long dc_lsize = cpu_dcache_line_size(); | |
128 | ||
18a8cd63 DD |
129 | switch (dc_lsize) { |
130 | case 0: | |
73f40352 | 131 | r4k_blast_dcache_page = (void *)cache_noop; |
18a8cd63 DD |
132 | break; |
133 | case 16: | |
1da177e4 | 134 | r4k_blast_dcache_page = blast_dcache16_page; |
18a8cd63 DD |
135 | break; |
136 | case 32: | |
1da177e4 | 137 | r4k_blast_dcache_page = r4k_blast_dcache_page_dc32; |
18a8cd63 DD |
138 | break; |
139 | case 64: | |
605b7ef7 | 140 | r4k_blast_dcache_page = r4k_blast_dcache_page_dc64; |
18a8cd63 DD |
141 | break; |
142 | case 128: | |
143 | r4k_blast_dcache_page = r4k_blast_dcache_page_dc128; | |
144 | break; | |
145 | default: | |
146 | break; | |
147 | } | |
1da177e4 LT |
148 | } |
149 | ||
4caa906e LY |
150 | #ifndef CONFIG_EVA |
151 | #define r4k_blast_dcache_user_page r4k_blast_dcache_page | |
152 | #else | |
153 | ||
154 | static void (*r4k_blast_dcache_user_page)(unsigned long addr); | |
155 | ||
156 | static void r4k_blast_dcache_user_page_setup(void) | |
157 | { | |
158 | unsigned long dc_lsize = cpu_dcache_line_size(); | |
159 | ||
160 | if (dc_lsize == 0) | |
161 | r4k_blast_dcache_user_page = (void *)cache_noop; | |
162 | else if (dc_lsize == 16) | |
163 | r4k_blast_dcache_user_page = blast_dcache16_user_page; | |
164 | else if (dc_lsize == 32) | |
165 | r4k_blast_dcache_user_page = blast_dcache32_user_page; | |
166 | else if (dc_lsize == 64) | |
167 | r4k_blast_dcache_user_page = blast_dcache64_user_page; | |
168 | } | |
169 | ||
170 | #endif | |
171 | ||
1da177e4 LT |
172 | static void (* r4k_blast_dcache_page_indexed)(unsigned long addr); |
173 | ||
078a55fc | 174 | static void r4k_blast_dcache_page_indexed_setup(void) |
1da177e4 LT |
175 | { |
176 | unsigned long dc_lsize = cpu_dcache_line_size(); | |
177 | ||
73f40352 CD |
178 | if (dc_lsize == 0) |
179 | r4k_blast_dcache_page_indexed = (void *)cache_noop; | |
180 | else if (dc_lsize == 16) | |
1da177e4 LT |
181 | r4k_blast_dcache_page_indexed = blast_dcache16_page_indexed; |
182 | else if (dc_lsize == 32) | |
183 | r4k_blast_dcache_page_indexed = blast_dcache32_page_indexed; | |
605b7ef7 KC |
184 | else if (dc_lsize == 64) |
185 | r4k_blast_dcache_page_indexed = blast_dcache64_page_indexed; | |
18a8cd63 DD |
186 | else if (dc_lsize == 128) |
187 | r4k_blast_dcache_page_indexed = blast_dcache128_page_indexed; | |
1da177e4 LT |
188 | } |
189 | ||
f2e3656d SL |
190 | void (* r4k_blast_dcache)(void); |
191 | EXPORT_SYMBOL(r4k_blast_dcache); | |
1da177e4 | 192 | |
078a55fc | 193 | static void r4k_blast_dcache_setup(void) |
1da177e4 LT |
194 | { |
195 | unsigned long dc_lsize = cpu_dcache_line_size(); | |
196 | ||
73f40352 CD |
197 | if (dc_lsize == 0) |
198 | r4k_blast_dcache = (void *)cache_noop; | |
199 | else if (dc_lsize == 16) | |
1da177e4 LT |
200 | r4k_blast_dcache = blast_dcache16; |
201 | else if (dc_lsize == 32) | |
202 | r4k_blast_dcache = blast_dcache32; | |
605b7ef7 KC |
203 | else if (dc_lsize == 64) |
204 | r4k_blast_dcache = blast_dcache64; | |
18a8cd63 DD |
205 | else if (dc_lsize == 128) |
206 | r4k_blast_dcache = blast_dcache128; | |
1da177e4 LT |
207 | } |
208 | ||
209 | /* force code alignment (used for TX49XX_ICACHE_INDEX_INV_WAR) */ | |
210 | #define JUMP_TO_ALIGN(order) \ | |
211 | __asm__ __volatile__( \ | |
212 | "b\t1f\n\t" \ | |
213 | ".align\t" #order "\n\t" \ | |
214 | "1:\n\t" \ | |
215 | ) | |
216 | #define CACHE32_UNROLL32_ALIGN JUMP_TO_ALIGN(10) /* 32 * 32 = 1024 */ | |
70342287 | 217 | #define CACHE32_UNROLL32_ALIGN2 JUMP_TO_ALIGN(11) |
1da177e4 LT |
218 | |
219 | static inline void blast_r4600_v1_icache32(void) | |
220 | { | |
221 | unsigned long flags; | |
222 | ||
223 | local_irq_save(flags); | |
224 | blast_icache32(); | |
225 | local_irq_restore(flags); | |
226 | } | |
227 | ||
228 | static inline void tx49_blast_icache32(void) | |
229 | { | |
230 | unsigned long start = INDEX_BASE; | |
231 | unsigned long end = start + current_cpu_data.icache.waysize; | |
232 | unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit; | |
233 | unsigned long ws_end = current_cpu_data.icache.ways << | |
70342287 | 234 | current_cpu_data.icache.waybit; |
1da177e4 LT |
235 | unsigned long ws, addr; |
236 | ||
237 | CACHE32_UNROLL32_ALIGN2; | |
238 | /* I'm in even chunk. blast odd chunks */ | |
42a3b4f2 RB |
239 | for (ws = 0; ws < ws_end; ws += ws_inc) |
240 | for (addr = start + 0x400; addr < end; addr += 0x400 * 2) | |
21a151d8 | 241 | cache32_unroll32(addr|ws, Index_Invalidate_I); |
1da177e4 LT |
242 | CACHE32_UNROLL32_ALIGN; |
243 | /* I'm in odd chunk. blast even chunks */ | |
42a3b4f2 RB |
244 | for (ws = 0; ws < ws_end; ws += ws_inc) |
245 | for (addr = start; addr < end; addr += 0x400 * 2) | |
21a151d8 | 246 | cache32_unroll32(addr|ws, Index_Invalidate_I); |
1da177e4 LT |
247 | } |
248 | ||
249 | static inline void blast_icache32_r4600_v1_page_indexed(unsigned long page) | |
250 | { | |
251 | unsigned long flags; | |
252 | ||
253 | local_irq_save(flags); | |
254 | blast_icache32_page_indexed(page); | |
255 | local_irq_restore(flags); | |
256 | } | |
257 | ||
258 | static inline void tx49_blast_icache32_page_indexed(unsigned long page) | |
259 | { | |
67a3f6de AN |
260 | unsigned long indexmask = current_cpu_data.icache.waysize - 1; |
261 | unsigned long start = INDEX_BASE + (page & indexmask); | |
1da177e4 LT |
262 | unsigned long end = start + PAGE_SIZE; |
263 | unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit; | |
264 | unsigned long ws_end = current_cpu_data.icache.ways << | |
70342287 | 265 | current_cpu_data.icache.waybit; |
1da177e4 LT |
266 | unsigned long ws, addr; |
267 | ||
268 | CACHE32_UNROLL32_ALIGN2; | |
269 | /* I'm in even chunk. blast odd chunks */ | |
42a3b4f2 RB |
270 | for (ws = 0; ws < ws_end; ws += ws_inc) |
271 | for (addr = start + 0x400; addr < end; addr += 0x400 * 2) | |
21a151d8 | 272 | cache32_unroll32(addr|ws, Index_Invalidate_I); |
1da177e4 LT |
273 | CACHE32_UNROLL32_ALIGN; |
274 | /* I'm in odd chunk. blast even chunks */ | |
42a3b4f2 RB |
275 | for (ws = 0; ws < ws_end; ws += ws_inc) |
276 | for (addr = start; addr < end; addr += 0x400 * 2) | |
21a151d8 | 277 | cache32_unroll32(addr|ws, Index_Invalidate_I); |
1da177e4 LT |
278 | } |
279 | ||
280 | static void (* r4k_blast_icache_page)(unsigned long addr); | |
281 | ||
078a55fc | 282 | static void r4k_blast_icache_page_setup(void) |
1da177e4 LT |
283 | { |
284 | unsigned long ic_lsize = cpu_icache_line_size(); | |
285 | ||
73f40352 CD |
286 | if (ic_lsize == 0) |
287 | r4k_blast_icache_page = (void *)cache_noop; | |
288 | else if (ic_lsize == 16) | |
1da177e4 | 289 | r4k_blast_icache_page = blast_icache16_page; |
43a06847 AK |
290 | else if (ic_lsize == 32 && current_cpu_type() == CPU_LOONGSON2) |
291 | r4k_blast_icache_page = loongson2_blast_icache32_page; | |
1da177e4 LT |
292 | else if (ic_lsize == 32) |
293 | r4k_blast_icache_page = blast_icache32_page; | |
294 | else if (ic_lsize == 64) | |
295 | r4k_blast_icache_page = blast_icache64_page; | |
18a8cd63 DD |
296 | else if (ic_lsize == 128) |
297 | r4k_blast_icache_page = blast_icache128_page; | |
1da177e4 LT |
298 | } |
299 | ||
4caa906e LY |
300 | #ifndef CONFIG_EVA |
301 | #define r4k_blast_icache_user_page r4k_blast_icache_page | |
302 | #else | |
303 | ||
304 | static void (*r4k_blast_icache_user_page)(unsigned long addr); | |
305 | ||
9a8f4ea0 | 306 | static void r4k_blast_icache_user_page_setup(void) |
4caa906e LY |
307 | { |
308 | unsigned long ic_lsize = cpu_icache_line_size(); | |
309 | ||
310 | if (ic_lsize == 0) | |
311 | r4k_blast_icache_user_page = (void *)cache_noop; | |
312 | else if (ic_lsize == 16) | |
313 | r4k_blast_icache_user_page = blast_icache16_user_page; | |
314 | else if (ic_lsize == 32) | |
315 | r4k_blast_icache_user_page = blast_icache32_user_page; | |
316 | else if (ic_lsize == 64) | |
317 | r4k_blast_icache_user_page = blast_icache64_user_page; | |
318 | } | |
319 | ||
320 | #endif | |
1da177e4 LT |
321 | |
322 | static void (* r4k_blast_icache_page_indexed)(unsigned long addr); | |
323 | ||
078a55fc | 324 | static void r4k_blast_icache_page_indexed_setup(void) |
1da177e4 LT |
325 | { |
326 | unsigned long ic_lsize = cpu_icache_line_size(); | |
327 | ||
73f40352 CD |
328 | if (ic_lsize == 0) |
329 | r4k_blast_icache_page_indexed = (void *)cache_noop; | |
330 | else if (ic_lsize == 16) | |
1da177e4 LT |
331 | r4k_blast_icache_page_indexed = blast_icache16_page_indexed; |
332 | else if (ic_lsize == 32) { | |
02fe2c9c | 333 | if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x()) |
1da177e4 LT |
334 | r4k_blast_icache_page_indexed = |
335 | blast_icache32_r4600_v1_page_indexed; | |
02fe2c9c TS |
336 | else if (TX49XX_ICACHE_INDEX_INV_WAR) |
337 | r4k_blast_icache_page_indexed = | |
338 | tx49_blast_icache32_page_indexed; | |
43a06847 AK |
339 | else if (current_cpu_type() == CPU_LOONGSON2) |
340 | r4k_blast_icache_page_indexed = | |
341 | loongson2_blast_icache32_page_indexed; | |
1da177e4 LT |
342 | else |
343 | r4k_blast_icache_page_indexed = | |
344 | blast_icache32_page_indexed; | |
345 | } else if (ic_lsize == 64) | |
346 | r4k_blast_icache_page_indexed = blast_icache64_page_indexed; | |
347 | } | |
348 | ||
f2e3656d SL |
349 | void (* r4k_blast_icache)(void); |
350 | EXPORT_SYMBOL(r4k_blast_icache); | |
1da177e4 | 351 | |
078a55fc | 352 | static void r4k_blast_icache_setup(void) |
1da177e4 LT |
353 | { |
354 | unsigned long ic_lsize = cpu_icache_line_size(); | |
355 | ||
73f40352 CD |
356 | if (ic_lsize == 0) |
357 | r4k_blast_icache = (void *)cache_noop; | |
358 | else if (ic_lsize == 16) | |
1da177e4 LT |
359 | r4k_blast_icache = blast_icache16; |
360 | else if (ic_lsize == 32) { | |
361 | if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x()) | |
362 | r4k_blast_icache = blast_r4600_v1_icache32; | |
363 | else if (TX49XX_ICACHE_INDEX_INV_WAR) | |
364 | r4k_blast_icache = tx49_blast_icache32; | |
43a06847 AK |
365 | else if (current_cpu_type() == CPU_LOONGSON2) |
366 | r4k_blast_icache = loongson2_blast_icache32; | |
1da177e4 LT |
367 | else |
368 | r4k_blast_icache = blast_icache32; | |
369 | } else if (ic_lsize == 64) | |
370 | r4k_blast_icache = blast_icache64; | |
18a8cd63 DD |
371 | else if (ic_lsize == 128) |
372 | r4k_blast_icache = blast_icache128; | |
1da177e4 LT |
373 | } |
374 | ||
375 | static void (* r4k_blast_scache_page)(unsigned long addr); | |
376 | ||
078a55fc | 377 | static void r4k_blast_scache_page_setup(void) |
1da177e4 LT |
378 | { |
379 | unsigned long sc_lsize = cpu_scache_line_size(); | |
380 | ||
4debe4f9 | 381 | if (scache_size == 0) |
73f40352 | 382 | r4k_blast_scache_page = (void *)cache_noop; |
4debe4f9 | 383 | else if (sc_lsize == 16) |
1da177e4 LT |
384 | r4k_blast_scache_page = blast_scache16_page; |
385 | else if (sc_lsize == 32) | |
386 | r4k_blast_scache_page = blast_scache32_page; | |
387 | else if (sc_lsize == 64) | |
388 | r4k_blast_scache_page = blast_scache64_page; | |
389 | else if (sc_lsize == 128) | |
390 | r4k_blast_scache_page = blast_scache128_page; | |
391 | } | |
392 | ||
393 | static void (* r4k_blast_scache_page_indexed)(unsigned long addr); | |
394 | ||
078a55fc | 395 | static void r4k_blast_scache_page_indexed_setup(void) |
1da177e4 LT |
396 | { |
397 | unsigned long sc_lsize = cpu_scache_line_size(); | |
398 | ||
4debe4f9 | 399 | if (scache_size == 0) |
73f40352 | 400 | r4k_blast_scache_page_indexed = (void *)cache_noop; |
4debe4f9 | 401 | else if (sc_lsize == 16) |
1da177e4 LT |
402 | r4k_blast_scache_page_indexed = blast_scache16_page_indexed; |
403 | else if (sc_lsize == 32) | |
404 | r4k_blast_scache_page_indexed = blast_scache32_page_indexed; | |
405 | else if (sc_lsize == 64) | |
406 | r4k_blast_scache_page_indexed = blast_scache64_page_indexed; | |
407 | else if (sc_lsize == 128) | |
408 | r4k_blast_scache_page_indexed = blast_scache128_page_indexed; | |
409 | } | |
410 | ||
411 | static void (* r4k_blast_scache)(void); | |
412 | ||
078a55fc | 413 | static void r4k_blast_scache_setup(void) |
1da177e4 LT |
414 | { |
415 | unsigned long sc_lsize = cpu_scache_line_size(); | |
416 | ||
4debe4f9 | 417 | if (scache_size == 0) |
73f40352 | 418 | r4k_blast_scache = (void *)cache_noop; |
4debe4f9 | 419 | else if (sc_lsize == 16) |
1da177e4 LT |
420 | r4k_blast_scache = blast_scache16; |
421 | else if (sc_lsize == 32) | |
422 | r4k_blast_scache = blast_scache32; | |
423 | else if (sc_lsize == 64) | |
424 | r4k_blast_scache = blast_scache64; | |
425 | else if (sc_lsize == 128) | |
426 | r4k_blast_scache = blast_scache128; | |
427 | } | |
428 | ||
1da177e4 LT |
429 | static inline void local_r4k___flush_cache_all(void * args) |
430 | { | |
10cc3529 | 431 | switch (current_cpu_type()) { |
14bd8c08 | 432 | case CPU_LOONGSON2: |
c579d310 | 433 | case CPU_LOONGSON3: |
1da177e4 LT |
434 | case CPU_R4000SC: |
435 | case CPU_R4000MC: | |
436 | case CPU_R4400SC: | |
437 | case CPU_R4400MC: | |
438 | case CPU_R10000: | |
439 | case CPU_R12000: | |
44d921b2 | 440 | case CPU_R14000: |
30577391 | 441 | case CPU_R16000: |
14bd8c08 RB |
442 | /* |
443 | * These caches are inclusive caches, that is, if something | |
444 | * is not cached in the S-cache, we know it also won't be | |
445 | * in one of the primary caches. | |
446 | */ | |
1da177e4 | 447 | r4k_blast_scache(); |
14bd8c08 RB |
448 | break; |
449 | ||
450 | default: | |
451 | r4k_blast_dcache(); | |
452 | r4k_blast_icache(); | |
453 | break; | |
1da177e4 LT |
454 | } |
455 | } | |
456 | ||
457 | static void r4k___flush_cache_all(void) | |
458 | { | |
48a26e60 | 459 | r4k_on_each_cpu(local_r4k___flush_cache_all, NULL); |
1da177e4 LT |
460 | } |
461 | ||
a76ab5c1 RB |
462 | static inline int has_valid_asid(const struct mm_struct *mm) |
463 | { | |
b633648c | 464 | #ifdef CONFIG_MIPS_MT_SMP |
a76ab5c1 RB |
465 | int i; |
466 | ||
467 | for_each_online_cpu(i) | |
468 | if (cpu_context(i, mm)) | |
469 | return 1; | |
470 | ||
471 | return 0; | |
472 | #else | |
473 | return cpu_context(smp_processor_id(), mm); | |
474 | #endif | |
475 | } | |
476 | ||
9c5a3d72 RB |
477 | static void r4k__flush_cache_vmap(void) |
478 | { | |
479 | r4k_blast_dcache(); | |
480 | } | |
481 | ||
482 | static void r4k__flush_cache_vunmap(void) | |
483 | { | |
484 | r4k_blast_dcache(); | |
485 | } | |
486 | ||
1da177e4 LT |
487 | static inline void local_r4k_flush_cache_range(void * args) |
488 | { | |
489 | struct vm_area_struct *vma = args; | |
2eaa7ec2 | 490 | int exec = vma->vm_flags & VM_EXEC; |
1da177e4 | 491 | |
a76ab5c1 | 492 | if (!(has_valid_asid(vma->vm_mm))) |
1da177e4 LT |
493 | return; |
494 | ||
0550d9d1 | 495 | r4k_blast_dcache(); |
2eaa7ec2 RB |
496 | if (exec) |
497 | r4k_blast_icache(); | |
1da177e4 LT |
498 | } |
499 | ||
500 | static void r4k_flush_cache_range(struct vm_area_struct *vma, | |
501 | unsigned long start, unsigned long end) | |
502 | { | |
2eaa7ec2 | 503 | int exec = vma->vm_flags & VM_EXEC; |
0550d9d1 | 504 | |
2eaa7ec2 | 505 | if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) |
48a26e60 | 506 | r4k_on_each_cpu(local_r4k_flush_cache_range, vma); |
1da177e4 LT |
507 | } |
508 | ||
509 | static inline void local_r4k_flush_cache_mm(void * args) | |
510 | { | |
511 | struct mm_struct *mm = args; | |
512 | ||
a76ab5c1 | 513 | if (!has_valid_asid(mm)) |
1da177e4 LT |
514 | return; |
515 | ||
1da177e4 LT |
516 | /* |
517 | * Kludge alert. For obscure reasons R4000SC and R4400SC go nuts if we | |
30577391 | 518 | * only flush the primary caches but R1x000 behave sane ... |
617667ba RB |
519 | * R4000SC and R4400SC indexed S-cache ops also invalidate primary |
520 | * caches, so we can bail out early. | |
1da177e4 | 521 | */ |
10cc3529 RB |
522 | if (current_cpu_type() == CPU_R4000SC || |
523 | current_cpu_type() == CPU_R4000MC || | |
524 | current_cpu_type() == CPU_R4400SC || | |
525 | current_cpu_type() == CPU_R4400MC) { | |
1da177e4 | 526 | r4k_blast_scache(); |
617667ba RB |
527 | return; |
528 | } | |
529 | ||
530 | r4k_blast_dcache(); | |
1da177e4 LT |
531 | } |
532 | ||
533 | static void r4k_flush_cache_mm(struct mm_struct *mm) | |
534 | { | |
535 | if (!cpu_has_dc_aliases) | |
536 | return; | |
537 | ||
48a26e60 | 538 | r4k_on_each_cpu(local_r4k_flush_cache_mm, mm); |
1da177e4 LT |
539 | } |
540 | ||
541 | struct flush_cache_page_args { | |
542 | struct vm_area_struct *vma; | |
6ec25809 | 543 | unsigned long addr; |
de62893b | 544 | unsigned long pfn; |
1da177e4 LT |
545 | }; |
546 | ||
547 | static inline void local_r4k_flush_cache_page(void *args) | |
548 | { | |
549 | struct flush_cache_page_args *fcp_args = args; | |
550 | struct vm_area_struct *vma = fcp_args->vma; | |
6ec25809 | 551 | unsigned long addr = fcp_args->addr; |
db813fe5 | 552 | struct page *page = pfn_to_page(fcp_args->pfn); |
1da177e4 LT |
553 | int exec = vma->vm_flags & VM_EXEC; |
554 | struct mm_struct *mm = vma->vm_mm; | |
c9c5023d | 555 | int map_coherent = 0; |
1da177e4 | 556 | pgd_t *pgdp; |
c6e8b587 | 557 | pud_t *pudp; |
1da177e4 LT |
558 | pmd_t *pmdp; |
559 | pte_t *ptep; | |
db813fe5 | 560 | void *vaddr; |
1da177e4 | 561 | |
79acf83e RB |
562 | /* |
563 | * If ownes no valid ASID yet, cannot possibly have gotten | |
564 | * this page into the cache. | |
565 | */ | |
a76ab5c1 | 566 | if (!has_valid_asid(mm)) |
79acf83e RB |
567 | return; |
568 | ||
6ec25809 RB |
569 | addr &= PAGE_MASK; |
570 | pgdp = pgd_offset(mm, addr); | |
571 | pudp = pud_offset(pgdp, addr); | |
572 | pmdp = pmd_offset(pudp, addr); | |
573 | ptep = pte_offset(pmdp, addr); | |
1da177e4 LT |
574 | |
575 | /* | |
576 | * If the page isn't marked valid, the page cannot possibly be | |
577 | * in the cache. | |
578 | */ | |
526af35e | 579 | if (!(pte_present(*ptep))) |
1da177e4 LT |
580 | return; |
581 | ||
db813fe5 RB |
582 | if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID)) |
583 | vaddr = NULL; | |
584 | else { | |
585 | /* | |
586 | * Use kmap_coherent or kmap_atomic to do flushes for | |
587 | * another ASID than the current one. | |
588 | */ | |
c9c5023d | 589 | map_coherent = (cpu_has_dc_aliases && |
e1534ae9 KS |
590 | page_mapcount(page) && |
591 | !Page_dcache_dirty(page)); | |
c9c5023d | 592 | if (map_coherent) |
db813fe5 RB |
593 | vaddr = kmap_coherent(page, addr); |
594 | else | |
9c02048f | 595 | vaddr = kmap_atomic(page); |
db813fe5 | 596 | addr = (unsigned long)vaddr; |
1da177e4 LT |
597 | } |
598 | ||
1da177e4 | 599 | if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) { |
80ca69f4 MC |
600 | vaddr ? r4k_blast_dcache_page(addr) : |
601 | r4k_blast_dcache_user_page(addr); | |
39b8d525 RB |
602 | if (exec && !cpu_icache_snoops_remote_store) |
603 | r4k_blast_scache_page(addr); | |
1da177e4 LT |
604 | } |
605 | if (exec) { | |
db813fe5 | 606 | if (vaddr && cpu_has_vtag_icache && mm == current->active_mm) { |
1da177e4 LT |
607 | int cpu = smp_processor_id(); |
608 | ||
26a51b27 TS |
609 | if (cpu_context(cpu, mm) != 0) |
610 | drop_mmu_context(mm, cpu); | |
1da177e4 | 611 | } else |
80ca69f4 MC |
612 | vaddr ? r4k_blast_icache_page(addr) : |
613 | r4k_blast_icache_user_page(addr); | |
db813fe5 RB |
614 | } |
615 | ||
616 | if (vaddr) { | |
c9c5023d | 617 | if (map_coherent) |
db813fe5 RB |
618 | kunmap_coherent(); |
619 | else | |
9c02048f | 620 | kunmap_atomic(vaddr); |
1da177e4 LT |
621 | } |
622 | } | |
623 | ||
6ec25809 RB |
624 | static void r4k_flush_cache_page(struct vm_area_struct *vma, |
625 | unsigned long addr, unsigned long pfn) | |
1da177e4 LT |
626 | { |
627 | struct flush_cache_page_args args; | |
628 | ||
1da177e4 | 629 | args.vma = vma; |
6ec25809 | 630 | args.addr = addr; |
de62893b | 631 | args.pfn = pfn; |
1da177e4 | 632 | |
48a26e60 | 633 | r4k_on_each_cpu(local_r4k_flush_cache_page, &args); |
1da177e4 LT |
634 | } |
635 | ||
636 | static inline void local_r4k_flush_data_cache_page(void * addr) | |
637 | { | |
638 | r4k_blast_dcache_page((unsigned long) addr); | |
639 | } | |
640 | ||
641 | static void r4k_flush_data_cache_page(unsigned long addr) | |
642 | { | |
a754f708 RB |
643 | if (in_atomic()) |
644 | local_r4k_flush_data_cache_page((void *)addr); | |
645 | else | |
48a26e60 | 646 | r4k_on_each_cpu(local_r4k_flush_data_cache_page, (void *) addr); |
1da177e4 LT |
647 | } |
648 | ||
649 | struct flush_icache_range_args { | |
d4264f18 AN |
650 | unsigned long start; |
651 | unsigned long end; | |
1da177e4 LT |
652 | }; |
653 | ||
e0cee3ee | 654 | static inline void local_r4k_flush_icache_range(unsigned long start, unsigned long end) |
1da177e4 | 655 | { |
1da177e4 | 656 | if (!cpu_has_ic_fills_f_dc) { |
73f40352 | 657 | if (end - start >= dcache_size) { |
1da177e4 LT |
658 | r4k_blast_dcache(); |
659 | } else { | |
10a3dabd | 660 | R4600_HIT_CACHEOP_WAR_IMPL; |
41700e73 | 661 | protected_blast_dcache_range(start, end); |
1da177e4 | 662 | } |
1da177e4 LT |
663 | } |
664 | ||
665 | if (end - start > icache_size) | |
666 | r4k_blast_icache(); | |
14bd8c08 RB |
667 | else { |
668 | switch (boot_cpu_type()) { | |
669 | case CPU_LOONGSON2: | |
bad009fe | 670 | protected_loongson2_blast_icache_range(start, end); |
14bd8c08 RB |
671 | break; |
672 | ||
673 | default: | |
bad009fe | 674 | protected_blast_icache_range(start, end); |
14bd8c08 RB |
675 | break; |
676 | } | |
677 | } | |
4676f935 LY |
678 | #ifdef CONFIG_EVA |
679 | /* | |
680 | * Due to all possible segment mappings, there might cache aliases | |
681 | * caused by the bootloader being in non-EVA mode, and the CPU switching | |
682 | * to EVA during early kernel init. It's best to flush the scache | |
683 | * to avoid having secondary cores fetching stale data and lead to | |
684 | * kernel crashes. | |
685 | */ | |
686 | bc_wback_inv(start, (end - start)); | |
687 | __sync(); | |
688 | #endif | |
1da177e4 LT |
689 | } |
690 | ||
e0cee3ee TB |
691 | static inline void local_r4k_flush_icache_range_ipi(void *args) |
692 | { | |
693 | struct flush_icache_range_args *fir_args = args; | |
694 | unsigned long start = fir_args->start; | |
695 | unsigned long end = fir_args->end; | |
696 | ||
697 | local_r4k_flush_icache_range(start, end); | |
698 | } | |
699 | ||
d4264f18 | 700 | static void r4k_flush_icache_range(unsigned long start, unsigned long end) |
1da177e4 LT |
701 | { |
702 | struct flush_icache_range_args args; | |
703 | ||
704 | args.start = start; | |
705 | args.end = end; | |
706 | ||
48a26e60 | 707 | r4k_on_each_cpu(local_r4k_flush_icache_range_ipi, &args); |
cc61c1fe | 708 | instruction_hazard(); |
1da177e4 LT |
709 | } |
710 | ||
8005711c | 711 | #if defined(CONFIG_DMA_NONCOHERENT) || defined(CONFIG_DMA_MAYBE_COHERENT) |
1da177e4 LT |
712 | |
713 | static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size) | |
714 | { | |
1da177e4 LT |
715 | /* Catch bad driver code */ |
716 | BUG_ON(size == 0); | |
717 | ||
ff522058 | 718 | preempt_disable(); |
fc5d2d27 | 719 | if (cpu_has_inclusive_pcaches) { |
41700e73 | 720 | if (size >= scache_size) |
1da177e4 | 721 | r4k_blast_scache(); |
41700e73 AN |
722 | else |
723 | blast_scache_range(addr, addr + size); | |
5596b0b2 | 724 | preempt_enable(); |
d0023c4a | 725 | __sync(); |
1da177e4 LT |
726 | return; |
727 | } | |
728 | ||
729 | /* | |
730 | * Either no secondary cache or the available caches don't have the | |
731 | * subset property so we have to flush the primary caches | |
732 | * explicitly | |
733 | */ | |
39b8d525 | 734 | if (cpu_has_safe_index_cacheops && size >= dcache_size) { |
1da177e4 LT |
735 | r4k_blast_dcache(); |
736 | } else { | |
1da177e4 | 737 | R4600_HIT_CACHEOP_WAR_IMPL; |
41700e73 | 738 | blast_dcache_range(addr, addr + size); |
1da177e4 | 739 | } |
ff522058 | 740 | preempt_enable(); |
1da177e4 LT |
741 | |
742 | bc_wback_inv(addr, size); | |
d0023c4a | 743 | __sync(); |
1da177e4 LT |
744 | } |
745 | ||
746 | static void r4k_dma_cache_inv(unsigned long addr, unsigned long size) | |
747 | { | |
1da177e4 LT |
748 | /* Catch bad driver code */ |
749 | BUG_ON(size == 0); | |
750 | ||
ff522058 | 751 | preempt_disable(); |
fc5d2d27 | 752 | if (cpu_has_inclusive_pcaches) { |
41700e73 | 753 | if (size >= scache_size) |
1da177e4 | 754 | r4k_blast_scache(); |
a8ca8b64 | 755 | else { |
a8ca8b64 RB |
756 | /* |
757 | * There is no clearly documented alignment requirement | |
758 | * for the cache instruction on MIPS processors and | |
759 | * some processors, among them the RM5200 and RM7000 | |
760 | * QED processors will throw an address error for cache | |
70342287 | 761 | * hit ops with insufficient alignment. Solved by |
a8ca8b64 RB |
762 | * aligning the address to cache line size. |
763 | */ | |
e9c33572 | 764 | blast_inv_scache_range(addr, addr + size); |
a8ca8b64 | 765 | } |
5596b0b2 | 766 | preempt_enable(); |
d0023c4a | 767 | __sync(); |
1da177e4 LT |
768 | return; |
769 | } | |
770 | ||
39b8d525 | 771 | if (cpu_has_safe_index_cacheops && size >= dcache_size) { |
1da177e4 LT |
772 | r4k_blast_dcache(); |
773 | } else { | |
1da177e4 | 774 | R4600_HIT_CACHEOP_WAR_IMPL; |
e9c33572 | 775 | blast_inv_dcache_range(addr, addr + size); |
1da177e4 | 776 | } |
ff522058 | 777 | preempt_enable(); |
1da177e4 LT |
778 | |
779 | bc_inv(addr, size); | |
d0023c4a | 780 | __sync(); |
1da177e4 | 781 | } |
8005711c | 782 | #endif /* CONFIG_DMA_NONCOHERENT || CONFIG_DMA_MAYBE_COHERENT */ |
1da177e4 LT |
783 | |
784 | /* | |
785 | * While we're protected against bad userland addresses we don't care | |
786 | * very much about what happens in that case. Usually a segmentation | |
787 | * fault will dump the process later on anyway ... | |
788 | */ | |
789 | static void local_r4k_flush_cache_sigtramp(void * arg) | |
790 | { | |
02fe2c9c TS |
791 | unsigned long ic_lsize = cpu_icache_line_size(); |
792 | unsigned long dc_lsize = cpu_dcache_line_size(); | |
793 | unsigned long sc_lsize = cpu_scache_line_size(); | |
1da177e4 LT |
794 | unsigned long addr = (unsigned long) arg; |
795 | ||
796 | R4600_HIT_CACHEOP_WAR_IMPL; | |
73f40352 CD |
797 | if (dc_lsize) |
798 | protected_writeback_dcache_line(addr & ~(dc_lsize - 1)); | |
4debe4f9 | 799 | if (!cpu_icache_snoops_remote_store && scache_size) |
1da177e4 | 800 | protected_writeback_scache_line(addr & ~(sc_lsize - 1)); |
73f40352 CD |
801 | if (ic_lsize) |
802 | protected_flush_icache_line(addr & ~(ic_lsize - 1)); | |
1da177e4 LT |
803 | if (MIPS4K_ICACHE_REFILL_WAR) { |
804 | __asm__ __volatile__ ( | |
805 | ".set push\n\t" | |
806 | ".set noat\n\t" | |
4ee48627 | 807 | ".set "MIPS_ISA_LEVEL"\n\t" |
875d43e7 | 808 | #ifdef CONFIG_32BIT |
1da177e4 LT |
809 | "la $at,1f\n\t" |
810 | #endif | |
875d43e7 | 811 | #ifdef CONFIG_64BIT |
1da177e4 LT |
812 | "dla $at,1f\n\t" |
813 | #endif | |
814 | "cache %0,($at)\n\t" | |
815 | "nop; nop; nop\n" | |
816 | "1:\n\t" | |
817 | ".set pop" | |
818 | : | |
819 | : "i" (Hit_Invalidate_I)); | |
820 | } | |
821 | if (MIPS_CACHE_SYNC_WAR) | |
822 | __asm__ __volatile__ ("sync"); | |
823 | } | |
824 | ||
825 | static void r4k_flush_cache_sigtramp(unsigned long addr) | |
826 | { | |
48a26e60 | 827 | r4k_on_each_cpu(local_r4k_flush_cache_sigtramp, (void *) addr); |
1da177e4 LT |
828 | } |
829 | ||
830 | static void r4k_flush_icache_all(void) | |
831 | { | |
832 | if (cpu_has_vtag_icache) | |
833 | r4k_blast_icache(); | |
834 | } | |
835 | ||
d9cdc901 RB |
836 | struct flush_kernel_vmap_range_args { |
837 | unsigned long vaddr; | |
838 | int size; | |
839 | }; | |
840 | ||
841 | static inline void local_r4k_flush_kernel_vmap_range(void *args) | |
842 | { | |
843 | struct flush_kernel_vmap_range_args *vmra = args; | |
844 | unsigned long vaddr = vmra->vaddr; | |
845 | int size = vmra->size; | |
846 | ||
847 | /* | |
848 | * Aliases only affect the primary caches so don't bother with | |
849 | * S-caches or T-caches. | |
850 | */ | |
851 | if (cpu_has_safe_index_cacheops && size >= dcache_size) | |
852 | r4k_blast_dcache(); | |
853 | else { | |
854 | R4600_HIT_CACHEOP_WAR_IMPL; | |
855 | blast_dcache_range(vaddr, vaddr + size); | |
856 | } | |
857 | } | |
858 | ||
859 | static void r4k_flush_kernel_vmap_range(unsigned long vaddr, int size) | |
860 | { | |
861 | struct flush_kernel_vmap_range_args args; | |
862 | ||
863 | args.vaddr = (unsigned long) vaddr; | |
864 | args.size = size; | |
865 | ||
866 | r4k_on_each_cpu(local_r4k_flush_kernel_vmap_range, &args); | |
867 | } | |
868 | ||
1da177e4 LT |
869 | static inline void rm7k_erratum31(void) |
870 | { | |
871 | const unsigned long ic_lsize = 32; | |
872 | unsigned long addr; | |
873 | ||
874 | /* RM7000 erratum #31. The icache is screwed at startup. */ | |
875 | write_c0_taglo(0); | |
876 | write_c0_taghi(0); | |
877 | ||
878 | for (addr = INDEX_BASE; addr <= INDEX_BASE + 4096; addr += ic_lsize) { | |
879 | __asm__ __volatile__ ( | |
d8748a3a | 880 | ".set push\n\t" |
1da177e4 LT |
881 | ".set noreorder\n\t" |
882 | ".set mips3\n\t" | |
883 | "cache\t%1, 0(%0)\n\t" | |
884 | "cache\t%1, 0x1000(%0)\n\t" | |
885 | "cache\t%1, 0x2000(%0)\n\t" | |
886 | "cache\t%1, 0x3000(%0)\n\t" | |
887 | "cache\t%2, 0(%0)\n\t" | |
888 | "cache\t%2, 0x1000(%0)\n\t" | |
889 | "cache\t%2, 0x2000(%0)\n\t" | |
890 | "cache\t%2, 0x3000(%0)\n\t" | |
891 | "cache\t%1, 0(%0)\n\t" | |
892 | "cache\t%1, 0x1000(%0)\n\t" | |
893 | "cache\t%1, 0x2000(%0)\n\t" | |
894 | "cache\t%1, 0x3000(%0)\n\t" | |
d8748a3a | 895 | ".set pop\n" |
1da177e4 LT |
896 | : |
897 | : "r" (addr), "i" (Index_Store_Tag_I), "i" (Fill)); | |
898 | } | |
899 | } | |
900 | ||
e2e7f29a | 901 | static inline int alias_74k_erratum(struct cpuinfo_mips *c) |
006a851b | 902 | { |
9213ad77 MR |
903 | unsigned int imp = c->processor_id & PRID_IMP_MASK; |
904 | unsigned int rev = c->processor_id & PRID_REV_MASK; | |
e2e7f29a | 905 | int present = 0; |
9213ad77 | 906 | |
006a851b SH |
907 | /* |
908 | * Early versions of the 74K do not update the cache tags on a | |
909 | * vtag miss/ptag hit which can occur in the case of KSEG0/KUSEG | |
e2e7f29a MR |
910 | * aliases. In this case it is better to treat the cache as always |
911 | * having aliases. Also disable the synonym tag update feature | |
912 | * where available. In this case no opportunistic tag update will | |
913 | * happen where a load causes a virtual address miss but a physical | |
914 | * address hit during a D-cache look-up. | |
006a851b | 915 | */ |
9213ad77 MR |
916 | switch (imp) { |
917 | case PRID_IMP_74K: | |
918 | if (rev <= PRID_REV_ENCODE_332(2, 4, 0)) | |
e2e7f29a | 919 | present = 1; |
9213ad77 MR |
920 | if (rev == PRID_REV_ENCODE_332(2, 4, 0)) |
921 | write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND); | |
922 | break; | |
923 | case PRID_IMP_1074K: | |
924 | if (rev <= PRID_REV_ENCODE_332(1, 1, 0)) { | |
e2e7f29a | 925 | present = 1; |
9213ad77 MR |
926 | write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND); |
927 | } | |
928 | break; | |
929 | default: | |
930 | BUG(); | |
006a851b | 931 | } |
e2e7f29a MR |
932 | |
933 | return present; | |
006a851b SH |
934 | } |
935 | ||
d74b0172 KC |
936 | static void b5k_instruction_hazard(void) |
937 | { | |
938 | __sync(); | |
939 | __sync(); | |
940 | __asm__ __volatile__( | |
941 | " nop; nop; nop; nop; nop; nop; nop; nop\n" | |
942 | " nop; nop; nop; nop; nop; nop; nop; nop\n" | |
943 | " nop; nop; nop; nop; nop; nop; nop; nop\n" | |
944 | " nop; nop; nop; nop; nop; nop; nop; nop\n" | |
945 | : : : "memory"); | |
946 | } | |
947 | ||
078a55fc | 948 | static char *way_string[] = { NULL, "direct mapped", "2-way", |
1e18ac7a PB |
949 | "3-way", "4-way", "5-way", "6-way", "7-way", "8-way", |
950 | "9-way", "10-way", "11-way", "12-way", | |
951 | "13-way", "14-way", "15-way", "16-way", | |
1da177e4 LT |
952 | }; |
953 | ||
078a55fc | 954 | static void probe_pcache(void) |
1da177e4 LT |
955 | { |
956 | struct cpuinfo_mips *c = ¤t_cpu_data; | |
957 | unsigned int config = read_c0_config(); | |
958 | unsigned int prid = read_c0_prid(); | |
e2e7f29a | 959 | int has_74k_erratum = 0; |
1da177e4 LT |
960 | unsigned long config1; |
961 | unsigned int lsize; | |
962 | ||
69f24d17 | 963 | switch (current_cpu_type()) { |
1da177e4 LT |
964 | case CPU_R4600: /* QED style two way caches? */ |
965 | case CPU_R4700: | |
966 | case CPU_R5000: | |
967 | case CPU_NEVADA: | |
968 | icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); | |
969 | c->icache.linesz = 16 << ((config & CONF_IB) >> 5); | |
970 | c->icache.ways = 2; | |
3c68da79 | 971 | c->icache.waybit = __ffs(icache_size/2); |
1da177e4 LT |
972 | |
973 | dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); | |
974 | c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); | |
975 | c->dcache.ways = 2; | |
3c68da79 | 976 | c->dcache.waybit= __ffs(dcache_size/2); |
1da177e4 LT |
977 | |
978 | c->options |= MIPS_CPU_CACHE_CDEX_P; | |
979 | break; | |
980 | ||
981 | case CPU_R5432: | |
982 | case CPU_R5500: | |
983 | icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); | |
984 | c->icache.linesz = 16 << ((config & CONF_IB) >> 5); | |
985 | c->icache.ways = 2; | |
986 | c->icache.waybit= 0; | |
987 | ||
988 | dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); | |
989 | c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); | |
990 | c->dcache.ways = 2; | |
991 | c->dcache.waybit = 0; | |
992 | ||
5864810b | 993 | c->options |= MIPS_CPU_CACHE_CDEX_P | MIPS_CPU_PREFETCH; |
1da177e4 LT |
994 | break; |
995 | ||
996 | case CPU_TX49XX: | |
997 | icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); | |
998 | c->icache.linesz = 16 << ((config & CONF_IB) >> 5); | |
999 | c->icache.ways = 4; | |
1000 | c->icache.waybit= 0; | |
1001 | ||
1002 | dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); | |
1003 | c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); | |
1004 | c->dcache.ways = 4; | |
1005 | c->dcache.waybit = 0; | |
1006 | ||
1007 | c->options |= MIPS_CPU_CACHE_CDEX_P; | |
de862b48 | 1008 | c->options |= MIPS_CPU_PREFETCH; |
1da177e4 LT |
1009 | break; |
1010 | ||
1011 | case CPU_R4000PC: | |
1012 | case CPU_R4000SC: | |
1013 | case CPU_R4000MC: | |
1014 | case CPU_R4400PC: | |
1015 | case CPU_R4400SC: | |
1016 | case CPU_R4400MC: | |
1017 | case CPU_R4300: | |
1018 | icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); | |
1019 | c->icache.linesz = 16 << ((config & CONF_IB) >> 5); | |
1020 | c->icache.ways = 1; | |
70342287 | 1021 | c->icache.waybit = 0; /* doesn't matter */ |
1da177e4 LT |
1022 | |
1023 | dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); | |
1024 | c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); | |
1025 | c->dcache.ways = 1; | |
1026 | c->dcache.waybit = 0; /* does not matter */ | |
1027 | ||
1028 | c->options |= MIPS_CPU_CACHE_CDEX_P; | |
1029 | break; | |
1030 | ||
1031 | case CPU_R10000: | |
1032 | case CPU_R12000: | |
44d921b2 | 1033 | case CPU_R14000: |
30577391 | 1034 | case CPU_R16000: |
1da177e4 LT |
1035 | icache_size = 1 << (12 + ((config & R10K_CONF_IC) >> 29)); |
1036 | c->icache.linesz = 64; | |
1037 | c->icache.ways = 2; | |
1038 | c->icache.waybit = 0; | |
1039 | ||
1040 | dcache_size = 1 << (12 + ((config & R10K_CONF_DC) >> 26)); | |
1041 | c->dcache.linesz = 32; | |
1042 | c->dcache.ways = 2; | |
1043 | c->dcache.waybit = 0; | |
1044 | ||
1045 | c->options |= MIPS_CPU_PREFETCH; | |
1046 | break; | |
1047 | ||
1048 | case CPU_VR4133: | |
2874fe55 | 1049 | write_c0_config(config & ~VR41_CONF_P4K); |
1da177e4 LT |
1050 | case CPU_VR4131: |
1051 | /* Workaround for cache instruction bug of VR4131 */ | |
1052 | if (c->processor_id == 0x0c80U || c->processor_id == 0x0c81U || | |
1053 | c->processor_id == 0x0c82U) { | |
4e8ab361 YY |
1054 | config |= 0x00400000U; |
1055 | if (c->processor_id == 0x0c80U) | |
1056 | config |= VR41_CONF_BP; | |
1da177e4 | 1057 | write_c0_config(config); |
1058ecda YY |
1058 | } else |
1059 | c->options |= MIPS_CPU_CACHE_CDEX_P; | |
1060 | ||
1da177e4 LT |
1061 | icache_size = 1 << (10 + ((config & CONF_IC) >> 9)); |
1062 | c->icache.linesz = 16 << ((config & CONF_IB) >> 5); | |
1063 | c->icache.ways = 2; | |
3c68da79 | 1064 | c->icache.waybit = __ffs(icache_size/2); |
1da177e4 LT |
1065 | |
1066 | dcache_size = 1 << (10 + ((config & CONF_DC) >> 6)); | |
1067 | c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); | |
1068 | c->dcache.ways = 2; | |
3c68da79 | 1069 | c->dcache.waybit = __ffs(dcache_size/2); |
1da177e4 LT |
1070 | break; |
1071 | ||
1072 | case CPU_VR41XX: | |
1073 | case CPU_VR4111: | |
1074 | case CPU_VR4121: | |
1075 | case CPU_VR4122: | |
1076 | case CPU_VR4181: | |
1077 | case CPU_VR4181A: | |
1078 | icache_size = 1 << (10 + ((config & CONF_IC) >> 9)); | |
1079 | c->icache.linesz = 16 << ((config & CONF_IB) >> 5); | |
1080 | c->icache.ways = 1; | |
70342287 | 1081 | c->icache.waybit = 0; /* doesn't matter */ |
1da177e4 LT |
1082 | |
1083 | dcache_size = 1 << (10 + ((config & CONF_DC) >> 6)); | |
1084 | c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); | |
1085 | c->dcache.ways = 1; | |
1086 | c->dcache.waybit = 0; /* does not matter */ | |
1087 | ||
1088 | c->options |= MIPS_CPU_CACHE_CDEX_P; | |
1089 | break; | |
1090 | ||
1091 | case CPU_RM7000: | |
1092 | rm7k_erratum31(); | |
1093 | ||
1da177e4 LT |
1094 | icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); |
1095 | c->icache.linesz = 16 << ((config & CONF_IB) >> 5); | |
1096 | c->icache.ways = 4; | |
3c68da79 | 1097 | c->icache.waybit = __ffs(icache_size / c->icache.ways); |
1da177e4 LT |
1098 | |
1099 | dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); | |
1100 | c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); | |
1101 | c->dcache.ways = 4; | |
3c68da79 | 1102 | c->dcache.waybit = __ffs(dcache_size / c->dcache.ways); |
1da177e4 | 1103 | |
1da177e4 | 1104 | c->options |= MIPS_CPU_CACHE_CDEX_P; |
1da177e4 LT |
1105 | c->options |= MIPS_CPU_PREFETCH; |
1106 | break; | |
1107 | ||
2a21c730 FZ |
1108 | case CPU_LOONGSON2: |
1109 | icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); | |
1110 | c->icache.linesz = 16 << ((config & CONF_IB) >> 5); | |
1111 | if (prid & 0x3) | |
1112 | c->icache.ways = 4; | |
1113 | else | |
1114 | c->icache.ways = 2; | |
1115 | c->icache.waybit = 0; | |
1116 | ||
1117 | dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); | |
1118 | c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); | |
1119 | if (prid & 0x3) | |
1120 | c->dcache.ways = 4; | |
1121 | else | |
1122 | c->dcache.ways = 2; | |
1123 | c->dcache.waybit = 0; | |
1124 | break; | |
1125 | ||
c579d310 HC |
1126 | case CPU_LOONGSON3: |
1127 | config1 = read_c0_config1(); | |
1128 | lsize = (config1 >> 19) & 7; | |
1129 | if (lsize) | |
1130 | c->icache.linesz = 2 << lsize; | |
1131 | else | |
1132 | c->icache.linesz = 0; | |
1133 | c->icache.sets = 64 << ((config1 >> 22) & 7); | |
1134 | c->icache.ways = 1 + ((config1 >> 16) & 7); | |
1135 | icache_size = c->icache.sets * | |
1136 | c->icache.ways * | |
1137 | c->icache.linesz; | |
1138 | c->icache.waybit = 0; | |
1139 | ||
1140 | lsize = (config1 >> 10) & 7; | |
1141 | if (lsize) | |
1142 | c->dcache.linesz = 2 << lsize; | |
1143 | else | |
1144 | c->dcache.linesz = 0; | |
1145 | c->dcache.sets = 64 << ((config1 >> 13) & 7); | |
1146 | c->dcache.ways = 1 + ((config1 >> 7) & 7); | |
1147 | dcache_size = c->dcache.sets * | |
1148 | c->dcache.ways * | |
1149 | c->dcache.linesz; | |
1150 | c->dcache.waybit = 0; | |
1151 | break; | |
1152 | ||
18a8cd63 DD |
1153 | case CPU_CAVIUM_OCTEON3: |
1154 | /* For now lie about the number of ways. */ | |
1155 | c->icache.linesz = 128; | |
1156 | c->icache.sets = 16; | |
1157 | c->icache.ways = 8; | |
1158 | c->icache.flags |= MIPS_CACHE_VTAG; | |
1159 | icache_size = c->icache.sets * c->icache.ways * c->icache.linesz; | |
1160 | ||
1161 | c->dcache.linesz = 128; | |
1162 | c->dcache.ways = 8; | |
1163 | c->dcache.sets = 8; | |
1164 | dcache_size = c->dcache.sets * c->dcache.ways * c->dcache.linesz; | |
1165 | c->options |= MIPS_CPU_PREFETCH; | |
1166 | break; | |
1167 | ||
1da177e4 LT |
1168 | default: |
1169 | if (!(config & MIPS_CONF_M)) | |
1170 | panic("Don't know how to probe P-caches on this cpu."); | |
1171 | ||
1172 | /* | |
1173 | * So we seem to be a MIPS32 or MIPS64 CPU | |
1174 | * So let's probe the I-cache ... | |
1175 | */ | |
1176 | config1 = read_c0_config1(); | |
1177 | ||
175cba8c MC |
1178 | lsize = (config1 >> 19) & 7; |
1179 | ||
1180 | /* IL == 7 is reserved */ | |
1181 | if (lsize == 7) | |
1182 | panic("Invalid icache line size"); | |
1183 | ||
1184 | c->icache.linesz = lsize ? 2 << lsize : 0; | |
1185 | ||
dc34b05f | 1186 | c->icache.sets = 32 << (((config1 >> 22) + 1) & 7); |
1da177e4 LT |
1187 | c->icache.ways = 1 + ((config1 >> 16) & 7); |
1188 | ||
1189 | icache_size = c->icache.sets * | |
70342287 RB |
1190 | c->icache.ways * |
1191 | c->icache.linesz; | |
3c68da79 | 1192 | c->icache.waybit = __ffs(icache_size/c->icache.ways); |
1da177e4 LT |
1193 | |
1194 | if (config & 0x8) /* VI bit */ | |
1195 | c->icache.flags |= MIPS_CACHE_VTAG; | |
1196 | ||
1197 | /* | |
1198 | * Now probe the MIPS32 / MIPS64 data cache. | |
1199 | */ | |
1200 | c->dcache.flags = 0; | |
1201 | ||
175cba8c MC |
1202 | lsize = (config1 >> 10) & 7; |
1203 | ||
1204 | /* DL == 7 is reserved */ | |
1205 | if (lsize == 7) | |
1206 | panic("Invalid dcache line size"); | |
1207 | ||
1208 | c->dcache.linesz = lsize ? 2 << lsize : 0; | |
1209 | ||
dc34b05f | 1210 | c->dcache.sets = 32 << (((config1 >> 13) + 1) & 7); |
1da177e4 LT |
1211 | c->dcache.ways = 1 + ((config1 >> 7) & 7); |
1212 | ||
1213 | dcache_size = c->dcache.sets * | |
70342287 RB |
1214 | c->dcache.ways * |
1215 | c->dcache.linesz; | |
3c68da79 | 1216 | c->dcache.waybit = __ffs(dcache_size/c->dcache.ways); |
1da177e4 LT |
1217 | |
1218 | c->options |= MIPS_CPU_PREFETCH; | |
1219 | break; | |
1220 | } | |
1221 | ||
1222 | /* | |
1223 | * Processor configuration sanity check for the R4000SC erratum | |
70342287 | 1224 | * #5. With page sizes larger than 32kB there is no possibility |
1da177e4 LT |
1225 | * to get a VCE exception anymore so we don't care about this |
1226 | * misconfiguration. The case is rather theoretical anyway; | |
1227 | * presumably no vendor is shipping his hardware in the "bad" | |
1228 | * configuration. | |
1229 | */ | |
8ff374b9 MR |
1230 | if ((prid & PRID_IMP_MASK) == PRID_IMP_R4000 && |
1231 | (prid & PRID_REV_MASK) < PRID_REV_R4400 && | |
1da177e4 LT |
1232 | !(config & CONF_SC) && c->icache.linesz != 16 && |
1233 | PAGE_SIZE <= 0x8000) | |
1234 | panic("Improper R4000SC processor configuration detected"); | |
1235 | ||
1236 | /* compute a couple of other cache variables */ | |
1237 | c->icache.waysize = icache_size / c->icache.ways; | |
1238 | c->dcache.waysize = dcache_size / c->dcache.ways; | |
1239 | ||
73f40352 CD |
1240 | c->icache.sets = c->icache.linesz ? |
1241 | icache_size / (c->icache.linesz * c->icache.ways) : 0; | |
1242 | c->dcache.sets = c->dcache.linesz ? | |
1243 | dcache_size / (c->dcache.linesz * c->dcache.ways) : 0; | |
1da177e4 LT |
1244 | |
1245 | /* | |
30577391 JK |
1246 | * R1x000 P-caches are odd in a positive way. They're 32kB 2-way |
1247 | * virtually indexed so normally would suffer from aliases. So | |
1da177e4 LT |
1248 | * normally they'd suffer from aliases but magic in the hardware deals |
1249 | * with that for us so we don't need to take care ourselves. | |
1250 | */ | |
69f24d17 | 1251 | switch (current_cpu_type()) { |
a95970f3 | 1252 | case CPU_20KC: |
505403b6 | 1253 | case CPU_25KF: |
641e97f3 RB |
1254 | case CPU_SB1: |
1255 | case CPU_SB1A: | |
efa0f81c | 1256 | case CPU_XLR: |
de62893b | 1257 | c->dcache.flags |= MIPS_CACHE_PINDEX; |
641e97f3 RB |
1258 | break; |
1259 | ||
d1e344e5 RB |
1260 | case CPU_R10000: |
1261 | case CPU_R12000: | |
44d921b2 | 1262 | case CPU_R14000: |
30577391 | 1263 | case CPU_R16000: |
d1e344e5 | 1264 | break; |
641e97f3 | 1265 | |
bf4aac07 MR |
1266 | case CPU_74K: |
1267 | case CPU_1074K: | |
e2e7f29a | 1268 | has_74k_erratum = alias_74k_erratum(c); |
bf4aac07 | 1269 | /* Fall through. */ |
113c62d9 | 1270 | case CPU_M14KC: |
f8fa4811 | 1271 | case CPU_M14KEC: |
d1e344e5 | 1272 | case CPU_24K: |
98a41de9 | 1273 | case CPU_34K: |
39b8d525 | 1274 | case CPU_1004K: |
26ab96df | 1275 | case CPU_INTERAPTIV: |
aced4cbd | 1276 | case CPU_P5600: |
708ac4b8 | 1277 | case CPU_PROAPTIV: |
f36c4720 | 1278 | case CPU_M5150: |
4695089f | 1279 | case CPU_QEMU_GENERIC: |
4e88a862 | 1280 | case CPU_I6400: |
02dc6bfb MC |
1281 | if (!(read_c0_config7() & MIPS_CONF7_IAR) && |
1282 | (c->icache.waysize > PAGE_SIZE)) | |
1283 | c->icache.flags |= MIPS_CACHE_ALIASES; | |
e2e7f29a | 1284 | if (!has_74k_erratum && (read_c0_config7() & MIPS_CONF7_AR)) { |
02dc6bfb MC |
1285 | /* |
1286 | * Effectively physically indexed dcache, | |
1287 | * thus no virtual aliases. | |
1288 | */ | |
beab375a RB |
1289 | c->dcache.flags |= MIPS_CACHE_PINDEX; |
1290 | break; | |
1291 | } | |
d1e344e5 | 1292 | default: |
e2e7f29a | 1293 | if (has_74k_erratum || c->dcache.waysize > PAGE_SIZE) |
beab375a | 1294 | c->dcache.flags |= MIPS_CACHE_ALIASES; |
d1e344e5 | 1295 | } |
1da177e4 | 1296 | |
69f24d17 | 1297 | switch (current_cpu_type()) { |
1da177e4 LT |
1298 | case CPU_20KC: |
1299 | /* | |
1300 | * Some older 20Kc chips doesn't have the 'VI' bit in | |
1301 | * the config register. | |
1302 | */ | |
1303 | c->icache.flags |= MIPS_CACHE_VTAG; | |
1304 | break; | |
1305 | ||
270717a8 | 1306 | case CPU_ALCHEMY: |
1da177e4 LT |
1307 | c->icache.flags |= MIPS_CACHE_IC_F_DC; |
1308 | break; | |
1da177e4 | 1309 | |
14bd8c08 RB |
1310 | case CPU_LOONGSON2: |
1311 | /* | |
1312 | * LOONGSON2 has 4 way icache, but when using indexed cache op, | |
1313 | * one op will act on all 4 ways | |
1314 | */ | |
1315 | c->icache.ways = 1; | |
1316 | } | |
2a21c730 | 1317 | |
1da177e4 LT |
1318 | printk("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n", |
1319 | icache_size >> 10, | |
7fc7316a | 1320 | c->icache.flags & MIPS_CACHE_VTAG ? "VIVT" : "VIPT", |
1da177e4 LT |
1321 | way_string[c->icache.ways], c->icache.linesz); |
1322 | ||
64bfca5c RB |
1323 | printk("Primary data cache %ldkB, %s, %s, %s, linesize %d bytes\n", |
1324 | dcache_size >> 10, way_string[c->dcache.ways], | |
1325 | (c->dcache.flags & MIPS_CACHE_PINDEX) ? "PIPT" : "VIPT", | |
1326 | (c->dcache.flags & MIPS_CACHE_ALIASES) ? | |
1327 | "cache aliases" : "no aliases", | |
1328 | c->dcache.linesz); | |
1da177e4 LT |
1329 | } |
1330 | ||
1331 | /* | |
1332 | * If you even _breathe_ on this function, look at the gcc output and make sure | |
1333 | * it does not pop things on and off the stack for the cache sizing loop that | |
1334 | * executes in KSEG1 space or else you will crash and burn badly. You have | |
1335 | * been warned. | |
1336 | */ | |
078a55fc | 1337 | static int probe_scache(void) |
1da177e4 | 1338 | { |
1da177e4 LT |
1339 | unsigned long flags, addr, begin, end, pow2; |
1340 | unsigned int config = read_c0_config(); | |
1341 | struct cpuinfo_mips *c = ¤t_cpu_data; | |
1da177e4 LT |
1342 | |
1343 | if (config & CONF_SC) | |
1344 | return 0; | |
1345 | ||
e001e528 | 1346 | begin = (unsigned long) &_stext; |
1da177e4 LT |
1347 | begin &= ~((4 * 1024 * 1024) - 1); |
1348 | end = begin + (4 * 1024 * 1024); | |
1349 | ||
1350 | /* | |
1351 | * This is such a bitch, you'd think they would make it easy to do | |
1352 | * this. Away you daemons of stupidity! | |
1353 | */ | |
1354 | local_irq_save(flags); | |
1355 | ||
1356 | /* Fill each size-multiple cache line with a valid tag. */ | |
1357 | pow2 = (64 * 1024); | |
1358 | for (addr = begin; addr < end; addr = (begin + pow2)) { | |
1359 | unsigned long *p = (unsigned long *) addr; | |
1360 | __asm__ __volatile__("nop" : : "r" (*p)); /* whee... */ | |
1361 | pow2 <<= 1; | |
1362 | } | |
1363 | ||
1364 | /* Load first line with zero (therefore invalid) tag. */ | |
1365 | write_c0_taglo(0); | |
1366 | write_c0_taghi(0); | |
1367 | __asm__ __volatile__("nop; nop; nop; nop;"); /* avoid the hazard */ | |
1368 | cache_op(Index_Store_Tag_I, begin); | |
1369 | cache_op(Index_Store_Tag_D, begin); | |
1370 | cache_op(Index_Store_Tag_SD, begin); | |
1371 | ||
1372 | /* Now search for the wrap around point. */ | |
1373 | pow2 = (128 * 1024); | |
1da177e4 LT |
1374 | for (addr = begin + (128 * 1024); addr < end; addr = begin + pow2) { |
1375 | cache_op(Index_Load_Tag_SD, addr); | |
1376 | __asm__ __volatile__("nop; nop; nop; nop;"); /* hazard... */ | |
1377 | if (!read_c0_taglo()) | |
1378 | break; | |
1379 | pow2 <<= 1; | |
1380 | } | |
1381 | local_irq_restore(flags); | |
1382 | addr -= begin; | |
1383 | ||
1384 | scache_size = addr; | |
1385 | c->scache.linesz = 16 << ((config & R4K_CONF_SB) >> 22); | |
1386 | c->scache.ways = 1; | |
755af33b | 1387 | c->scache.waybit = 0; /* does not matter */ |
1da177e4 LT |
1388 | |
1389 | return 1; | |
1390 | } | |
1391 | ||
2a21c730 FZ |
1392 | static void __init loongson2_sc_init(void) |
1393 | { | |
1394 | struct cpuinfo_mips *c = ¤t_cpu_data; | |
1395 | ||
1396 | scache_size = 512*1024; | |
1397 | c->scache.linesz = 32; | |
1398 | c->scache.ways = 4; | |
1399 | c->scache.waybit = 0; | |
1400 | c->scache.waysize = scache_size / (c->scache.ways); | |
1401 | c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways); | |
1402 | pr_info("Unified secondary cache %ldkB %s, linesize %d bytes.\n", | |
1403 | scache_size >> 10, way_string[c->scache.ways], c->scache.linesz); | |
1404 | ||
1405 | c->options |= MIPS_CPU_INCLUSIVE_CACHES; | |
1406 | } | |
2a21c730 | 1407 | |
c579d310 HC |
1408 | static void __init loongson3_sc_init(void) |
1409 | { | |
1410 | struct cpuinfo_mips *c = ¤t_cpu_data; | |
1411 | unsigned int config2, lsize; | |
1412 | ||
1413 | config2 = read_c0_config2(); | |
1414 | lsize = (config2 >> 4) & 15; | |
1415 | if (lsize) | |
1416 | c->scache.linesz = 2 << lsize; | |
1417 | else | |
1418 | c->scache.linesz = 0; | |
1419 | c->scache.sets = 64 << ((config2 >> 8) & 15); | |
1420 | c->scache.ways = 1 + (config2 & 15); | |
1421 | ||
1422 | scache_size = c->scache.sets * | |
1423 | c->scache.ways * | |
1424 | c->scache.linesz; | |
1425 | /* Loongson-3 has 4 cores, 1MB scache for each. scaches are shared */ | |
1426 | scache_size *= 4; | |
1427 | c->scache.waybit = 0; | |
1428 | pr_info("Unified secondary cache %ldkB %s, linesize %d bytes.\n", | |
1429 | scache_size >> 10, way_string[c->scache.ways], c->scache.linesz); | |
1430 | if (scache_size) | |
1431 | c->options |= MIPS_CPU_INCLUSIVE_CACHES; | |
1432 | return; | |
1433 | } | |
1434 | ||
1da177e4 LT |
1435 | extern int r5k_sc_init(void); |
1436 | extern int rm7k_sc_init(void); | |
9318c51a | 1437 | extern int mips_sc_init(void); |
1da177e4 | 1438 | |
078a55fc | 1439 | static void setup_scache(void) |
1da177e4 LT |
1440 | { |
1441 | struct cpuinfo_mips *c = ¤t_cpu_data; | |
1442 | unsigned int config = read_c0_config(); | |
1da177e4 LT |
1443 | int sc_present = 0; |
1444 | ||
1445 | /* | |
1446 | * Do the probing thing on R4000SC and R4400SC processors. Other | |
1447 | * processors don't have a S-cache that would be relevant to the | |
603e82ed | 1448 | * Linux memory management. |
1da177e4 | 1449 | */ |
69f24d17 | 1450 | switch (current_cpu_type()) { |
1da177e4 LT |
1451 | case CPU_R4000SC: |
1452 | case CPU_R4000MC: | |
1453 | case CPU_R4400SC: | |
1454 | case CPU_R4400MC: | |
ba5187db | 1455 | sc_present = run_uncached(probe_scache); |
1da177e4 LT |
1456 | if (sc_present) |
1457 | c->options |= MIPS_CPU_CACHE_CDEX_S; | |
1458 | break; | |
1459 | ||
1460 | case CPU_R10000: | |
1461 | case CPU_R12000: | |
44d921b2 | 1462 | case CPU_R14000: |
30577391 | 1463 | case CPU_R16000: |
1da177e4 LT |
1464 | scache_size = 0x80000 << ((config & R10K_CONF_SS) >> 16); |
1465 | c->scache.linesz = 64 << ((config >> 13) & 1); | |
1466 | c->scache.ways = 2; | |
1467 | c->scache.waybit= 0; | |
1468 | sc_present = 1; | |
1469 | break; | |
1470 | ||
1471 | case CPU_R5000: | |
1472 | case CPU_NEVADA: | |
1473 | #ifdef CONFIG_R5000_CPU_SCACHE | |
1474 | r5k_sc_init(); | |
1475 | #endif | |
70342287 | 1476 | return; |
1da177e4 LT |
1477 | |
1478 | case CPU_RM7000: | |
1da177e4 LT |
1479 | #ifdef CONFIG_RM7000_CPU_SCACHE |
1480 | rm7k_sc_init(); | |
1481 | #endif | |
1482 | return; | |
1483 | ||
2a21c730 FZ |
1484 | case CPU_LOONGSON2: |
1485 | loongson2_sc_init(); | |
1486 | return; | |
14bd8c08 | 1487 | |
c579d310 HC |
1488 | case CPU_LOONGSON3: |
1489 | loongson3_sc_init(); | |
1490 | return; | |
1491 | ||
18a8cd63 | 1492 | case CPU_CAVIUM_OCTEON3: |
a3d4fb2d J |
1493 | case CPU_XLP: |
1494 | /* don't need to worry about L2, fully coherent */ | |
1495 | return; | |
2a21c730 | 1496 | |
1da177e4 | 1497 | default: |
adb37892 | 1498 | if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 | |
b5ad2c21 MC |
1499 | MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R1 | |
1500 | MIPS_CPU_ISA_M64R2 | MIPS_CPU_ISA_M64R6)) { | |
9318c51a CD |
1501 | #ifdef CONFIG_MIPS_CPU_SCACHE |
1502 | if (mips_sc_init ()) { | |
1503 | scache_size = c->scache.ways * c->scache.sets * c->scache.linesz; | |
1504 | printk("MIPS secondary cache %ldkB, %s, linesize %d bytes.\n", | |
1505 | scache_size >> 10, | |
1506 | way_string[c->scache.ways], c->scache.linesz); | |
1507 | } | |
1508 | #else | |
1509 | if (!(c->scache.flags & MIPS_CACHE_NOT_PRESENT)) | |
1510 | panic("Dunno how to handle MIPS32 / MIPS64 second level cache"); | |
1511 | #endif | |
1512 | return; | |
1513 | } | |
1da177e4 LT |
1514 | sc_present = 0; |
1515 | } | |
1516 | ||
1517 | if (!sc_present) | |
1518 | return; | |
1519 | ||
1da177e4 LT |
1520 | /* compute a couple of other cache variables */ |
1521 | c->scache.waysize = scache_size / c->scache.ways; | |
1522 | ||
1523 | c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways); | |
1524 | ||
1525 | printk("Unified secondary cache %ldkB %s, linesize %d bytes.\n", | |
1526 | scache_size >> 10, way_string[c->scache.ways], c->scache.linesz); | |
1527 | ||
fc5d2d27 | 1528 | c->options |= MIPS_CPU_INCLUSIVE_CACHES; |
1da177e4 LT |
1529 | } |
1530 | ||
9370b351 SS |
1531 | void au1x00_fixup_config_od(void) |
1532 | { | |
1533 | /* | |
1534 | * c0_config.od (bit 19) was write only (and read as 0) | |
1535 | * on the early revisions of Alchemy SOCs. It disables the bus | |
1536 | * transaction overlapping and needs to be set to fix various errata. | |
1537 | */ | |
1538 | switch (read_c0_prid()) { | |
1539 | case 0x00030100: /* Au1000 DA */ | |
1540 | case 0x00030201: /* Au1000 HA */ | |
1541 | case 0x00030202: /* Au1000 HB */ | |
1542 | case 0x01030200: /* Au1500 AB */ | |
1543 | /* | |
1544 | * Au1100 errata actually keeps silence about this bit, so we set it | |
1545 | * just in case for those revisions that require it to be set according | |
270717a8 | 1546 | * to the (now gone) cpu table. |
9370b351 SS |
1547 | */ |
1548 | case 0x02030200: /* Au1100 AB */ | |
1549 | case 0x02030201: /* Au1100 BA */ | |
1550 | case 0x02030202: /* Au1100 BC */ | |
1551 | set_c0_config(1 << 19); | |
1552 | break; | |
1553 | } | |
1554 | } | |
1555 | ||
89052bd7 RB |
1556 | /* CP0 hazard avoidance. */ |
1557 | #define NXP_BARRIER() \ | |
1558 | __asm__ __volatile__( \ | |
1559 | ".set noreorder\n\t" \ | |
1560 | "nop; nop; nop; nop; nop; nop;\n\t" \ | |
1561 | ".set reorder\n\t") | |
1562 | ||
1563 | static void nxp_pr4450_fixup_config(void) | |
1564 | { | |
1565 | unsigned long config0; | |
1566 | ||
1567 | config0 = read_c0_config(); | |
1568 | ||
1569 | /* clear all three cache coherency fields */ | |
1570 | config0 &= ~(0x7 | (7 << 25) | (7 << 28)); | |
1571 | config0 |= (((_page_cachable_default >> _CACHE_SHIFT) << 0) | | |
1572 | ((_page_cachable_default >> _CACHE_SHIFT) << 25) | | |
1573 | ((_page_cachable_default >> _CACHE_SHIFT) << 28)); | |
1574 | write_c0_config(config0); | |
1575 | NXP_BARRIER(); | |
1576 | } | |
1577 | ||
078a55fc | 1578 | static int cca = -1; |
35133692 CD |
1579 | |
1580 | static int __init cca_setup(char *str) | |
1581 | { | |
1582 | get_option(&str, &cca); | |
1583 | ||
b5b64f2b | 1584 | return 0; |
35133692 CD |
1585 | } |
1586 | ||
b5b64f2b | 1587 | early_param("cca", cca_setup); |
35133692 | 1588 | |
078a55fc | 1589 | static void coherency_setup(void) |
1da177e4 | 1590 | { |
35133692 CD |
1591 | if (cca < 0 || cca > 7) |
1592 | cca = read_c0_config() & CONF_CM_CMASK; | |
1593 | _page_cachable_default = cca << _CACHE_SHIFT; | |
1594 | ||
1595 | pr_debug("Using cache attribute %d\n", cca); | |
1596 | change_c0_config(CONF_CM_CMASK, cca); | |
1da177e4 LT |
1597 | |
1598 | /* | |
1599 | * c0_status.cu=0 specifies that updates by the sc instruction use | |
1600 | * the coherency mode specified by the TLB; 1 means cachable | |
1601 | * coherent update on write will be used. Not all processors have | |
1602 | * this bit and; some wire it to zero, others like Toshiba had the | |
1603 | * silly idea of putting something else there ... | |
1604 | */ | |
10cc3529 | 1605 | switch (current_cpu_type()) { |
1da177e4 LT |
1606 | case CPU_R4000PC: |
1607 | case CPU_R4000SC: | |
1608 | case CPU_R4000MC: | |
1609 | case CPU_R4400PC: | |
1610 | case CPU_R4400SC: | |
1611 | case CPU_R4400MC: | |
1612 | clear_c0_config(CONF_CU); | |
1613 | break; | |
9370b351 | 1614 | /* |
df586d59 | 1615 | * We need to catch the early Alchemy SOCs with |
270717a8 ML |
1616 | * the write-only co_config.od bit and set it back to one on: |
1617 | * Au1000 rev DA, HA, HB; Au1100 AB, BA, BC, Au1500 AB | |
9370b351 | 1618 | */ |
270717a8 | 1619 | case CPU_ALCHEMY: |
9370b351 SS |
1620 | au1x00_fixup_config_od(); |
1621 | break; | |
89052bd7 RB |
1622 | |
1623 | case PRID_IMP_PR4450: | |
1624 | nxp_pr4450_fixup_config(); | |
1625 | break; | |
1da177e4 LT |
1626 | } |
1627 | } | |
1628 | ||
078a55fc | 1629 | static void r4k_cache_error_setup(void) |
1da177e4 | 1630 | { |
641e97f3 RB |
1631 | extern char __weak except_vec2_generic; |
1632 | extern char __weak except_vec2_sb1; | |
1da177e4 | 1633 | |
69f24d17 | 1634 | switch (current_cpu_type()) { |
641e97f3 RB |
1635 | case CPU_SB1: |
1636 | case CPU_SB1A: | |
1637 | set_uncached_handler(0x100, &except_vec2_sb1, 0x80); | |
1638 | break; | |
1639 | ||
1640 | default: | |
1641 | set_uncached_handler(0x100, &except_vec2_generic, 0x80); | |
1642 | break; | |
1643 | } | |
9cd9669b DD |
1644 | } |
1645 | ||
078a55fc | 1646 | void r4k_cache_init(void) |
9cd9669b DD |
1647 | { |
1648 | extern void build_clear_page(void); | |
1649 | extern void build_copy_page(void); | |
1650 | struct cpuinfo_mips *c = ¤t_cpu_data; | |
1da177e4 LT |
1651 | |
1652 | probe_pcache(); | |
1653 | setup_scache(); | |
1654 | ||
1da177e4 LT |
1655 | r4k_blast_dcache_page_setup(); |
1656 | r4k_blast_dcache_page_indexed_setup(); | |
1657 | r4k_blast_dcache_setup(); | |
1658 | r4k_blast_icache_page_setup(); | |
1659 | r4k_blast_icache_page_indexed_setup(); | |
1660 | r4k_blast_icache_setup(); | |
1661 | r4k_blast_scache_page_setup(); | |
1662 | r4k_blast_scache_page_indexed_setup(); | |
1663 | r4k_blast_scache_setup(); | |
4caa906e LY |
1664 | #ifdef CONFIG_EVA |
1665 | r4k_blast_dcache_user_page_setup(); | |
1666 | r4k_blast_icache_user_page_setup(); | |
1667 | #endif | |
1da177e4 LT |
1668 | |
1669 | /* | |
1670 | * Some MIPS32 and MIPS64 processors have physically indexed caches. | |
1671 | * This code supports virtually indexed processors and will be | |
1672 | * unnecessarily inefficient on physically indexed processors. | |
1673 | */ | |
73f40352 CD |
1674 | if (c->dcache.linesz) |
1675 | shm_align_mask = max_t( unsigned long, | |
1676 | c->dcache.sets * c->dcache.linesz - 1, | |
1677 | PAGE_SIZE - 1); | |
1678 | else | |
1679 | shm_align_mask = PAGE_SIZE-1; | |
9c5a3d72 RB |
1680 | |
1681 | __flush_cache_vmap = r4k__flush_cache_vmap; | |
1682 | __flush_cache_vunmap = r4k__flush_cache_vunmap; | |
1683 | ||
db813fe5 | 1684 | flush_cache_all = cache_noop; |
1da177e4 LT |
1685 | __flush_cache_all = r4k___flush_cache_all; |
1686 | flush_cache_mm = r4k_flush_cache_mm; | |
1687 | flush_cache_page = r4k_flush_cache_page; | |
1da177e4 LT |
1688 | flush_cache_range = r4k_flush_cache_range; |
1689 | ||
d9cdc901 RB |
1690 | __flush_kernel_vmap_range = r4k_flush_kernel_vmap_range; |
1691 | ||
1da177e4 LT |
1692 | flush_cache_sigtramp = r4k_flush_cache_sigtramp; |
1693 | flush_icache_all = r4k_flush_icache_all; | |
7e3bfc7c | 1694 | local_flush_data_cache_page = local_r4k_flush_data_cache_page; |
1da177e4 LT |
1695 | flush_data_cache_page = r4k_flush_data_cache_page; |
1696 | flush_icache_range = r4k_flush_icache_range; | |
e0cee3ee | 1697 | local_flush_icache_range = local_r4k_flush_icache_range; |
1da177e4 | 1698 | |
8005711c | 1699 | #if defined(CONFIG_DMA_NONCOHERENT) || defined(CONFIG_DMA_MAYBE_COHERENT) |
39b8d525 RB |
1700 | if (coherentio) { |
1701 | _dma_cache_wback_inv = (void *)cache_noop; | |
1702 | _dma_cache_wback = (void *)cache_noop; | |
1703 | _dma_cache_inv = (void *)cache_noop; | |
1704 | } else { | |
1705 | _dma_cache_wback_inv = r4k_dma_cache_wback_inv; | |
1706 | _dma_cache_wback = r4k_dma_cache_wback_inv; | |
1707 | _dma_cache_inv = r4k_dma_cache_inv; | |
1708 | } | |
1da177e4 LT |
1709 | #endif |
1710 | ||
1da177e4 LT |
1711 | build_clear_page(); |
1712 | build_copy_page(); | |
b6d92b4a SH |
1713 | |
1714 | /* | |
1715 | * We want to run CMP kernels on core with and without coherent | |
1716 | * caches. Therefore, do not use CONFIG_MIPS_CMP to decide whether | |
1717 | * or not to flush caches. | |
1718 | */ | |
1d40cfcd | 1719 | local_r4k___flush_cache_all(NULL); |
b6d92b4a | 1720 | |
1d40cfcd | 1721 | coherency_setup(); |
9cd9669b | 1722 | board_cache_error_setup = r4k_cache_error_setup; |
d74b0172 KC |
1723 | |
1724 | /* | |
1725 | * Per-CPU overrides | |
1726 | */ | |
1727 | switch (current_cpu_type()) { | |
1728 | case CPU_BMIPS4350: | |
1729 | case CPU_BMIPS4380: | |
1730 | /* No IPI is needed because all CPUs share the same D$ */ | |
1731 | flush_data_cache_page = r4k_blast_dcache_page; | |
1732 | break; | |
1733 | case CPU_BMIPS5000: | |
1734 | /* We lose our superpowers if L2 is disabled */ | |
1735 | if (c->scache.flags & MIPS_CACHE_NOT_PRESENT) | |
1736 | break; | |
1737 | ||
1738 | /* I$ fills from D$ just by emptying the write buffers */ | |
1739 | flush_cache_page = (void *)b5k_instruction_hazard; | |
1740 | flush_cache_range = (void *)b5k_instruction_hazard; | |
1741 | flush_cache_sigtramp = (void *)b5k_instruction_hazard; | |
1742 | local_flush_data_cache_page = (void *)b5k_instruction_hazard; | |
1743 | flush_data_cache_page = (void *)b5k_instruction_hazard; | |
1744 | flush_icache_range = (void *)b5k_instruction_hazard; | |
1745 | local_flush_icache_range = (void *)b5k_instruction_hazard; | |
1746 | ||
1747 | /* Cache aliases are handled in hardware; allow HIGHMEM */ | |
1748 | current_cpu_data.dcache.flags &= ~MIPS_CACHE_ALIASES; | |
1749 | ||
1750 | /* Optimization: an L2 flush implicitly flushes the L1 */ | |
1751 | current_cpu_data.options |= MIPS_CPU_INCLUSIVE_CACHES; | |
1752 | break; | |
1753 | } | |
1da177e4 | 1754 | } |
61d73044 JH |
1755 | |
1756 | static int r4k_cache_pm_notifier(struct notifier_block *self, unsigned long cmd, | |
1757 | void *v) | |
1758 | { | |
1759 | switch (cmd) { | |
1760 | case CPU_PM_ENTER_FAILED: | |
1761 | case CPU_PM_EXIT: | |
1762 | coherency_setup(); | |
1763 | break; | |
1764 | } | |
1765 | ||
1766 | return NOTIFY_OK; | |
1767 | } | |
1768 | ||
1769 | static struct notifier_block r4k_cache_pm_notifier_block = { | |
1770 | .notifier_call = r4k_cache_pm_notifier, | |
1771 | }; | |
1772 | ||
1773 | int __init r4k_cache_init_pm(void) | |
1774 | { | |
1775 | return cpu_pm_register_notifier(&r4k_cache_pm_notifier_block); | |
1776 | } | |
1777 | arch_initcall(r4k_cache_init_pm); |