Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
79add627 | 6 | * Copyright (C) 1996 David S. Miller (davem@davemloft.net) |
1da177e4 LT |
7 | * Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002 Ralf Baechle (ralf@gnu.org) |
8 | * Copyright (C) 1999, 2000 Silicon Graphics, Inc. | |
9 | */ | |
a754f708 | 10 | #include <linux/hardirq.h> |
1da177e4 | 11 | #include <linux/init.h> |
db813fe5 | 12 | #include <linux/highmem.h> |
1da177e4 | 13 | #include <linux/kernel.h> |
641e97f3 | 14 | #include <linux/linkage.h> |
1da177e4 | 15 | #include <linux/sched.h> |
631330f5 | 16 | #include <linux/smp.h> |
1da177e4 | 17 | #include <linux/mm.h> |
35133692 | 18 | #include <linux/module.h> |
1da177e4 LT |
19 | #include <linux/bitops.h> |
20 | ||
21 | #include <asm/bcache.h> | |
22 | #include <asm/bootinfo.h> | |
ec74e361 | 23 | #include <asm/cache.h> |
1da177e4 LT |
24 | #include <asm/cacheops.h> |
25 | #include <asm/cpu.h> | |
26 | #include <asm/cpu-features.h> | |
27 | #include <asm/io.h> | |
28 | #include <asm/page.h> | |
29 | #include <asm/pgtable.h> | |
30 | #include <asm/r4kcache.h> | |
e001e528 | 31 | #include <asm/sections.h> |
1da177e4 LT |
32 | #include <asm/mmu_context.h> |
33 | #include <asm/war.h> | |
ba5187db | 34 | #include <asm/cacheflush.h> /* for run_uncached() */ |
9cd9669b | 35 | #include <asm/traps.h> |
7f3f1d01 RB |
36 | |
37 | /* | |
38 | * Special Variant of smp_call_function for use by cache functions: | |
39 | * | |
40 | * o No return value | |
41 | * o collapses to normal function call on UP kernels | |
42 | * o collapses to normal function call on systems with a single shared | |
43 | * primary cache. | |
c8c5f3fd | 44 | * o doesn't disable interrupts on the local CPU |
7f3f1d01 | 45 | */ |
48a26e60 | 46 | static inline void r4k_on_each_cpu(void (*func) (void *info), void *info) |
7f3f1d01 RB |
47 | { |
48 | preempt_disable(); | |
49 | ||
50 | #if !defined(CONFIG_MIPS_MT_SMP) && !defined(CONFIG_MIPS_MT_SMTC) | |
48a26e60 | 51 | smp_call_function(func, info, 1); |
7f3f1d01 RB |
52 | #endif |
53 | func(info); | |
54 | preempt_enable(); | |
55 | } | |
56 | ||
39b8d525 RB |
57 | #if defined(CONFIG_MIPS_CMP) |
58 | #define cpu_has_safe_index_cacheops 0 | |
59 | #else | |
60 | #define cpu_has_safe_index_cacheops 1 | |
61 | #endif | |
62 | ||
ec74e361 RB |
63 | /* |
64 | * Must die. | |
65 | */ | |
66 | static unsigned long icache_size __read_mostly; | |
67 | static unsigned long dcache_size __read_mostly; | |
68 | static unsigned long scache_size __read_mostly; | |
1da177e4 LT |
69 | |
70 | /* | |
71 | * Dummy cache handling routines for machines without boardcaches | |
72 | */ | |
73f40352 | 73 | static void cache_noop(void) {} |
1da177e4 LT |
74 | |
75 | static struct bcache_ops no_sc_ops = { | |
73f40352 CD |
76 | .bc_enable = (void *)cache_noop, |
77 | .bc_disable = (void *)cache_noop, | |
78 | .bc_wback_inv = (void *)cache_noop, | |
79 | .bc_inv = (void *)cache_noop | |
1da177e4 LT |
80 | }; |
81 | ||
82 | struct bcache_ops *bcops = &no_sc_ops; | |
83 | ||
330cfe01 TS |
84 | #define cpu_is_r4600_v1_x() ((read_c0_prid() & 0xfffffff0) == 0x00002010) |
85 | #define cpu_is_r4600_v2_x() ((read_c0_prid() & 0xfffffff0) == 0x00002020) | |
1da177e4 LT |
86 | |
87 | #define R4600_HIT_CACHEOP_WAR_IMPL \ | |
88 | do { \ | |
89 | if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x()) \ | |
90 | *(volatile unsigned long *)CKSEG1; \ | |
91 | if (R4600_V1_HIT_CACHEOP_WAR) \ | |
92 | __asm__ __volatile__("nop;nop;nop;nop"); \ | |
93 | } while (0) | |
94 | ||
95 | static void (*r4k_blast_dcache_page)(unsigned long addr); | |
96 | ||
97 | static inline void r4k_blast_dcache_page_dc32(unsigned long addr) | |
98 | { | |
99 | R4600_HIT_CACHEOP_WAR_IMPL; | |
100 | blast_dcache32_page(addr); | |
101 | } | |
102 | ||
605b7ef7 KC |
103 | static inline void r4k_blast_dcache_page_dc64(unsigned long addr) |
104 | { | |
105 | R4600_HIT_CACHEOP_WAR_IMPL; | |
106 | blast_dcache64_page(addr); | |
107 | } | |
108 | ||
234fcd14 | 109 | static void __cpuinit r4k_blast_dcache_page_setup(void) |
1da177e4 LT |
110 | { |
111 | unsigned long dc_lsize = cpu_dcache_line_size(); | |
112 | ||
73f40352 CD |
113 | if (dc_lsize == 0) |
114 | r4k_blast_dcache_page = (void *)cache_noop; | |
115 | else if (dc_lsize == 16) | |
1da177e4 LT |
116 | r4k_blast_dcache_page = blast_dcache16_page; |
117 | else if (dc_lsize == 32) | |
118 | r4k_blast_dcache_page = r4k_blast_dcache_page_dc32; | |
605b7ef7 KC |
119 | else if (dc_lsize == 64) |
120 | r4k_blast_dcache_page = r4k_blast_dcache_page_dc64; | |
1da177e4 LT |
121 | } |
122 | ||
123 | static void (* r4k_blast_dcache_page_indexed)(unsigned long addr); | |
124 | ||
234fcd14 | 125 | static void __cpuinit r4k_blast_dcache_page_indexed_setup(void) |
1da177e4 LT |
126 | { |
127 | unsigned long dc_lsize = cpu_dcache_line_size(); | |
128 | ||
73f40352 CD |
129 | if (dc_lsize == 0) |
130 | r4k_blast_dcache_page_indexed = (void *)cache_noop; | |
131 | else if (dc_lsize == 16) | |
1da177e4 LT |
132 | r4k_blast_dcache_page_indexed = blast_dcache16_page_indexed; |
133 | else if (dc_lsize == 32) | |
134 | r4k_blast_dcache_page_indexed = blast_dcache32_page_indexed; | |
605b7ef7 KC |
135 | else if (dc_lsize == 64) |
136 | r4k_blast_dcache_page_indexed = blast_dcache64_page_indexed; | |
1da177e4 LT |
137 | } |
138 | ||
139 | static void (* r4k_blast_dcache)(void); | |
140 | ||
234fcd14 | 141 | static void __cpuinit r4k_blast_dcache_setup(void) |
1da177e4 LT |
142 | { |
143 | unsigned long dc_lsize = cpu_dcache_line_size(); | |
144 | ||
73f40352 CD |
145 | if (dc_lsize == 0) |
146 | r4k_blast_dcache = (void *)cache_noop; | |
147 | else if (dc_lsize == 16) | |
1da177e4 LT |
148 | r4k_blast_dcache = blast_dcache16; |
149 | else if (dc_lsize == 32) | |
150 | r4k_blast_dcache = blast_dcache32; | |
605b7ef7 KC |
151 | else if (dc_lsize == 64) |
152 | r4k_blast_dcache = blast_dcache64; | |
1da177e4 LT |
153 | } |
154 | ||
155 | /* force code alignment (used for TX49XX_ICACHE_INDEX_INV_WAR) */ | |
156 | #define JUMP_TO_ALIGN(order) \ | |
157 | __asm__ __volatile__( \ | |
158 | "b\t1f\n\t" \ | |
159 | ".align\t" #order "\n\t" \ | |
160 | "1:\n\t" \ | |
161 | ) | |
162 | #define CACHE32_UNROLL32_ALIGN JUMP_TO_ALIGN(10) /* 32 * 32 = 1024 */ | |
163 | #define CACHE32_UNROLL32_ALIGN2 JUMP_TO_ALIGN(11) | |
164 | ||
165 | static inline void blast_r4600_v1_icache32(void) | |
166 | { | |
167 | unsigned long flags; | |
168 | ||
169 | local_irq_save(flags); | |
170 | blast_icache32(); | |
171 | local_irq_restore(flags); | |
172 | } | |
173 | ||
174 | static inline void tx49_blast_icache32(void) | |
175 | { | |
176 | unsigned long start = INDEX_BASE; | |
177 | unsigned long end = start + current_cpu_data.icache.waysize; | |
178 | unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit; | |
179 | unsigned long ws_end = current_cpu_data.icache.ways << | |
180 | current_cpu_data.icache.waybit; | |
181 | unsigned long ws, addr; | |
182 | ||
183 | CACHE32_UNROLL32_ALIGN2; | |
184 | /* I'm in even chunk. blast odd chunks */ | |
42a3b4f2 RB |
185 | for (ws = 0; ws < ws_end; ws += ws_inc) |
186 | for (addr = start + 0x400; addr < end; addr += 0x400 * 2) | |
21a151d8 | 187 | cache32_unroll32(addr|ws, Index_Invalidate_I); |
1da177e4 LT |
188 | CACHE32_UNROLL32_ALIGN; |
189 | /* I'm in odd chunk. blast even chunks */ | |
42a3b4f2 RB |
190 | for (ws = 0; ws < ws_end; ws += ws_inc) |
191 | for (addr = start; addr < end; addr += 0x400 * 2) | |
21a151d8 | 192 | cache32_unroll32(addr|ws, Index_Invalidate_I); |
1da177e4 LT |
193 | } |
194 | ||
195 | static inline void blast_icache32_r4600_v1_page_indexed(unsigned long page) | |
196 | { | |
197 | unsigned long flags; | |
198 | ||
199 | local_irq_save(flags); | |
200 | blast_icache32_page_indexed(page); | |
201 | local_irq_restore(flags); | |
202 | } | |
203 | ||
204 | static inline void tx49_blast_icache32_page_indexed(unsigned long page) | |
205 | { | |
67a3f6de AN |
206 | unsigned long indexmask = current_cpu_data.icache.waysize - 1; |
207 | unsigned long start = INDEX_BASE + (page & indexmask); | |
1da177e4 LT |
208 | unsigned long end = start + PAGE_SIZE; |
209 | unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit; | |
210 | unsigned long ws_end = current_cpu_data.icache.ways << | |
211 | current_cpu_data.icache.waybit; | |
212 | unsigned long ws, addr; | |
213 | ||
214 | CACHE32_UNROLL32_ALIGN2; | |
215 | /* I'm in even chunk. blast odd chunks */ | |
42a3b4f2 RB |
216 | for (ws = 0; ws < ws_end; ws += ws_inc) |
217 | for (addr = start + 0x400; addr < end; addr += 0x400 * 2) | |
21a151d8 | 218 | cache32_unroll32(addr|ws, Index_Invalidate_I); |
1da177e4 LT |
219 | CACHE32_UNROLL32_ALIGN; |
220 | /* I'm in odd chunk. blast even chunks */ | |
42a3b4f2 RB |
221 | for (ws = 0; ws < ws_end; ws += ws_inc) |
222 | for (addr = start; addr < end; addr += 0x400 * 2) | |
21a151d8 | 223 | cache32_unroll32(addr|ws, Index_Invalidate_I); |
1da177e4 LT |
224 | } |
225 | ||
226 | static void (* r4k_blast_icache_page)(unsigned long addr); | |
227 | ||
234fcd14 | 228 | static void __cpuinit r4k_blast_icache_page_setup(void) |
1da177e4 LT |
229 | { |
230 | unsigned long ic_lsize = cpu_icache_line_size(); | |
231 | ||
73f40352 CD |
232 | if (ic_lsize == 0) |
233 | r4k_blast_icache_page = (void *)cache_noop; | |
234 | else if (ic_lsize == 16) | |
1da177e4 LT |
235 | r4k_blast_icache_page = blast_icache16_page; |
236 | else if (ic_lsize == 32) | |
237 | r4k_blast_icache_page = blast_icache32_page; | |
238 | else if (ic_lsize == 64) | |
239 | r4k_blast_icache_page = blast_icache64_page; | |
240 | } | |
241 | ||
242 | ||
243 | static void (* r4k_blast_icache_page_indexed)(unsigned long addr); | |
244 | ||
234fcd14 | 245 | static void __cpuinit r4k_blast_icache_page_indexed_setup(void) |
1da177e4 LT |
246 | { |
247 | unsigned long ic_lsize = cpu_icache_line_size(); | |
248 | ||
73f40352 CD |
249 | if (ic_lsize == 0) |
250 | r4k_blast_icache_page_indexed = (void *)cache_noop; | |
251 | else if (ic_lsize == 16) | |
1da177e4 LT |
252 | r4k_blast_icache_page_indexed = blast_icache16_page_indexed; |
253 | else if (ic_lsize == 32) { | |
02fe2c9c | 254 | if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x()) |
1da177e4 LT |
255 | r4k_blast_icache_page_indexed = |
256 | blast_icache32_r4600_v1_page_indexed; | |
02fe2c9c TS |
257 | else if (TX49XX_ICACHE_INDEX_INV_WAR) |
258 | r4k_blast_icache_page_indexed = | |
259 | tx49_blast_icache32_page_indexed; | |
1da177e4 LT |
260 | else |
261 | r4k_blast_icache_page_indexed = | |
262 | blast_icache32_page_indexed; | |
263 | } else if (ic_lsize == 64) | |
264 | r4k_blast_icache_page_indexed = blast_icache64_page_indexed; | |
265 | } | |
266 | ||
267 | static void (* r4k_blast_icache)(void); | |
268 | ||
234fcd14 | 269 | static void __cpuinit r4k_blast_icache_setup(void) |
1da177e4 LT |
270 | { |
271 | unsigned long ic_lsize = cpu_icache_line_size(); | |
272 | ||
73f40352 CD |
273 | if (ic_lsize == 0) |
274 | r4k_blast_icache = (void *)cache_noop; | |
275 | else if (ic_lsize == 16) | |
1da177e4 LT |
276 | r4k_blast_icache = blast_icache16; |
277 | else if (ic_lsize == 32) { | |
278 | if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x()) | |
279 | r4k_blast_icache = blast_r4600_v1_icache32; | |
280 | else if (TX49XX_ICACHE_INDEX_INV_WAR) | |
281 | r4k_blast_icache = tx49_blast_icache32; | |
282 | else | |
283 | r4k_blast_icache = blast_icache32; | |
284 | } else if (ic_lsize == 64) | |
285 | r4k_blast_icache = blast_icache64; | |
286 | } | |
287 | ||
288 | static void (* r4k_blast_scache_page)(unsigned long addr); | |
289 | ||
234fcd14 | 290 | static void __cpuinit r4k_blast_scache_page_setup(void) |
1da177e4 LT |
291 | { |
292 | unsigned long sc_lsize = cpu_scache_line_size(); | |
293 | ||
4debe4f9 | 294 | if (scache_size == 0) |
73f40352 | 295 | r4k_blast_scache_page = (void *)cache_noop; |
4debe4f9 | 296 | else if (sc_lsize == 16) |
1da177e4 LT |
297 | r4k_blast_scache_page = blast_scache16_page; |
298 | else if (sc_lsize == 32) | |
299 | r4k_blast_scache_page = blast_scache32_page; | |
300 | else if (sc_lsize == 64) | |
301 | r4k_blast_scache_page = blast_scache64_page; | |
302 | else if (sc_lsize == 128) | |
303 | r4k_blast_scache_page = blast_scache128_page; | |
304 | } | |
305 | ||
306 | static void (* r4k_blast_scache_page_indexed)(unsigned long addr); | |
307 | ||
234fcd14 | 308 | static void __cpuinit r4k_blast_scache_page_indexed_setup(void) |
1da177e4 LT |
309 | { |
310 | unsigned long sc_lsize = cpu_scache_line_size(); | |
311 | ||
4debe4f9 | 312 | if (scache_size == 0) |
73f40352 | 313 | r4k_blast_scache_page_indexed = (void *)cache_noop; |
4debe4f9 | 314 | else if (sc_lsize == 16) |
1da177e4 LT |
315 | r4k_blast_scache_page_indexed = blast_scache16_page_indexed; |
316 | else if (sc_lsize == 32) | |
317 | r4k_blast_scache_page_indexed = blast_scache32_page_indexed; | |
318 | else if (sc_lsize == 64) | |
319 | r4k_blast_scache_page_indexed = blast_scache64_page_indexed; | |
320 | else if (sc_lsize == 128) | |
321 | r4k_blast_scache_page_indexed = blast_scache128_page_indexed; | |
322 | } | |
323 | ||
324 | static void (* r4k_blast_scache)(void); | |
325 | ||
234fcd14 | 326 | static void __cpuinit r4k_blast_scache_setup(void) |
1da177e4 LT |
327 | { |
328 | unsigned long sc_lsize = cpu_scache_line_size(); | |
329 | ||
4debe4f9 | 330 | if (scache_size == 0) |
73f40352 | 331 | r4k_blast_scache = (void *)cache_noop; |
4debe4f9 | 332 | else if (sc_lsize == 16) |
1da177e4 LT |
333 | r4k_blast_scache = blast_scache16; |
334 | else if (sc_lsize == 32) | |
335 | r4k_blast_scache = blast_scache32; | |
336 | else if (sc_lsize == 64) | |
337 | r4k_blast_scache = blast_scache64; | |
338 | else if (sc_lsize == 128) | |
339 | r4k_blast_scache = blast_scache128; | |
340 | } | |
341 | ||
1da177e4 LT |
342 | static inline void local_r4k___flush_cache_all(void * args) |
343 | { | |
2a21c730 FZ |
344 | #if defined(CONFIG_CPU_LOONGSON2) |
345 | r4k_blast_scache(); | |
346 | return; | |
347 | #endif | |
1da177e4 LT |
348 | r4k_blast_dcache(); |
349 | r4k_blast_icache(); | |
350 | ||
10cc3529 | 351 | switch (current_cpu_type()) { |
1da177e4 LT |
352 | case CPU_R4000SC: |
353 | case CPU_R4000MC: | |
354 | case CPU_R4400SC: | |
355 | case CPU_R4400MC: | |
356 | case CPU_R10000: | |
357 | case CPU_R12000: | |
44d921b2 | 358 | case CPU_R14000: |
1da177e4 LT |
359 | r4k_blast_scache(); |
360 | } | |
361 | } | |
362 | ||
363 | static void r4k___flush_cache_all(void) | |
364 | { | |
48a26e60 | 365 | r4k_on_each_cpu(local_r4k___flush_cache_all, NULL); |
1da177e4 LT |
366 | } |
367 | ||
a76ab5c1 RB |
368 | static inline int has_valid_asid(const struct mm_struct *mm) |
369 | { | |
370 | #if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC) | |
371 | int i; | |
372 | ||
373 | for_each_online_cpu(i) | |
374 | if (cpu_context(i, mm)) | |
375 | return 1; | |
376 | ||
377 | return 0; | |
378 | #else | |
379 | return cpu_context(smp_processor_id(), mm); | |
380 | #endif | |
381 | } | |
382 | ||
9c5a3d72 RB |
383 | static void r4k__flush_cache_vmap(void) |
384 | { | |
385 | r4k_blast_dcache(); | |
386 | } | |
387 | ||
388 | static void r4k__flush_cache_vunmap(void) | |
389 | { | |
390 | r4k_blast_dcache(); | |
391 | } | |
392 | ||
1da177e4 LT |
393 | static inline void local_r4k_flush_cache_range(void * args) |
394 | { | |
395 | struct vm_area_struct *vma = args; | |
2eaa7ec2 | 396 | int exec = vma->vm_flags & VM_EXEC; |
1da177e4 | 397 | |
a76ab5c1 | 398 | if (!(has_valid_asid(vma->vm_mm))) |
1da177e4 LT |
399 | return; |
400 | ||
0550d9d1 | 401 | r4k_blast_dcache(); |
2eaa7ec2 RB |
402 | if (exec) |
403 | r4k_blast_icache(); | |
1da177e4 LT |
404 | } |
405 | ||
406 | static void r4k_flush_cache_range(struct vm_area_struct *vma, | |
407 | unsigned long start, unsigned long end) | |
408 | { | |
2eaa7ec2 | 409 | int exec = vma->vm_flags & VM_EXEC; |
0550d9d1 | 410 | |
2eaa7ec2 | 411 | if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) |
48a26e60 | 412 | r4k_on_each_cpu(local_r4k_flush_cache_range, vma); |
1da177e4 LT |
413 | } |
414 | ||
415 | static inline void local_r4k_flush_cache_mm(void * args) | |
416 | { | |
417 | struct mm_struct *mm = args; | |
418 | ||
a76ab5c1 | 419 | if (!has_valid_asid(mm)) |
1da177e4 LT |
420 | return; |
421 | ||
1da177e4 LT |
422 | /* |
423 | * Kludge alert. For obscure reasons R4000SC and R4400SC go nuts if we | |
424 | * only flush the primary caches but R10000 and R12000 behave sane ... | |
617667ba RB |
425 | * R4000SC and R4400SC indexed S-cache ops also invalidate primary |
426 | * caches, so we can bail out early. | |
1da177e4 | 427 | */ |
10cc3529 RB |
428 | if (current_cpu_type() == CPU_R4000SC || |
429 | current_cpu_type() == CPU_R4000MC || | |
430 | current_cpu_type() == CPU_R4400SC || | |
431 | current_cpu_type() == CPU_R4400MC) { | |
1da177e4 | 432 | r4k_blast_scache(); |
617667ba RB |
433 | return; |
434 | } | |
435 | ||
436 | r4k_blast_dcache(); | |
1da177e4 LT |
437 | } |
438 | ||
439 | static void r4k_flush_cache_mm(struct mm_struct *mm) | |
440 | { | |
441 | if (!cpu_has_dc_aliases) | |
442 | return; | |
443 | ||
48a26e60 | 444 | r4k_on_each_cpu(local_r4k_flush_cache_mm, mm); |
1da177e4 LT |
445 | } |
446 | ||
447 | struct flush_cache_page_args { | |
448 | struct vm_area_struct *vma; | |
6ec25809 | 449 | unsigned long addr; |
de62893b | 450 | unsigned long pfn; |
1da177e4 LT |
451 | }; |
452 | ||
453 | static inline void local_r4k_flush_cache_page(void *args) | |
454 | { | |
455 | struct flush_cache_page_args *fcp_args = args; | |
456 | struct vm_area_struct *vma = fcp_args->vma; | |
6ec25809 | 457 | unsigned long addr = fcp_args->addr; |
db813fe5 | 458 | struct page *page = pfn_to_page(fcp_args->pfn); |
1da177e4 LT |
459 | int exec = vma->vm_flags & VM_EXEC; |
460 | struct mm_struct *mm = vma->vm_mm; | |
c9c5023d | 461 | int map_coherent = 0; |
1da177e4 | 462 | pgd_t *pgdp; |
c6e8b587 | 463 | pud_t *pudp; |
1da177e4 LT |
464 | pmd_t *pmdp; |
465 | pte_t *ptep; | |
db813fe5 | 466 | void *vaddr; |
1da177e4 | 467 | |
79acf83e RB |
468 | /* |
469 | * If ownes no valid ASID yet, cannot possibly have gotten | |
470 | * this page into the cache. | |
471 | */ | |
a76ab5c1 | 472 | if (!has_valid_asid(mm)) |
79acf83e RB |
473 | return; |
474 | ||
6ec25809 RB |
475 | addr &= PAGE_MASK; |
476 | pgdp = pgd_offset(mm, addr); | |
477 | pudp = pud_offset(pgdp, addr); | |
478 | pmdp = pmd_offset(pudp, addr); | |
479 | ptep = pte_offset(pmdp, addr); | |
1da177e4 LT |
480 | |
481 | /* | |
482 | * If the page isn't marked valid, the page cannot possibly be | |
483 | * in the cache. | |
484 | */ | |
526af35e | 485 | if (!(pte_present(*ptep))) |
1da177e4 LT |
486 | return; |
487 | ||
db813fe5 RB |
488 | if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID)) |
489 | vaddr = NULL; | |
490 | else { | |
491 | /* | |
492 | * Use kmap_coherent or kmap_atomic to do flushes for | |
493 | * another ASID than the current one. | |
494 | */ | |
c9c5023d RB |
495 | map_coherent = (cpu_has_dc_aliases && |
496 | page_mapped(page) && !Page_dcache_dirty(page)); | |
497 | if (map_coherent) | |
db813fe5 RB |
498 | vaddr = kmap_coherent(page, addr); |
499 | else | |
9c02048f | 500 | vaddr = kmap_atomic(page); |
db813fe5 | 501 | addr = (unsigned long)vaddr; |
1da177e4 LT |
502 | } |
503 | ||
1da177e4 | 504 | if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) { |
db813fe5 | 505 | r4k_blast_dcache_page(addr); |
39b8d525 RB |
506 | if (exec && !cpu_icache_snoops_remote_store) |
507 | r4k_blast_scache_page(addr); | |
1da177e4 LT |
508 | } |
509 | if (exec) { | |
db813fe5 | 510 | if (vaddr && cpu_has_vtag_icache && mm == current->active_mm) { |
1da177e4 LT |
511 | int cpu = smp_processor_id(); |
512 | ||
26a51b27 TS |
513 | if (cpu_context(cpu, mm) != 0) |
514 | drop_mmu_context(mm, cpu); | |
1da177e4 | 515 | } else |
db813fe5 RB |
516 | r4k_blast_icache_page(addr); |
517 | } | |
518 | ||
519 | if (vaddr) { | |
c9c5023d | 520 | if (map_coherent) |
db813fe5 RB |
521 | kunmap_coherent(); |
522 | else | |
9c02048f | 523 | kunmap_atomic(vaddr); |
1da177e4 LT |
524 | } |
525 | } | |
526 | ||
6ec25809 RB |
527 | static void r4k_flush_cache_page(struct vm_area_struct *vma, |
528 | unsigned long addr, unsigned long pfn) | |
1da177e4 LT |
529 | { |
530 | struct flush_cache_page_args args; | |
531 | ||
1da177e4 | 532 | args.vma = vma; |
6ec25809 | 533 | args.addr = addr; |
de62893b | 534 | args.pfn = pfn; |
1da177e4 | 535 | |
48a26e60 | 536 | r4k_on_each_cpu(local_r4k_flush_cache_page, &args); |
1da177e4 LT |
537 | } |
538 | ||
539 | static inline void local_r4k_flush_data_cache_page(void * addr) | |
540 | { | |
541 | r4k_blast_dcache_page((unsigned long) addr); | |
542 | } | |
543 | ||
544 | static void r4k_flush_data_cache_page(unsigned long addr) | |
545 | { | |
a754f708 RB |
546 | if (in_atomic()) |
547 | local_r4k_flush_data_cache_page((void *)addr); | |
548 | else | |
48a26e60 | 549 | r4k_on_each_cpu(local_r4k_flush_data_cache_page, (void *) addr); |
1da177e4 LT |
550 | } |
551 | ||
552 | struct flush_icache_range_args { | |
d4264f18 AN |
553 | unsigned long start; |
554 | unsigned long end; | |
1da177e4 LT |
555 | }; |
556 | ||
e0cee3ee | 557 | static inline void local_r4k_flush_icache_range(unsigned long start, unsigned long end) |
1da177e4 | 558 | { |
1da177e4 | 559 | if (!cpu_has_ic_fills_f_dc) { |
73f40352 | 560 | if (end - start >= dcache_size) { |
1da177e4 LT |
561 | r4k_blast_dcache(); |
562 | } else { | |
10a3dabd | 563 | R4600_HIT_CACHEOP_WAR_IMPL; |
41700e73 | 564 | protected_blast_dcache_range(start, end); |
1da177e4 | 565 | } |
1da177e4 LT |
566 | } |
567 | ||
568 | if (end - start > icache_size) | |
569 | r4k_blast_icache(); | |
41700e73 AN |
570 | else |
571 | protected_blast_icache_range(start, end); | |
1da177e4 LT |
572 | } |
573 | ||
e0cee3ee TB |
574 | static inline void local_r4k_flush_icache_range_ipi(void *args) |
575 | { | |
576 | struct flush_icache_range_args *fir_args = args; | |
577 | unsigned long start = fir_args->start; | |
578 | unsigned long end = fir_args->end; | |
579 | ||
580 | local_r4k_flush_icache_range(start, end); | |
581 | } | |
582 | ||
d4264f18 | 583 | static void r4k_flush_icache_range(unsigned long start, unsigned long end) |
1da177e4 LT |
584 | { |
585 | struct flush_icache_range_args args; | |
586 | ||
587 | args.start = start; | |
588 | args.end = end; | |
589 | ||
48a26e60 | 590 | r4k_on_each_cpu(local_r4k_flush_icache_range_ipi, &args); |
cc61c1fe | 591 | instruction_hazard(); |
1da177e4 LT |
592 | } |
593 | ||
1da177e4 LT |
594 | #ifdef CONFIG_DMA_NONCOHERENT |
595 | ||
596 | static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size) | |
597 | { | |
1da177e4 LT |
598 | /* Catch bad driver code */ |
599 | BUG_ON(size == 0); | |
600 | ||
fc5d2d27 | 601 | if (cpu_has_inclusive_pcaches) { |
41700e73 | 602 | if (size >= scache_size) |
1da177e4 | 603 | r4k_blast_scache(); |
41700e73 AN |
604 | else |
605 | blast_scache_range(addr, addr + size); | |
d0023c4a | 606 | __sync(); |
1da177e4 LT |
607 | return; |
608 | } | |
609 | ||
610 | /* | |
611 | * Either no secondary cache or the available caches don't have the | |
612 | * subset property so we have to flush the primary caches | |
613 | * explicitly | |
614 | */ | |
39b8d525 | 615 | if (cpu_has_safe_index_cacheops && size >= dcache_size) { |
1da177e4 LT |
616 | r4k_blast_dcache(); |
617 | } else { | |
1da177e4 | 618 | R4600_HIT_CACHEOP_WAR_IMPL; |
41700e73 | 619 | blast_dcache_range(addr, addr + size); |
1da177e4 LT |
620 | } |
621 | ||
622 | bc_wback_inv(addr, size); | |
d0023c4a | 623 | __sync(); |
1da177e4 LT |
624 | } |
625 | ||
626 | static void r4k_dma_cache_inv(unsigned long addr, unsigned long size) | |
627 | { | |
1da177e4 LT |
628 | /* Catch bad driver code */ |
629 | BUG_ON(size == 0); | |
630 | ||
fc5d2d27 | 631 | if (cpu_has_inclusive_pcaches) { |
41700e73 | 632 | if (size >= scache_size) |
1da177e4 | 633 | r4k_blast_scache(); |
a8ca8b64 RB |
634 | else { |
635 | unsigned long lsize = cpu_scache_line_size(); | |
636 | unsigned long almask = ~(lsize - 1); | |
637 | ||
638 | /* | |
639 | * There is no clearly documented alignment requirement | |
640 | * for the cache instruction on MIPS processors and | |
641 | * some processors, among them the RM5200 and RM7000 | |
642 | * QED processors will throw an address error for cache | |
643 | * hit ops with insufficient alignment. Solved by | |
644 | * aligning the address to cache line size. | |
645 | */ | |
646 | cache_op(Hit_Writeback_Inv_SD, addr & almask); | |
647 | cache_op(Hit_Writeback_Inv_SD, | |
648 | (addr + size - 1) & almask); | |
e9c33572 | 649 | blast_inv_scache_range(addr, addr + size); |
a8ca8b64 | 650 | } |
d0023c4a | 651 | __sync(); |
1da177e4 LT |
652 | return; |
653 | } | |
654 | ||
39b8d525 | 655 | if (cpu_has_safe_index_cacheops && size >= dcache_size) { |
1da177e4 LT |
656 | r4k_blast_dcache(); |
657 | } else { | |
a8ca8b64 RB |
658 | unsigned long lsize = cpu_dcache_line_size(); |
659 | unsigned long almask = ~(lsize - 1); | |
660 | ||
1da177e4 | 661 | R4600_HIT_CACHEOP_WAR_IMPL; |
a8ca8b64 RB |
662 | cache_op(Hit_Writeback_Inv_D, addr & almask); |
663 | cache_op(Hit_Writeback_Inv_D, (addr + size - 1) & almask); | |
e9c33572 | 664 | blast_inv_dcache_range(addr, addr + size); |
1da177e4 LT |
665 | } |
666 | ||
667 | bc_inv(addr, size); | |
d0023c4a | 668 | __sync(); |
1da177e4 LT |
669 | } |
670 | #endif /* CONFIG_DMA_NONCOHERENT */ | |
671 | ||
672 | /* | |
673 | * While we're protected against bad userland addresses we don't care | |
674 | * very much about what happens in that case. Usually a segmentation | |
675 | * fault will dump the process later on anyway ... | |
676 | */ | |
677 | static void local_r4k_flush_cache_sigtramp(void * arg) | |
678 | { | |
02fe2c9c TS |
679 | unsigned long ic_lsize = cpu_icache_line_size(); |
680 | unsigned long dc_lsize = cpu_dcache_line_size(); | |
681 | unsigned long sc_lsize = cpu_scache_line_size(); | |
1da177e4 LT |
682 | unsigned long addr = (unsigned long) arg; |
683 | ||
684 | R4600_HIT_CACHEOP_WAR_IMPL; | |
73f40352 CD |
685 | if (dc_lsize) |
686 | protected_writeback_dcache_line(addr & ~(dc_lsize - 1)); | |
4debe4f9 | 687 | if (!cpu_icache_snoops_remote_store && scache_size) |
1da177e4 | 688 | protected_writeback_scache_line(addr & ~(sc_lsize - 1)); |
73f40352 CD |
689 | if (ic_lsize) |
690 | protected_flush_icache_line(addr & ~(ic_lsize - 1)); | |
1da177e4 LT |
691 | if (MIPS4K_ICACHE_REFILL_WAR) { |
692 | __asm__ __volatile__ ( | |
693 | ".set push\n\t" | |
694 | ".set noat\n\t" | |
695 | ".set mips3\n\t" | |
875d43e7 | 696 | #ifdef CONFIG_32BIT |
1da177e4 LT |
697 | "la $at,1f\n\t" |
698 | #endif | |
875d43e7 | 699 | #ifdef CONFIG_64BIT |
1da177e4 LT |
700 | "dla $at,1f\n\t" |
701 | #endif | |
702 | "cache %0,($at)\n\t" | |
703 | "nop; nop; nop\n" | |
704 | "1:\n\t" | |
705 | ".set pop" | |
706 | : | |
707 | : "i" (Hit_Invalidate_I)); | |
708 | } | |
709 | if (MIPS_CACHE_SYNC_WAR) | |
710 | __asm__ __volatile__ ("sync"); | |
711 | } | |
712 | ||
713 | static void r4k_flush_cache_sigtramp(unsigned long addr) | |
714 | { | |
48a26e60 | 715 | r4k_on_each_cpu(local_r4k_flush_cache_sigtramp, (void *) addr); |
1da177e4 LT |
716 | } |
717 | ||
718 | static void r4k_flush_icache_all(void) | |
719 | { | |
720 | if (cpu_has_vtag_icache) | |
721 | r4k_blast_icache(); | |
722 | } | |
723 | ||
d9cdc901 RB |
724 | struct flush_kernel_vmap_range_args { |
725 | unsigned long vaddr; | |
726 | int size; | |
727 | }; | |
728 | ||
729 | static inline void local_r4k_flush_kernel_vmap_range(void *args) | |
730 | { | |
731 | struct flush_kernel_vmap_range_args *vmra = args; | |
732 | unsigned long vaddr = vmra->vaddr; | |
733 | int size = vmra->size; | |
734 | ||
735 | /* | |
736 | * Aliases only affect the primary caches so don't bother with | |
737 | * S-caches or T-caches. | |
738 | */ | |
739 | if (cpu_has_safe_index_cacheops && size >= dcache_size) | |
740 | r4k_blast_dcache(); | |
741 | else { | |
742 | R4600_HIT_CACHEOP_WAR_IMPL; | |
743 | blast_dcache_range(vaddr, vaddr + size); | |
744 | } | |
745 | } | |
746 | ||
747 | static void r4k_flush_kernel_vmap_range(unsigned long vaddr, int size) | |
748 | { | |
749 | struct flush_kernel_vmap_range_args args; | |
750 | ||
751 | args.vaddr = (unsigned long) vaddr; | |
752 | args.size = size; | |
753 | ||
754 | r4k_on_each_cpu(local_r4k_flush_kernel_vmap_range, &args); | |
755 | } | |
756 | ||
1da177e4 LT |
757 | static inline void rm7k_erratum31(void) |
758 | { | |
759 | const unsigned long ic_lsize = 32; | |
760 | unsigned long addr; | |
761 | ||
762 | /* RM7000 erratum #31. The icache is screwed at startup. */ | |
763 | write_c0_taglo(0); | |
764 | write_c0_taghi(0); | |
765 | ||
766 | for (addr = INDEX_BASE; addr <= INDEX_BASE + 4096; addr += ic_lsize) { | |
767 | __asm__ __volatile__ ( | |
d8748a3a | 768 | ".set push\n\t" |
1da177e4 LT |
769 | ".set noreorder\n\t" |
770 | ".set mips3\n\t" | |
771 | "cache\t%1, 0(%0)\n\t" | |
772 | "cache\t%1, 0x1000(%0)\n\t" | |
773 | "cache\t%1, 0x2000(%0)\n\t" | |
774 | "cache\t%1, 0x3000(%0)\n\t" | |
775 | "cache\t%2, 0(%0)\n\t" | |
776 | "cache\t%2, 0x1000(%0)\n\t" | |
777 | "cache\t%2, 0x2000(%0)\n\t" | |
778 | "cache\t%2, 0x3000(%0)\n\t" | |
779 | "cache\t%1, 0(%0)\n\t" | |
780 | "cache\t%1, 0x1000(%0)\n\t" | |
781 | "cache\t%1, 0x2000(%0)\n\t" | |
782 | "cache\t%1, 0x3000(%0)\n\t" | |
d8748a3a | 783 | ".set pop\n" |
1da177e4 LT |
784 | : |
785 | : "r" (addr), "i" (Index_Store_Tag_I), "i" (Fill)); | |
786 | } | |
787 | } | |
788 | ||
234fcd14 | 789 | static char *way_string[] __cpuinitdata = { NULL, "direct mapped", "2-way", |
1da177e4 LT |
790 | "3-way", "4-way", "5-way", "6-way", "7-way", "8-way" |
791 | }; | |
792 | ||
234fcd14 | 793 | static void __cpuinit probe_pcache(void) |
1da177e4 LT |
794 | { |
795 | struct cpuinfo_mips *c = ¤t_cpu_data; | |
796 | unsigned int config = read_c0_config(); | |
797 | unsigned int prid = read_c0_prid(); | |
798 | unsigned long config1; | |
799 | unsigned int lsize; | |
800 | ||
801 | switch (c->cputype) { | |
802 | case CPU_R4600: /* QED style two way caches? */ | |
803 | case CPU_R4700: | |
804 | case CPU_R5000: | |
805 | case CPU_NEVADA: | |
806 | icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); | |
807 | c->icache.linesz = 16 << ((config & CONF_IB) >> 5); | |
808 | c->icache.ways = 2; | |
3c68da79 | 809 | c->icache.waybit = __ffs(icache_size/2); |
1da177e4 LT |
810 | |
811 | dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); | |
812 | c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); | |
813 | c->dcache.ways = 2; | |
3c68da79 | 814 | c->dcache.waybit= __ffs(dcache_size/2); |
1da177e4 LT |
815 | |
816 | c->options |= MIPS_CPU_CACHE_CDEX_P; | |
817 | break; | |
818 | ||
819 | case CPU_R5432: | |
820 | case CPU_R5500: | |
821 | icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); | |
822 | c->icache.linesz = 16 << ((config & CONF_IB) >> 5); | |
823 | c->icache.ways = 2; | |
824 | c->icache.waybit= 0; | |
825 | ||
826 | dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); | |
827 | c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); | |
828 | c->dcache.ways = 2; | |
829 | c->dcache.waybit = 0; | |
830 | ||
5864810b | 831 | c->options |= MIPS_CPU_CACHE_CDEX_P | MIPS_CPU_PREFETCH; |
1da177e4 LT |
832 | break; |
833 | ||
834 | case CPU_TX49XX: | |
835 | icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); | |
836 | c->icache.linesz = 16 << ((config & CONF_IB) >> 5); | |
837 | c->icache.ways = 4; | |
838 | c->icache.waybit= 0; | |
839 | ||
840 | dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); | |
841 | c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); | |
842 | c->dcache.ways = 4; | |
843 | c->dcache.waybit = 0; | |
844 | ||
845 | c->options |= MIPS_CPU_CACHE_CDEX_P; | |
de862b48 | 846 | c->options |= MIPS_CPU_PREFETCH; |
1da177e4 LT |
847 | break; |
848 | ||
849 | case CPU_R4000PC: | |
850 | case CPU_R4000SC: | |
851 | case CPU_R4000MC: | |
852 | case CPU_R4400PC: | |
853 | case CPU_R4400SC: | |
854 | case CPU_R4400MC: | |
855 | case CPU_R4300: | |
856 | icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); | |
857 | c->icache.linesz = 16 << ((config & CONF_IB) >> 5); | |
858 | c->icache.ways = 1; | |
859 | c->icache.waybit = 0; /* doesn't matter */ | |
860 | ||
861 | dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); | |
862 | c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); | |
863 | c->dcache.ways = 1; | |
864 | c->dcache.waybit = 0; /* does not matter */ | |
865 | ||
866 | c->options |= MIPS_CPU_CACHE_CDEX_P; | |
867 | break; | |
868 | ||
869 | case CPU_R10000: | |
870 | case CPU_R12000: | |
44d921b2 | 871 | case CPU_R14000: |
1da177e4 LT |
872 | icache_size = 1 << (12 + ((config & R10K_CONF_IC) >> 29)); |
873 | c->icache.linesz = 64; | |
874 | c->icache.ways = 2; | |
875 | c->icache.waybit = 0; | |
876 | ||
877 | dcache_size = 1 << (12 + ((config & R10K_CONF_DC) >> 26)); | |
878 | c->dcache.linesz = 32; | |
879 | c->dcache.ways = 2; | |
880 | c->dcache.waybit = 0; | |
881 | ||
882 | c->options |= MIPS_CPU_PREFETCH; | |
883 | break; | |
884 | ||
885 | case CPU_VR4133: | |
2874fe55 | 886 | write_c0_config(config & ~VR41_CONF_P4K); |
1da177e4 LT |
887 | case CPU_VR4131: |
888 | /* Workaround for cache instruction bug of VR4131 */ | |
889 | if (c->processor_id == 0x0c80U || c->processor_id == 0x0c81U || | |
890 | c->processor_id == 0x0c82U) { | |
4e8ab361 YY |
891 | config |= 0x00400000U; |
892 | if (c->processor_id == 0x0c80U) | |
893 | config |= VR41_CONF_BP; | |
1da177e4 | 894 | write_c0_config(config); |
1058ecda YY |
895 | } else |
896 | c->options |= MIPS_CPU_CACHE_CDEX_P; | |
897 | ||
1da177e4 LT |
898 | icache_size = 1 << (10 + ((config & CONF_IC) >> 9)); |
899 | c->icache.linesz = 16 << ((config & CONF_IB) >> 5); | |
900 | c->icache.ways = 2; | |
3c68da79 | 901 | c->icache.waybit = __ffs(icache_size/2); |
1da177e4 LT |
902 | |
903 | dcache_size = 1 << (10 + ((config & CONF_DC) >> 6)); | |
904 | c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); | |
905 | c->dcache.ways = 2; | |
3c68da79 | 906 | c->dcache.waybit = __ffs(dcache_size/2); |
1da177e4 LT |
907 | break; |
908 | ||
909 | case CPU_VR41XX: | |
910 | case CPU_VR4111: | |
911 | case CPU_VR4121: | |
912 | case CPU_VR4122: | |
913 | case CPU_VR4181: | |
914 | case CPU_VR4181A: | |
915 | icache_size = 1 << (10 + ((config & CONF_IC) >> 9)); | |
916 | c->icache.linesz = 16 << ((config & CONF_IB) >> 5); | |
917 | c->icache.ways = 1; | |
918 | c->icache.waybit = 0; /* doesn't matter */ | |
919 | ||
920 | dcache_size = 1 << (10 + ((config & CONF_DC) >> 6)); | |
921 | c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); | |
922 | c->dcache.ways = 1; | |
923 | c->dcache.waybit = 0; /* does not matter */ | |
924 | ||
925 | c->options |= MIPS_CPU_CACHE_CDEX_P; | |
926 | break; | |
927 | ||
928 | case CPU_RM7000: | |
929 | rm7k_erratum31(); | |
930 | ||
931 | case CPU_RM9000: | |
932 | icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); | |
933 | c->icache.linesz = 16 << ((config & CONF_IB) >> 5); | |
934 | c->icache.ways = 4; | |
3c68da79 | 935 | c->icache.waybit = __ffs(icache_size / c->icache.ways); |
1da177e4 LT |
936 | |
937 | dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); | |
938 | c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); | |
939 | c->dcache.ways = 4; | |
3c68da79 | 940 | c->dcache.waybit = __ffs(dcache_size / c->dcache.ways); |
1da177e4 LT |
941 | |
942 | #if !defined(CONFIG_SMP) || !defined(RM9000_CDEX_SMP_WAR) | |
943 | c->options |= MIPS_CPU_CACHE_CDEX_P; | |
944 | #endif | |
945 | c->options |= MIPS_CPU_PREFETCH; | |
946 | break; | |
947 | ||
2a21c730 FZ |
948 | case CPU_LOONGSON2: |
949 | icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); | |
950 | c->icache.linesz = 16 << ((config & CONF_IB) >> 5); | |
951 | if (prid & 0x3) | |
952 | c->icache.ways = 4; | |
953 | else | |
954 | c->icache.ways = 2; | |
955 | c->icache.waybit = 0; | |
956 | ||
957 | dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); | |
958 | c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); | |
959 | if (prid & 0x3) | |
960 | c->dcache.ways = 4; | |
961 | else | |
962 | c->dcache.ways = 2; | |
963 | c->dcache.waybit = 0; | |
964 | break; | |
965 | ||
1da177e4 LT |
966 | default: |
967 | if (!(config & MIPS_CONF_M)) | |
968 | panic("Don't know how to probe P-caches on this cpu."); | |
969 | ||
970 | /* | |
971 | * So we seem to be a MIPS32 or MIPS64 CPU | |
972 | * So let's probe the I-cache ... | |
973 | */ | |
974 | config1 = read_c0_config1(); | |
975 | ||
976 | if ((lsize = ((config1 >> 19) & 7))) | |
977 | c->icache.linesz = 2 << lsize; | |
978 | else | |
979 | c->icache.linesz = lsize; | |
dc34b05f | 980 | c->icache.sets = 32 << (((config1 >> 22) + 1) & 7); |
1da177e4 LT |
981 | c->icache.ways = 1 + ((config1 >> 16) & 7); |
982 | ||
983 | icache_size = c->icache.sets * | |
984 | c->icache.ways * | |
985 | c->icache.linesz; | |
3c68da79 | 986 | c->icache.waybit = __ffs(icache_size/c->icache.ways); |
1da177e4 LT |
987 | |
988 | if (config & 0x8) /* VI bit */ | |
989 | c->icache.flags |= MIPS_CACHE_VTAG; | |
990 | ||
991 | /* | |
992 | * Now probe the MIPS32 / MIPS64 data cache. | |
993 | */ | |
994 | c->dcache.flags = 0; | |
995 | ||
996 | if ((lsize = ((config1 >> 10) & 7))) | |
997 | c->dcache.linesz = 2 << lsize; | |
998 | else | |
999 | c->dcache.linesz= lsize; | |
dc34b05f | 1000 | c->dcache.sets = 32 << (((config1 >> 13) + 1) & 7); |
1da177e4 LT |
1001 | c->dcache.ways = 1 + ((config1 >> 7) & 7); |
1002 | ||
1003 | dcache_size = c->dcache.sets * | |
1004 | c->dcache.ways * | |
1005 | c->dcache.linesz; | |
3c68da79 | 1006 | c->dcache.waybit = __ffs(dcache_size/c->dcache.ways); |
1da177e4 LT |
1007 | |
1008 | c->options |= MIPS_CPU_PREFETCH; | |
1009 | break; | |
1010 | } | |
1011 | ||
1012 | /* | |
1013 | * Processor configuration sanity check for the R4000SC erratum | |
1014 | * #5. With page sizes larger than 32kB there is no possibility | |
1015 | * to get a VCE exception anymore so we don't care about this | |
1016 | * misconfiguration. The case is rather theoretical anyway; | |
1017 | * presumably no vendor is shipping his hardware in the "bad" | |
1018 | * configuration. | |
1019 | */ | |
1020 | if ((prid & 0xff00) == PRID_IMP_R4000 && (prid & 0xff) < 0x40 && | |
1021 | !(config & CONF_SC) && c->icache.linesz != 16 && | |
1022 | PAGE_SIZE <= 0x8000) | |
1023 | panic("Improper R4000SC processor configuration detected"); | |
1024 | ||
1025 | /* compute a couple of other cache variables */ | |
1026 | c->icache.waysize = icache_size / c->icache.ways; | |
1027 | c->dcache.waysize = dcache_size / c->dcache.ways; | |
1028 | ||
73f40352 CD |
1029 | c->icache.sets = c->icache.linesz ? |
1030 | icache_size / (c->icache.linesz * c->icache.ways) : 0; | |
1031 | c->dcache.sets = c->dcache.linesz ? | |
1032 | dcache_size / (c->dcache.linesz * c->dcache.ways) : 0; | |
1da177e4 LT |
1033 | |
1034 | /* | |
1035 | * R10000 and R12000 P-caches are odd in a positive way. They're 32kB | |
1036 | * 2-way virtually indexed so normally would suffer from aliases. So | |
1037 | * normally they'd suffer from aliases but magic in the hardware deals | |
1038 | * with that for us so we don't need to take care ourselves. | |
1039 | */ | |
d1e344e5 | 1040 | switch (c->cputype) { |
a95970f3 | 1041 | case CPU_20KC: |
505403b6 | 1042 | case CPU_25KF: |
641e97f3 RB |
1043 | case CPU_SB1: |
1044 | case CPU_SB1A: | |
efa0f81c | 1045 | case CPU_XLR: |
de62893b | 1046 | c->dcache.flags |= MIPS_CACHE_PINDEX; |
641e97f3 RB |
1047 | break; |
1048 | ||
d1e344e5 RB |
1049 | case CPU_R10000: |
1050 | case CPU_R12000: | |
44d921b2 | 1051 | case CPU_R14000: |
d1e344e5 | 1052 | break; |
641e97f3 | 1053 | |
113c62d9 | 1054 | case CPU_M14KC: |
d1e344e5 | 1055 | case CPU_24K: |
98a41de9 | 1056 | case CPU_34K: |
2e78ae3f | 1057 | case CPU_74K: |
39b8d525 | 1058 | case CPU_1004K: |
beab375a RB |
1059 | if ((read_c0_config7() & (1 << 16))) { |
1060 | /* effectively physically indexed dcache, | |
1061 | thus no virtual aliases. */ | |
1062 | c->dcache.flags |= MIPS_CACHE_PINDEX; | |
1063 | break; | |
1064 | } | |
d1e344e5 | 1065 | default: |
beab375a RB |
1066 | if (c->dcache.waysize > PAGE_SIZE) |
1067 | c->dcache.flags |= MIPS_CACHE_ALIASES; | |
d1e344e5 | 1068 | } |
1da177e4 LT |
1069 | |
1070 | switch (c->cputype) { | |
1071 | case CPU_20KC: | |
1072 | /* | |
1073 | * Some older 20Kc chips doesn't have the 'VI' bit in | |
1074 | * the config register. | |
1075 | */ | |
1076 | c->icache.flags |= MIPS_CACHE_VTAG; | |
1077 | break; | |
1078 | ||
270717a8 | 1079 | case CPU_ALCHEMY: |
1da177e4 LT |
1080 | c->icache.flags |= MIPS_CACHE_IC_F_DC; |
1081 | break; | |
1082 | } | |
1083 | ||
2a21c730 FZ |
1084 | #ifdef CONFIG_CPU_LOONGSON2 |
1085 | /* | |
1086 | * LOONGSON2 has 4 way icache, but when using indexed cache op, | |
1087 | * one op will act on all 4 ways | |
1088 | */ | |
1089 | c->icache.ways = 1; | |
1090 | #endif | |
1091 | ||
1da177e4 LT |
1092 | printk("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n", |
1093 | icache_size >> 10, | |
7fc7316a | 1094 | c->icache.flags & MIPS_CACHE_VTAG ? "VIVT" : "VIPT", |
1da177e4 LT |
1095 | way_string[c->icache.ways], c->icache.linesz); |
1096 | ||
64bfca5c RB |
1097 | printk("Primary data cache %ldkB, %s, %s, %s, linesize %d bytes\n", |
1098 | dcache_size >> 10, way_string[c->dcache.ways], | |
1099 | (c->dcache.flags & MIPS_CACHE_PINDEX) ? "PIPT" : "VIPT", | |
1100 | (c->dcache.flags & MIPS_CACHE_ALIASES) ? | |
1101 | "cache aliases" : "no aliases", | |
1102 | c->dcache.linesz); | |
1da177e4 LT |
1103 | } |
1104 | ||
1105 | /* | |
1106 | * If you even _breathe_ on this function, look at the gcc output and make sure | |
1107 | * it does not pop things on and off the stack for the cache sizing loop that | |
1108 | * executes in KSEG1 space or else you will crash and burn badly. You have | |
1109 | * been warned. | |
1110 | */ | |
234fcd14 | 1111 | static int __cpuinit probe_scache(void) |
1da177e4 | 1112 | { |
1da177e4 LT |
1113 | unsigned long flags, addr, begin, end, pow2; |
1114 | unsigned int config = read_c0_config(); | |
1115 | struct cpuinfo_mips *c = ¤t_cpu_data; | |
1da177e4 LT |
1116 | |
1117 | if (config & CONF_SC) | |
1118 | return 0; | |
1119 | ||
e001e528 | 1120 | begin = (unsigned long) &_stext; |
1da177e4 LT |
1121 | begin &= ~((4 * 1024 * 1024) - 1); |
1122 | end = begin + (4 * 1024 * 1024); | |
1123 | ||
1124 | /* | |
1125 | * This is such a bitch, you'd think they would make it easy to do | |
1126 | * this. Away you daemons of stupidity! | |
1127 | */ | |
1128 | local_irq_save(flags); | |
1129 | ||
1130 | /* Fill each size-multiple cache line with a valid tag. */ | |
1131 | pow2 = (64 * 1024); | |
1132 | for (addr = begin; addr < end; addr = (begin + pow2)) { | |
1133 | unsigned long *p = (unsigned long *) addr; | |
1134 | __asm__ __volatile__("nop" : : "r" (*p)); /* whee... */ | |
1135 | pow2 <<= 1; | |
1136 | } | |
1137 | ||
1138 | /* Load first line with zero (therefore invalid) tag. */ | |
1139 | write_c0_taglo(0); | |
1140 | write_c0_taghi(0); | |
1141 | __asm__ __volatile__("nop; nop; nop; nop;"); /* avoid the hazard */ | |
1142 | cache_op(Index_Store_Tag_I, begin); | |
1143 | cache_op(Index_Store_Tag_D, begin); | |
1144 | cache_op(Index_Store_Tag_SD, begin); | |
1145 | ||
1146 | /* Now search for the wrap around point. */ | |
1147 | pow2 = (128 * 1024); | |
1da177e4 LT |
1148 | for (addr = begin + (128 * 1024); addr < end; addr = begin + pow2) { |
1149 | cache_op(Index_Load_Tag_SD, addr); | |
1150 | __asm__ __volatile__("nop; nop; nop; nop;"); /* hazard... */ | |
1151 | if (!read_c0_taglo()) | |
1152 | break; | |
1153 | pow2 <<= 1; | |
1154 | } | |
1155 | local_irq_restore(flags); | |
1156 | addr -= begin; | |
1157 | ||
1158 | scache_size = addr; | |
1159 | c->scache.linesz = 16 << ((config & R4K_CONF_SB) >> 22); | |
1160 | c->scache.ways = 1; | |
1161 | c->dcache.waybit = 0; /* does not matter */ | |
1162 | ||
1163 | return 1; | |
1164 | } | |
1165 | ||
2a21c730 FZ |
1166 | #if defined(CONFIG_CPU_LOONGSON2) |
1167 | static void __init loongson2_sc_init(void) | |
1168 | { | |
1169 | struct cpuinfo_mips *c = ¤t_cpu_data; | |
1170 | ||
1171 | scache_size = 512*1024; | |
1172 | c->scache.linesz = 32; | |
1173 | c->scache.ways = 4; | |
1174 | c->scache.waybit = 0; | |
1175 | c->scache.waysize = scache_size / (c->scache.ways); | |
1176 | c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways); | |
1177 | pr_info("Unified secondary cache %ldkB %s, linesize %d bytes.\n", | |
1178 | scache_size >> 10, way_string[c->scache.ways], c->scache.linesz); | |
1179 | ||
1180 | c->options |= MIPS_CPU_INCLUSIVE_CACHES; | |
1181 | } | |
1182 | #endif | |
1183 | ||
1da177e4 LT |
1184 | extern int r5k_sc_init(void); |
1185 | extern int rm7k_sc_init(void); | |
9318c51a | 1186 | extern int mips_sc_init(void); |
1da177e4 | 1187 | |
234fcd14 | 1188 | static void __cpuinit setup_scache(void) |
1da177e4 LT |
1189 | { |
1190 | struct cpuinfo_mips *c = ¤t_cpu_data; | |
1191 | unsigned int config = read_c0_config(); | |
1da177e4 LT |
1192 | int sc_present = 0; |
1193 | ||
1194 | /* | |
1195 | * Do the probing thing on R4000SC and R4400SC processors. Other | |
1196 | * processors don't have a S-cache that would be relevant to the | |
603e82ed | 1197 | * Linux memory management. |
1da177e4 LT |
1198 | */ |
1199 | switch (c->cputype) { | |
1200 | case CPU_R4000SC: | |
1201 | case CPU_R4000MC: | |
1202 | case CPU_R4400SC: | |
1203 | case CPU_R4400MC: | |
ba5187db | 1204 | sc_present = run_uncached(probe_scache); |
1da177e4 LT |
1205 | if (sc_present) |
1206 | c->options |= MIPS_CPU_CACHE_CDEX_S; | |
1207 | break; | |
1208 | ||
1209 | case CPU_R10000: | |
1210 | case CPU_R12000: | |
44d921b2 | 1211 | case CPU_R14000: |
1da177e4 LT |
1212 | scache_size = 0x80000 << ((config & R10K_CONF_SS) >> 16); |
1213 | c->scache.linesz = 64 << ((config >> 13) & 1); | |
1214 | c->scache.ways = 2; | |
1215 | c->scache.waybit= 0; | |
1216 | sc_present = 1; | |
1217 | break; | |
1218 | ||
1219 | case CPU_R5000: | |
1220 | case CPU_NEVADA: | |
1221 | #ifdef CONFIG_R5000_CPU_SCACHE | |
1222 | r5k_sc_init(); | |
1223 | #endif | |
1224 | return; | |
1225 | ||
1226 | case CPU_RM7000: | |
1227 | case CPU_RM9000: | |
1228 | #ifdef CONFIG_RM7000_CPU_SCACHE | |
1229 | rm7k_sc_init(); | |
1230 | #endif | |
1231 | return; | |
1232 | ||
2a21c730 FZ |
1233 | #if defined(CONFIG_CPU_LOONGSON2) |
1234 | case CPU_LOONGSON2: | |
1235 | loongson2_sc_init(); | |
1236 | return; | |
1237 | #endif | |
a3d4fb2d J |
1238 | case CPU_XLP: |
1239 | /* don't need to worry about L2, fully coherent */ | |
1240 | return; | |
2a21c730 | 1241 | |
1da177e4 | 1242 | default: |
9318c51a CD |
1243 | if (c->isa_level == MIPS_CPU_ISA_M32R1 || |
1244 | c->isa_level == MIPS_CPU_ISA_M32R2 || | |
1245 | c->isa_level == MIPS_CPU_ISA_M64R1 || | |
1246 | c->isa_level == MIPS_CPU_ISA_M64R2) { | |
1247 | #ifdef CONFIG_MIPS_CPU_SCACHE | |
1248 | if (mips_sc_init ()) { | |
1249 | scache_size = c->scache.ways * c->scache.sets * c->scache.linesz; | |
1250 | printk("MIPS secondary cache %ldkB, %s, linesize %d bytes.\n", | |
1251 | scache_size >> 10, | |
1252 | way_string[c->scache.ways], c->scache.linesz); | |
1253 | } | |
1254 | #else | |
1255 | if (!(c->scache.flags & MIPS_CACHE_NOT_PRESENT)) | |
1256 | panic("Dunno how to handle MIPS32 / MIPS64 second level cache"); | |
1257 | #endif | |
1258 | return; | |
1259 | } | |
1da177e4 LT |
1260 | sc_present = 0; |
1261 | } | |
1262 | ||
1263 | if (!sc_present) | |
1264 | return; | |
1265 | ||
1da177e4 LT |
1266 | /* compute a couple of other cache variables */ |
1267 | c->scache.waysize = scache_size / c->scache.ways; | |
1268 | ||
1269 | c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways); | |
1270 | ||
1271 | printk("Unified secondary cache %ldkB %s, linesize %d bytes.\n", | |
1272 | scache_size >> 10, way_string[c->scache.ways], c->scache.linesz); | |
1273 | ||
fc5d2d27 | 1274 | c->options |= MIPS_CPU_INCLUSIVE_CACHES; |
1da177e4 LT |
1275 | } |
1276 | ||
9370b351 SS |
1277 | void au1x00_fixup_config_od(void) |
1278 | { | |
1279 | /* | |
1280 | * c0_config.od (bit 19) was write only (and read as 0) | |
1281 | * on the early revisions of Alchemy SOCs. It disables the bus | |
1282 | * transaction overlapping and needs to be set to fix various errata. | |
1283 | */ | |
1284 | switch (read_c0_prid()) { | |
1285 | case 0x00030100: /* Au1000 DA */ | |
1286 | case 0x00030201: /* Au1000 HA */ | |
1287 | case 0x00030202: /* Au1000 HB */ | |
1288 | case 0x01030200: /* Au1500 AB */ | |
1289 | /* | |
1290 | * Au1100 errata actually keeps silence about this bit, so we set it | |
1291 | * just in case for those revisions that require it to be set according | |
270717a8 | 1292 | * to the (now gone) cpu table. |
9370b351 SS |
1293 | */ |
1294 | case 0x02030200: /* Au1100 AB */ | |
1295 | case 0x02030201: /* Au1100 BA */ | |
1296 | case 0x02030202: /* Au1100 BC */ | |
1297 | set_c0_config(1 << 19); | |
1298 | break; | |
1299 | } | |
1300 | } | |
1301 | ||
89052bd7 RB |
1302 | /* CP0 hazard avoidance. */ |
1303 | #define NXP_BARRIER() \ | |
1304 | __asm__ __volatile__( \ | |
1305 | ".set noreorder\n\t" \ | |
1306 | "nop; nop; nop; nop; nop; nop;\n\t" \ | |
1307 | ".set reorder\n\t") | |
1308 | ||
1309 | static void nxp_pr4450_fixup_config(void) | |
1310 | { | |
1311 | unsigned long config0; | |
1312 | ||
1313 | config0 = read_c0_config(); | |
1314 | ||
1315 | /* clear all three cache coherency fields */ | |
1316 | config0 &= ~(0x7 | (7 << 25) | (7 << 28)); | |
1317 | config0 |= (((_page_cachable_default >> _CACHE_SHIFT) << 0) | | |
1318 | ((_page_cachable_default >> _CACHE_SHIFT) << 25) | | |
1319 | ((_page_cachable_default >> _CACHE_SHIFT) << 28)); | |
1320 | write_c0_config(config0); | |
1321 | NXP_BARRIER(); | |
1322 | } | |
1323 | ||
35133692 CD |
1324 | static int __cpuinitdata cca = -1; |
1325 | ||
1326 | static int __init cca_setup(char *str) | |
1327 | { | |
1328 | get_option(&str, &cca); | |
1329 | ||
1330 | return 1; | |
1331 | } | |
1332 | ||
1333 | __setup("cca=", cca_setup); | |
1334 | ||
234fcd14 | 1335 | static void __cpuinit coherency_setup(void) |
1da177e4 | 1336 | { |
35133692 CD |
1337 | if (cca < 0 || cca > 7) |
1338 | cca = read_c0_config() & CONF_CM_CMASK; | |
1339 | _page_cachable_default = cca << _CACHE_SHIFT; | |
1340 | ||
1341 | pr_debug("Using cache attribute %d\n", cca); | |
1342 | change_c0_config(CONF_CM_CMASK, cca); | |
1da177e4 LT |
1343 | |
1344 | /* | |
1345 | * c0_status.cu=0 specifies that updates by the sc instruction use | |
1346 | * the coherency mode specified by the TLB; 1 means cachable | |
1347 | * coherent update on write will be used. Not all processors have | |
1348 | * this bit and; some wire it to zero, others like Toshiba had the | |
1349 | * silly idea of putting something else there ... | |
1350 | */ | |
10cc3529 | 1351 | switch (current_cpu_type()) { |
1da177e4 LT |
1352 | case CPU_R4000PC: |
1353 | case CPU_R4000SC: | |
1354 | case CPU_R4000MC: | |
1355 | case CPU_R4400PC: | |
1356 | case CPU_R4400SC: | |
1357 | case CPU_R4400MC: | |
1358 | clear_c0_config(CONF_CU); | |
1359 | break; | |
9370b351 | 1360 | /* |
df586d59 | 1361 | * We need to catch the early Alchemy SOCs with |
270717a8 ML |
1362 | * the write-only co_config.od bit and set it back to one on: |
1363 | * Au1000 rev DA, HA, HB; Au1100 AB, BA, BC, Au1500 AB | |
9370b351 | 1364 | */ |
270717a8 | 1365 | case CPU_ALCHEMY: |
9370b351 SS |
1366 | au1x00_fixup_config_od(); |
1367 | break; | |
89052bd7 RB |
1368 | |
1369 | case PRID_IMP_PR4450: | |
1370 | nxp_pr4450_fixup_config(); | |
1371 | break; | |
1da177e4 LT |
1372 | } |
1373 | } | |
1374 | ||
39b8d525 RB |
1375 | #if defined(CONFIG_DMA_NONCOHERENT) |
1376 | ||
1377 | static int __cpuinitdata coherentio; | |
1378 | ||
1379 | static int __init setcoherentio(char *str) | |
1380 | { | |
1381 | coherentio = 1; | |
1382 | ||
1383 | return 1; | |
1384 | } | |
1385 | ||
1386 | __setup("coherentio", setcoherentio); | |
1387 | #endif | |
1388 | ||
9cd9669b | 1389 | static void __cpuinit r4k_cache_error_setup(void) |
1da177e4 | 1390 | { |
641e97f3 RB |
1391 | extern char __weak except_vec2_generic; |
1392 | extern char __weak except_vec2_sb1; | |
1da177e4 LT |
1393 | struct cpuinfo_mips *c = ¤t_cpu_data; |
1394 | ||
641e97f3 RB |
1395 | switch (c->cputype) { |
1396 | case CPU_SB1: | |
1397 | case CPU_SB1A: | |
1398 | set_uncached_handler(0x100, &except_vec2_sb1, 0x80); | |
1399 | break; | |
1400 | ||
1401 | default: | |
1402 | set_uncached_handler(0x100, &except_vec2_generic, 0x80); | |
1403 | break; | |
1404 | } | |
9cd9669b DD |
1405 | } |
1406 | ||
1407 | void __cpuinit r4k_cache_init(void) | |
1408 | { | |
1409 | extern void build_clear_page(void); | |
1410 | extern void build_copy_page(void); | |
1411 | struct cpuinfo_mips *c = ¤t_cpu_data; | |
1da177e4 LT |
1412 | |
1413 | probe_pcache(); | |
1414 | setup_scache(); | |
1415 | ||
1da177e4 LT |
1416 | r4k_blast_dcache_page_setup(); |
1417 | r4k_blast_dcache_page_indexed_setup(); | |
1418 | r4k_blast_dcache_setup(); | |
1419 | r4k_blast_icache_page_setup(); | |
1420 | r4k_blast_icache_page_indexed_setup(); | |
1421 | r4k_blast_icache_setup(); | |
1422 | r4k_blast_scache_page_setup(); | |
1423 | r4k_blast_scache_page_indexed_setup(); | |
1424 | r4k_blast_scache_setup(); | |
1425 | ||
1426 | /* | |
1427 | * Some MIPS32 and MIPS64 processors have physically indexed caches. | |
1428 | * This code supports virtually indexed processors and will be | |
1429 | * unnecessarily inefficient on physically indexed processors. | |
1430 | */ | |
73f40352 CD |
1431 | if (c->dcache.linesz) |
1432 | shm_align_mask = max_t( unsigned long, | |
1433 | c->dcache.sets * c->dcache.linesz - 1, | |
1434 | PAGE_SIZE - 1); | |
1435 | else | |
1436 | shm_align_mask = PAGE_SIZE-1; | |
9c5a3d72 RB |
1437 | |
1438 | __flush_cache_vmap = r4k__flush_cache_vmap; | |
1439 | __flush_cache_vunmap = r4k__flush_cache_vunmap; | |
1440 | ||
db813fe5 | 1441 | flush_cache_all = cache_noop; |
1da177e4 LT |
1442 | __flush_cache_all = r4k___flush_cache_all; |
1443 | flush_cache_mm = r4k_flush_cache_mm; | |
1444 | flush_cache_page = r4k_flush_cache_page; | |
1da177e4 LT |
1445 | flush_cache_range = r4k_flush_cache_range; |
1446 | ||
d9cdc901 RB |
1447 | __flush_kernel_vmap_range = r4k_flush_kernel_vmap_range; |
1448 | ||
1da177e4 LT |
1449 | flush_cache_sigtramp = r4k_flush_cache_sigtramp; |
1450 | flush_icache_all = r4k_flush_icache_all; | |
7e3bfc7c | 1451 | local_flush_data_cache_page = local_r4k_flush_data_cache_page; |
1da177e4 LT |
1452 | flush_data_cache_page = r4k_flush_data_cache_page; |
1453 | flush_icache_range = r4k_flush_icache_range; | |
e0cee3ee | 1454 | local_flush_icache_range = local_r4k_flush_icache_range; |
1da177e4 | 1455 | |
39b8d525 RB |
1456 | #if defined(CONFIG_DMA_NONCOHERENT) |
1457 | if (coherentio) { | |
1458 | _dma_cache_wback_inv = (void *)cache_noop; | |
1459 | _dma_cache_wback = (void *)cache_noop; | |
1460 | _dma_cache_inv = (void *)cache_noop; | |
1461 | } else { | |
1462 | _dma_cache_wback_inv = r4k_dma_cache_wback_inv; | |
1463 | _dma_cache_wback = r4k_dma_cache_wback_inv; | |
1464 | _dma_cache_inv = r4k_dma_cache_inv; | |
1465 | } | |
1da177e4 LT |
1466 | #endif |
1467 | ||
1da177e4 LT |
1468 | build_clear_page(); |
1469 | build_copy_page(); | |
39b8d525 | 1470 | #if !defined(CONFIG_MIPS_CMP) |
1d40cfcd | 1471 | local_r4k___flush_cache_all(NULL); |
39b8d525 | 1472 | #endif |
1d40cfcd | 1473 | coherency_setup(); |
9cd9669b | 1474 | board_cache_error_setup = r4k_cache_error_setup; |
1da177e4 | 1475 | } |