Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
79add627 | 6 | * Copyright (C) 1996 David S. Miller (davem@davemloft.net) |
1da177e4 LT |
7 | * Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002 Ralf Baechle (ralf@gnu.org) |
8 | * Copyright (C) 1999, 2000 Silicon Graphics, Inc. | |
9 | */ | |
a754f708 | 10 | #include <linux/hardirq.h> |
1da177e4 | 11 | #include <linux/init.h> |
db813fe5 | 12 | #include <linux/highmem.h> |
1da177e4 | 13 | #include <linux/kernel.h> |
641e97f3 | 14 | #include <linux/linkage.h> |
ff522058 | 15 | #include <linux/preempt.h> |
1da177e4 | 16 | #include <linux/sched.h> |
631330f5 | 17 | #include <linux/smp.h> |
1da177e4 | 18 | #include <linux/mm.h> |
35133692 | 19 | #include <linux/module.h> |
1da177e4 LT |
20 | #include <linux/bitops.h> |
21 | ||
22 | #include <asm/bcache.h> | |
23 | #include <asm/bootinfo.h> | |
ec74e361 | 24 | #include <asm/cache.h> |
1da177e4 LT |
25 | #include <asm/cacheops.h> |
26 | #include <asm/cpu.h> | |
27 | #include <asm/cpu-features.h> | |
28 | #include <asm/io.h> | |
29 | #include <asm/page.h> | |
30 | #include <asm/pgtable.h> | |
31 | #include <asm/r4kcache.h> | |
e001e528 | 32 | #include <asm/sections.h> |
1da177e4 LT |
33 | #include <asm/mmu_context.h> |
34 | #include <asm/war.h> | |
ba5187db | 35 | #include <asm/cacheflush.h> /* for run_uncached() */ |
9cd9669b | 36 | #include <asm/traps.h> |
b6d92b4a | 37 | #include <asm/dma-coherence.h> |
7f3f1d01 RB |
38 | |
39 | /* | |
40 | * Special Variant of smp_call_function for use by cache functions: | |
41 | * | |
42 | * o No return value | |
43 | * o collapses to normal function call on UP kernels | |
44 | * o collapses to normal function call on systems with a single shared | |
45 | * primary cache. | |
c8c5f3fd | 46 | * o doesn't disable interrupts on the local CPU |
7f3f1d01 | 47 | */ |
48a26e60 | 48 | static inline void r4k_on_each_cpu(void (*func) (void *info), void *info) |
7f3f1d01 RB |
49 | { |
50 | preempt_disable(); | |
51 | ||
52 | #if !defined(CONFIG_MIPS_MT_SMP) && !defined(CONFIG_MIPS_MT_SMTC) | |
48a26e60 | 53 | smp_call_function(func, info, 1); |
7f3f1d01 RB |
54 | #endif |
55 | func(info); | |
56 | preempt_enable(); | |
57 | } | |
58 | ||
39b8d525 RB |
59 | #if defined(CONFIG_MIPS_CMP) |
60 | #define cpu_has_safe_index_cacheops 0 | |
61 | #else | |
62 | #define cpu_has_safe_index_cacheops 1 | |
63 | #endif | |
64 | ||
ec74e361 RB |
65 | /* |
66 | * Must die. | |
67 | */ | |
68 | static unsigned long icache_size __read_mostly; | |
69 | static unsigned long dcache_size __read_mostly; | |
70 | static unsigned long scache_size __read_mostly; | |
1da177e4 LT |
71 | |
72 | /* | |
73 | * Dummy cache handling routines for machines without boardcaches | |
74 | */ | |
73f40352 | 75 | static void cache_noop(void) {} |
1da177e4 LT |
76 | |
77 | static struct bcache_ops no_sc_ops = { | |
73f40352 CD |
78 | .bc_enable = (void *)cache_noop, |
79 | .bc_disable = (void *)cache_noop, | |
80 | .bc_wback_inv = (void *)cache_noop, | |
81 | .bc_inv = (void *)cache_noop | |
1da177e4 LT |
82 | }; |
83 | ||
84 | struct bcache_ops *bcops = &no_sc_ops; | |
85 | ||
330cfe01 TS |
86 | #define cpu_is_r4600_v1_x() ((read_c0_prid() & 0xfffffff0) == 0x00002010) |
87 | #define cpu_is_r4600_v2_x() ((read_c0_prid() & 0xfffffff0) == 0x00002020) | |
1da177e4 LT |
88 | |
89 | #define R4600_HIT_CACHEOP_WAR_IMPL \ | |
90 | do { \ | |
91 | if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x()) \ | |
92 | *(volatile unsigned long *)CKSEG1; \ | |
93 | if (R4600_V1_HIT_CACHEOP_WAR) \ | |
94 | __asm__ __volatile__("nop;nop;nop;nop"); \ | |
95 | } while (0) | |
96 | ||
97 | static void (*r4k_blast_dcache_page)(unsigned long addr); | |
98 | ||
99 | static inline void r4k_blast_dcache_page_dc32(unsigned long addr) | |
100 | { | |
101 | R4600_HIT_CACHEOP_WAR_IMPL; | |
102 | blast_dcache32_page(addr); | |
103 | } | |
104 | ||
605b7ef7 KC |
105 | static inline void r4k_blast_dcache_page_dc64(unsigned long addr) |
106 | { | |
107 | R4600_HIT_CACHEOP_WAR_IMPL; | |
108 | blast_dcache64_page(addr); | |
109 | } | |
110 | ||
078a55fc | 111 | static void r4k_blast_dcache_page_setup(void) |
1da177e4 LT |
112 | { |
113 | unsigned long dc_lsize = cpu_dcache_line_size(); | |
114 | ||
73f40352 CD |
115 | if (dc_lsize == 0) |
116 | r4k_blast_dcache_page = (void *)cache_noop; | |
117 | else if (dc_lsize == 16) | |
1da177e4 LT |
118 | r4k_blast_dcache_page = blast_dcache16_page; |
119 | else if (dc_lsize == 32) | |
120 | r4k_blast_dcache_page = r4k_blast_dcache_page_dc32; | |
605b7ef7 KC |
121 | else if (dc_lsize == 64) |
122 | r4k_blast_dcache_page = r4k_blast_dcache_page_dc64; | |
1da177e4 LT |
123 | } |
124 | ||
125 | static void (* r4k_blast_dcache_page_indexed)(unsigned long addr); | |
126 | ||
078a55fc | 127 | static void r4k_blast_dcache_page_indexed_setup(void) |
1da177e4 LT |
128 | { |
129 | unsigned long dc_lsize = cpu_dcache_line_size(); | |
130 | ||
73f40352 CD |
131 | if (dc_lsize == 0) |
132 | r4k_blast_dcache_page_indexed = (void *)cache_noop; | |
133 | else if (dc_lsize == 16) | |
1da177e4 LT |
134 | r4k_blast_dcache_page_indexed = blast_dcache16_page_indexed; |
135 | else if (dc_lsize == 32) | |
136 | r4k_blast_dcache_page_indexed = blast_dcache32_page_indexed; | |
605b7ef7 KC |
137 | else if (dc_lsize == 64) |
138 | r4k_blast_dcache_page_indexed = blast_dcache64_page_indexed; | |
1da177e4 LT |
139 | } |
140 | ||
f2e3656d SL |
141 | void (* r4k_blast_dcache)(void); |
142 | EXPORT_SYMBOL(r4k_blast_dcache); | |
1da177e4 | 143 | |
078a55fc | 144 | static void r4k_blast_dcache_setup(void) |
1da177e4 LT |
145 | { |
146 | unsigned long dc_lsize = cpu_dcache_line_size(); | |
147 | ||
73f40352 CD |
148 | if (dc_lsize == 0) |
149 | r4k_blast_dcache = (void *)cache_noop; | |
150 | else if (dc_lsize == 16) | |
1da177e4 LT |
151 | r4k_blast_dcache = blast_dcache16; |
152 | else if (dc_lsize == 32) | |
153 | r4k_blast_dcache = blast_dcache32; | |
605b7ef7 KC |
154 | else if (dc_lsize == 64) |
155 | r4k_blast_dcache = blast_dcache64; | |
1da177e4 LT |
156 | } |
157 | ||
158 | /* force code alignment (used for TX49XX_ICACHE_INDEX_INV_WAR) */ | |
159 | #define JUMP_TO_ALIGN(order) \ | |
160 | __asm__ __volatile__( \ | |
161 | "b\t1f\n\t" \ | |
162 | ".align\t" #order "\n\t" \ | |
163 | "1:\n\t" \ | |
164 | ) | |
165 | #define CACHE32_UNROLL32_ALIGN JUMP_TO_ALIGN(10) /* 32 * 32 = 1024 */ | |
70342287 | 166 | #define CACHE32_UNROLL32_ALIGN2 JUMP_TO_ALIGN(11) |
1da177e4 LT |
167 | |
168 | static inline void blast_r4600_v1_icache32(void) | |
169 | { | |
170 | unsigned long flags; | |
171 | ||
172 | local_irq_save(flags); | |
173 | blast_icache32(); | |
174 | local_irq_restore(flags); | |
175 | } | |
176 | ||
177 | static inline void tx49_blast_icache32(void) | |
178 | { | |
179 | unsigned long start = INDEX_BASE; | |
180 | unsigned long end = start + current_cpu_data.icache.waysize; | |
181 | unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit; | |
182 | unsigned long ws_end = current_cpu_data.icache.ways << | |
70342287 | 183 | current_cpu_data.icache.waybit; |
1da177e4 LT |
184 | unsigned long ws, addr; |
185 | ||
186 | CACHE32_UNROLL32_ALIGN2; | |
187 | /* I'm in even chunk. blast odd chunks */ | |
42a3b4f2 RB |
188 | for (ws = 0; ws < ws_end; ws += ws_inc) |
189 | for (addr = start + 0x400; addr < end; addr += 0x400 * 2) | |
21a151d8 | 190 | cache32_unroll32(addr|ws, Index_Invalidate_I); |
1da177e4 LT |
191 | CACHE32_UNROLL32_ALIGN; |
192 | /* I'm in odd chunk. blast even chunks */ | |
42a3b4f2 RB |
193 | for (ws = 0; ws < ws_end; ws += ws_inc) |
194 | for (addr = start; addr < end; addr += 0x400 * 2) | |
21a151d8 | 195 | cache32_unroll32(addr|ws, Index_Invalidate_I); |
1da177e4 LT |
196 | } |
197 | ||
198 | static inline void blast_icache32_r4600_v1_page_indexed(unsigned long page) | |
199 | { | |
200 | unsigned long flags; | |
201 | ||
202 | local_irq_save(flags); | |
203 | blast_icache32_page_indexed(page); | |
204 | local_irq_restore(flags); | |
205 | } | |
206 | ||
207 | static inline void tx49_blast_icache32_page_indexed(unsigned long page) | |
208 | { | |
67a3f6de AN |
209 | unsigned long indexmask = current_cpu_data.icache.waysize - 1; |
210 | unsigned long start = INDEX_BASE + (page & indexmask); | |
1da177e4 LT |
211 | unsigned long end = start + PAGE_SIZE; |
212 | unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit; | |
213 | unsigned long ws_end = current_cpu_data.icache.ways << | |
70342287 | 214 | current_cpu_data.icache.waybit; |
1da177e4 LT |
215 | unsigned long ws, addr; |
216 | ||
217 | CACHE32_UNROLL32_ALIGN2; | |
218 | /* I'm in even chunk. blast odd chunks */ | |
42a3b4f2 RB |
219 | for (ws = 0; ws < ws_end; ws += ws_inc) |
220 | for (addr = start + 0x400; addr < end; addr += 0x400 * 2) | |
21a151d8 | 221 | cache32_unroll32(addr|ws, Index_Invalidate_I); |
1da177e4 LT |
222 | CACHE32_UNROLL32_ALIGN; |
223 | /* I'm in odd chunk. blast even chunks */ | |
42a3b4f2 RB |
224 | for (ws = 0; ws < ws_end; ws += ws_inc) |
225 | for (addr = start; addr < end; addr += 0x400 * 2) | |
21a151d8 | 226 | cache32_unroll32(addr|ws, Index_Invalidate_I); |
1da177e4 LT |
227 | } |
228 | ||
229 | static void (* r4k_blast_icache_page)(unsigned long addr); | |
230 | ||
078a55fc | 231 | static void r4k_blast_icache_page_setup(void) |
1da177e4 LT |
232 | { |
233 | unsigned long ic_lsize = cpu_icache_line_size(); | |
234 | ||
73f40352 CD |
235 | if (ic_lsize == 0) |
236 | r4k_blast_icache_page = (void *)cache_noop; | |
237 | else if (ic_lsize == 16) | |
1da177e4 LT |
238 | r4k_blast_icache_page = blast_icache16_page; |
239 | else if (ic_lsize == 32) | |
240 | r4k_blast_icache_page = blast_icache32_page; | |
241 | else if (ic_lsize == 64) | |
242 | r4k_blast_icache_page = blast_icache64_page; | |
243 | } | |
244 | ||
245 | ||
246 | static void (* r4k_blast_icache_page_indexed)(unsigned long addr); | |
247 | ||
078a55fc | 248 | static void r4k_blast_icache_page_indexed_setup(void) |
1da177e4 LT |
249 | { |
250 | unsigned long ic_lsize = cpu_icache_line_size(); | |
251 | ||
73f40352 CD |
252 | if (ic_lsize == 0) |
253 | r4k_blast_icache_page_indexed = (void *)cache_noop; | |
254 | else if (ic_lsize == 16) | |
1da177e4 LT |
255 | r4k_blast_icache_page_indexed = blast_icache16_page_indexed; |
256 | else if (ic_lsize == 32) { | |
02fe2c9c | 257 | if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x()) |
1da177e4 LT |
258 | r4k_blast_icache_page_indexed = |
259 | blast_icache32_r4600_v1_page_indexed; | |
02fe2c9c TS |
260 | else if (TX49XX_ICACHE_INDEX_INV_WAR) |
261 | r4k_blast_icache_page_indexed = | |
262 | tx49_blast_icache32_page_indexed; | |
1da177e4 LT |
263 | else |
264 | r4k_blast_icache_page_indexed = | |
265 | blast_icache32_page_indexed; | |
266 | } else if (ic_lsize == 64) | |
267 | r4k_blast_icache_page_indexed = blast_icache64_page_indexed; | |
268 | } | |
269 | ||
f2e3656d SL |
270 | void (* r4k_blast_icache)(void); |
271 | EXPORT_SYMBOL(r4k_blast_icache); | |
1da177e4 | 272 | |
078a55fc | 273 | static void r4k_blast_icache_setup(void) |
1da177e4 LT |
274 | { |
275 | unsigned long ic_lsize = cpu_icache_line_size(); | |
276 | ||
73f40352 CD |
277 | if (ic_lsize == 0) |
278 | r4k_blast_icache = (void *)cache_noop; | |
279 | else if (ic_lsize == 16) | |
1da177e4 LT |
280 | r4k_blast_icache = blast_icache16; |
281 | else if (ic_lsize == 32) { | |
282 | if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x()) | |
283 | r4k_blast_icache = blast_r4600_v1_icache32; | |
284 | else if (TX49XX_ICACHE_INDEX_INV_WAR) | |
285 | r4k_blast_icache = tx49_blast_icache32; | |
286 | else | |
287 | r4k_blast_icache = blast_icache32; | |
288 | } else if (ic_lsize == 64) | |
289 | r4k_blast_icache = blast_icache64; | |
290 | } | |
291 | ||
292 | static void (* r4k_blast_scache_page)(unsigned long addr); | |
293 | ||
078a55fc | 294 | static void r4k_blast_scache_page_setup(void) |
1da177e4 LT |
295 | { |
296 | unsigned long sc_lsize = cpu_scache_line_size(); | |
297 | ||
4debe4f9 | 298 | if (scache_size == 0) |
73f40352 | 299 | r4k_blast_scache_page = (void *)cache_noop; |
4debe4f9 | 300 | else if (sc_lsize == 16) |
1da177e4 LT |
301 | r4k_blast_scache_page = blast_scache16_page; |
302 | else if (sc_lsize == 32) | |
303 | r4k_blast_scache_page = blast_scache32_page; | |
304 | else if (sc_lsize == 64) | |
305 | r4k_blast_scache_page = blast_scache64_page; | |
306 | else if (sc_lsize == 128) | |
307 | r4k_blast_scache_page = blast_scache128_page; | |
308 | } | |
309 | ||
310 | static void (* r4k_blast_scache_page_indexed)(unsigned long addr); | |
311 | ||
078a55fc | 312 | static void r4k_blast_scache_page_indexed_setup(void) |
1da177e4 LT |
313 | { |
314 | unsigned long sc_lsize = cpu_scache_line_size(); | |
315 | ||
4debe4f9 | 316 | if (scache_size == 0) |
73f40352 | 317 | r4k_blast_scache_page_indexed = (void *)cache_noop; |
4debe4f9 | 318 | else if (sc_lsize == 16) |
1da177e4 LT |
319 | r4k_blast_scache_page_indexed = blast_scache16_page_indexed; |
320 | else if (sc_lsize == 32) | |
321 | r4k_blast_scache_page_indexed = blast_scache32_page_indexed; | |
322 | else if (sc_lsize == 64) | |
323 | r4k_blast_scache_page_indexed = blast_scache64_page_indexed; | |
324 | else if (sc_lsize == 128) | |
325 | r4k_blast_scache_page_indexed = blast_scache128_page_indexed; | |
326 | } | |
327 | ||
328 | static void (* r4k_blast_scache)(void); | |
329 | ||
078a55fc | 330 | static void r4k_blast_scache_setup(void) |
1da177e4 LT |
331 | { |
332 | unsigned long sc_lsize = cpu_scache_line_size(); | |
333 | ||
4debe4f9 | 334 | if (scache_size == 0) |
73f40352 | 335 | r4k_blast_scache = (void *)cache_noop; |
4debe4f9 | 336 | else if (sc_lsize == 16) |
1da177e4 LT |
337 | r4k_blast_scache = blast_scache16; |
338 | else if (sc_lsize == 32) | |
339 | r4k_blast_scache = blast_scache32; | |
340 | else if (sc_lsize == 64) | |
341 | r4k_blast_scache = blast_scache64; | |
342 | else if (sc_lsize == 128) | |
343 | r4k_blast_scache = blast_scache128; | |
344 | } | |
345 | ||
1da177e4 LT |
346 | static inline void local_r4k___flush_cache_all(void * args) |
347 | { | |
2a21c730 FZ |
348 | #if defined(CONFIG_CPU_LOONGSON2) |
349 | r4k_blast_scache(); | |
350 | return; | |
351 | #endif | |
1da177e4 LT |
352 | r4k_blast_dcache(); |
353 | r4k_blast_icache(); | |
354 | ||
10cc3529 | 355 | switch (current_cpu_type()) { |
1da177e4 LT |
356 | case CPU_R4000SC: |
357 | case CPU_R4000MC: | |
358 | case CPU_R4400SC: | |
359 | case CPU_R4400MC: | |
360 | case CPU_R10000: | |
361 | case CPU_R12000: | |
44d921b2 | 362 | case CPU_R14000: |
1da177e4 LT |
363 | r4k_blast_scache(); |
364 | } | |
365 | } | |
366 | ||
367 | static void r4k___flush_cache_all(void) | |
368 | { | |
48a26e60 | 369 | r4k_on_each_cpu(local_r4k___flush_cache_all, NULL); |
1da177e4 LT |
370 | } |
371 | ||
a76ab5c1 RB |
372 | static inline int has_valid_asid(const struct mm_struct *mm) |
373 | { | |
374 | #if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC) | |
375 | int i; | |
376 | ||
377 | for_each_online_cpu(i) | |
378 | if (cpu_context(i, mm)) | |
379 | return 1; | |
380 | ||
381 | return 0; | |
382 | #else | |
383 | return cpu_context(smp_processor_id(), mm); | |
384 | #endif | |
385 | } | |
386 | ||
9c5a3d72 RB |
387 | static void r4k__flush_cache_vmap(void) |
388 | { | |
389 | r4k_blast_dcache(); | |
390 | } | |
391 | ||
392 | static void r4k__flush_cache_vunmap(void) | |
393 | { | |
394 | r4k_blast_dcache(); | |
395 | } | |
396 | ||
1da177e4 LT |
397 | static inline void local_r4k_flush_cache_range(void * args) |
398 | { | |
399 | struct vm_area_struct *vma = args; | |
2eaa7ec2 | 400 | int exec = vma->vm_flags & VM_EXEC; |
1da177e4 | 401 | |
a76ab5c1 | 402 | if (!(has_valid_asid(vma->vm_mm))) |
1da177e4 LT |
403 | return; |
404 | ||
0550d9d1 | 405 | r4k_blast_dcache(); |
2eaa7ec2 RB |
406 | if (exec) |
407 | r4k_blast_icache(); | |
1da177e4 LT |
408 | } |
409 | ||
410 | static void r4k_flush_cache_range(struct vm_area_struct *vma, | |
411 | unsigned long start, unsigned long end) | |
412 | { | |
2eaa7ec2 | 413 | int exec = vma->vm_flags & VM_EXEC; |
0550d9d1 | 414 | |
2eaa7ec2 | 415 | if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) |
48a26e60 | 416 | r4k_on_each_cpu(local_r4k_flush_cache_range, vma); |
1da177e4 LT |
417 | } |
418 | ||
419 | static inline void local_r4k_flush_cache_mm(void * args) | |
420 | { | |
421 | struct mm_struct *mm = args; | |
422 | ||
a76ab5c1 | 423 | if (!has_valid_asid(mm)) |
1da177e4 LT |
424 | return; |
425 | ||
1da177e4 LT |
426 | /* |
427 | * Kludge alert. For obscure reasons R4000SC and R4400SC go nuts if we | |
428 | * only flush the primary caches but R10000 and R12000 behave sane ... | |
617667ba RB |
429 | * R4000SC and R4400SC indexed S-cache ops also invalidate primary |
430 | * caches, so we can bail out early. | |
1da177e4 | 431 | */ |
10cc3529 RB |
432 | if (current_cpu_type() == CPU_R4000SC || |
433 | current_cpu_type() == CPU_R4000MC || | |
434 | current_cpu_type() == CPU_R4400SC || | |
435 | current_cpu_type() == CPU_R4400MC) { | |
1da177e4 | 436 | r4k_blast_scache(); |
617667ba RB |
437 | return; |
438 | } | |
439 | ||
440 | r4k_blast_dcache(); | |
1da177e4 LT |
441 | } |
442 | ||
443 | static void r4k_flush_cache_mm(struct mm_struct *mm) | |
444 | { | |
445 | if (!cpu_has_dc_aliases) | |
446 | return; | |
447 | ||
48a26e60 | 448 | r4k_on_each_cpu(local_r4k_flush_cache_mm, mm); |
1da177e4 LT |
449 | } |
450 | ||
451 | struct flush_cache_page_args { | |
452 | struct vm_area_struct *vma; | |
6ec25809 | 453 | unsigned long addr; |
de62893b | 454 | unsigned long pfn; |
1da177e4 LT |
455 | }; |
456 | ||
457 | static inline void local_r4k_flush_cache_page(void *args) | |
458 | { | |
459 | struct flush_cache_page_args *fcp_args = args; | |
460 | struct vm_area_struct *vma = fcp_args->vma; | |
6ec25809 | 461 | unsigned long addr = fcp_args->addr; |
db813fe5 | 462 | struct page *page = pfn_to_page(fcp_args->pfn); |
1da177e4 LT |
463 | int exec = vma->vm_flags & VM_EXEC; |
464 | struct mm_struct *mm = vma->vm_mm; | |
c9c5023d | 465 | int map_coherent = 0; |
1da177e4 | 466 | pgd_t *pgdp; |
c6e8b587 | 467 | pud_t *pudp; |
1da177e4 LT |
468 | pmd_t *pmdp; |
469 | pte_t *ptep; | |
db813fe5 | 470 | void *vaddr; |
1da177e4 | 471 | |
79acf83e RB |
472 | /* |
473 | * If ownes no valid ASID yet, cannot possibly have gotten | |
474 | * this page into the cache. | |
475 | */ | |
a76ab5c1 | 476 | if (!has_valid_asid(mm)) |
79acf83e RB |
477 | return; |
478 | ||
6ec25809 RB |
479 | addr &= PAGE_MASK; |
480 | pgdp = pgd_offset(mm, addr); | |
481 | pudp = pud_offset(pgdp, addr); | |
482 | pmdp = pmd_offset(pudp, addr); | |
483 | ptep = pte_offset(pmdp, addr); | |
1da177e4 LT |
484 | |
485 | /* | |
486 | * If the page isn't marked valid, the page cannot possibly be | |
487 | * in the cache. | |
488 | */ | |
526af35e | 489 | if (!(pte_present(*ptep))) |
1da177e4 LT |
490 | return; |
491 | ||
db813fe5 RB |
492 | if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID)) |
493 | vaddr = NULL; | |
494 | else { | |
495 | /* | |
496 | * Use kmap_coherent or kmap_atomic to do flushes for | |
497 | * another ASID than the current one. | |
498 | */ | |
c9c5023d RB |
499 | map_coherent = (cpu_has_dc_aliases && |
500 | page_mapped(page) && !Page_dcache_dirty(page)); | |
501 | if (map_coherent) | |
db813fe5 RB |
502 | vaddr = kmap_coherent(page, addr); |
503 | else | |
9c02048f | 504 | vaddr = kmap_atomic(page); |
db813fe5 | 505 | addr = (unsigned long)vaddr; |
1da177e4 LT |
506 | } |
507 | ||
1da177e4 | 508 | if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) { |
db813fe5 | 509 | r4k_blast_dcache_page(addr); |
39b8d525 RB |
510 | if (exec && !cpu_icache_snoops_remote_store) |
511 | r4k_blast_scache_page(addr); | |
1da177e4 LT |
512 | } |
513 | if (exec) { | |
db813fe5 | 514 | if (vaddr && cpu_has_vtag_icache && mm == current->active_mm) { |
1da177e4 LT |
515 | int cpu = smp_processor_id(); |
516 | ||
26a51b27 TS |
517 | if (cpu_context(cpu, mm) != 0) |
518 | drop_mmu_context(mm, cpu); | |
1da177e4 | 519 | } else |
db813fe5 RB |
520 | r4k_blast_icache_page(addr); |
521 | } | |
522 | ||
523 | if (vaddr) { | |
c9c5023d | 524 | if (map_coherent) |
db813fe5 RB |
525 | kunmap_coherent(); |
526 | else | |
9c02048f | 527 | kunmap_atomic(vaddr); |
1da177e4 LT |
528 | } |
529 | } | |
530 | ||
6ec25809 RB |
531 | static void r4k_flush_cache_page(struct vm_area_struct *vma, |
532 | unsigned long addr, unsigned long pfn) | |
1da177e4 LT |
533 | { |
534 | struct flush_cache_page_args args; | |
535 | ||
1da177e4 | 536 | args.vma = vma; |
6ec25809 | 537 | args.addr = addr; |
de62893b | 538 | args.pfn = pfn; |
1da177e4 | 539 | |
48a26e60 | 540 | r4k_on_each_cpu(local_r4k_flush_cache_page, &args); |
1da177e4 LT |
541 | } |
542 | ||
543 | static inline void local_r4k_flush_data_cache_page(void * addr) | |
544 | { | |
545 | r4k_blast_dcache_page((unsigned long) addr); | |
546 | } | |
547 | ||
548 | static void r4k_flush_data_cache_page(unsigned long addr) | |
549 | { | |
a754f708 RB |
550 | if (in_atomic()) |
551 | local_r4k_flush_data_cache_page((void *)addr); | |
552 | else | |
48a26e60 | 553 | r4k_on_each_cpu(local_r4k_flush_data_cache_page, (void *) addr); |
1da177e4 LT |
554 | } |
555 | ||
556 | struct flush_icache_range_args { | |
d4264f18 AN |
557 | unsigned long start; |
558 | unsigned long end; | |
1da177e4 LT |
559 | }; |
560 | ||
e0cee3ee | 561 | static inline void local_r4k_flush_icache_range(unsigned long start, unsigned long end) |
1da177e4 | 562 | { |
1da177e4 | 563 | if (!cpu_has_ic_fills_f_dc) { |
73f40352 | 564 | if (end - start >= dcache_size) { |
1da177e4 LT |
565 | r4k_blast_dcache(); |
566 | } else { | |
10a3dabd | 567 | R4600_HIT_CACHEOP_WAR_IMPL; |
41700e73 | 568 | protected_blast_dcache_range(start, end); |
1da177e4 | 569 | } |
1da177e4 LT |
570 | } |
571 | ||
572 | if (end - start > icache_size) | |
573 | r4k_blast_icache(); | |
41700e73 AN |
574 | else |
575 | protected_blast_icache_range(start, end); | |
1da177e4 LT |
576 | } |
577 | ||
e0cee3ee TB |
578 | static inline void local_r4k_flush_icache_range_ipi(void *args) |
579 | { | |
580 | struct flush_icache_range_args *fir_args = args; | |
581 | unsigned long start = fir_args->start; | |
582 | unsigned long end = fir_args->end; | |
583 | ||
584 | local_r4k_flush_icache_range(start, end); | |
585 | } | |
586 | ||
d4264f18 | 587 | static void r4k_flush_icache_range(unsigned long start, unsigned long end) |
1da177e4 LT |
588 | { |
589 | struct flush_icache_range_args args; | |
590 | ||
591 | args.start = start; | |
592 | args.end = end; | |
593 | ||
48a26e60 | 594 | r4k_on_each_cpu(local_r4k_flush_icache_range_ipi, &args); |
cc61c1fe | 595 | instruction_hazard(); |
1da177e4 LT |
596 | } |
597 | ||
1da177e4 LT |
598 | #ifdef CONFIG_DMA_NONCOHERENT |
599 | ||
600 | static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size) | |
601 | { | |
1da177e4 LT |
602 | /* Catch bad driver code */ |
603 | BUG_ON(size == 0); | |
604 | ||
ff522058 | 605 | preempt_disable(); |
fc5d2d27 | 606 | if (cpu_has_inclusive_pcaches) { |
41700e73 | 607 | if (size >= scache_size) |
1da177e4 | 608 | r4k_blast_scache(); |
41700e73 AN |
609 | else |
610 | blast_scache_range(addr, addr + size); | |
d0023c4a | 611 | __sync(); |
1da177e4 LT |
612 | return; |
613 | } | |
614 | ||
615 | /* | |
616 | * Either no secondary cache or the available caches don't have the | |
617 | * subset property so we have to flush the primary caches | |
618 | * explicitly | |
619 | */ | |
39b8d525 | 620 | if (cpu_has_safe_index_cacheops && size >= dcache_size) { |
1da177e4 LT |
621 | r4k_blast_dcache(); |
622 | } else { | |
1da177e4 | 623 | R4600_HIT_CACHEOP_WAR_IMPL; |
41700e73 | 624 | blast_dcache_range(addr, addr + size); |
1da177e4 | 625 | } |
ff522058 | 626 | preempt_enable(); |
1da177e4 LT |
627 | |
628 | bc_wback_inv(addr, size); | |
d0023c4a | 629 | __sync(); |
1da177e4 LT |
630 | } |
631 | ||
632 | static void r4k_dma_cache_inv(unsigned long addr, unsigned long size) | |
633 | { | |
1da177e4 LT |
634 | /* Catch bad driver code */ |
635 | BUG_ON(size == 0); | |
636 | ||
ff522058 | 637 | preempt_disable(); |
fc5d2d27 | 638 | if (cpu_has_inclusive_pcaches) { |
41700e73 | 639 | if (size >= scache_size) |
1da177e4 | 640 | r4k_blast_scache(); |
a8ca8b64 | 641 | else { |
a8ca8b64 RB |
642 | /* |
643 | * There is no clearly documented alignment requirement | |
644 | * for the cache instruction on MIPS processors and | |
645 | * some processors, among them the RM5200 and RM7000 | |
646 | * QED processors will throw an address error for cache | |
70342287 | 647 | * hit ops with insufficient alignment. Solved by |
a8ca8b64 RB |
648 | * aligning the address to cache line size. |
649 | */ | |
e9c33572 | 650 | blast_inv_scache_range(addr, addr + size); |
a8ca8b64 | 651 | } |
d0023c4a | 652 | __sync(); |
1da177e4 LT |
653 | return; |
654 | } | |
655 | ||
39b8d525 | 656 | if (cpu_has_safe_index_cacheops && size >= dcache_size) { |
1da177e4 LT |
657 | r4k_blast_dcache(); |
658 | } else { | |
1da177e4 | 659 | R4600_HIT_CACHEOP_WAR_IMPL; |
e9c33572 | 660 | blast_inv_dcache_range(addr, addr + size); |
1da177e4 | 661 | } |
ff522058 | 662 | preempt_enable(); |
1da177e4 LT |
663 | |
664 | bc_inv(addr, size); | |
d0023c4a | 665 | __sync(); |
1da177e4 LT |
666 | } |
667 | #endif /* CONFIG_DMA_NONCOHERENT */ | |
668 | ||
669 | /* | |
670 | * While we're protected against bad userland addresses we don't care | |
671 | * very much about what happens in that case. Usually a segmentation | |
672 | * fault will dump the process later on anyway ... | |
673 | */ | |
674 | static void local_r4k_flush_cache_sigtramp(void * arg) | |
675 | { | |
02fe2c9c TS |
676 | unsigned long ic_lsize = cpu_icache_line_size(); |
677 | unsigned long dc_lsize = cpu_dcache_line_size(); | |
678 | unsigned long sc_lsize = cpu_scache_line_size(); | |
1da177e4 LT |
679 | unsigned long addr = (unsigned long) arg; |
680 | ||
681 | R4600_HIT_CACHEOP_WAR_IMPL; | |
73f40352 CD |
682 | if (dc_lsize) |
683 | protected_writeback_dcache_line(addr & ~(dc_lsize - 1)); | |
4debe4f9 | 684 | if (!cpu_icache_snoops_remote_store && scache_size) |
1da177e4 | 685 | protected_writeback_scache_line(addr & ~(sc_lsize - 1)); |
73f40352 CD |
686 | if (ic_lsize) |
687 | protected_flush_icache_line(addr & ~(ic_lsize - 1)); | |
1da177e4 LT |
688 | if (MIPS4K_ICACHE_REFILL_WAR) { |
689 | __asm__ __volatile__ ( | |
690 | ".set push\n\t" | |
691 | ".set noat\n\t" | |
692 | ".set mips3\n\t" | |
875d43e7 | 693 | #ifdef CONFIG_32BIT |
1da177e4 LT |
694 | "la $at,1f\n\t" |
695 | #endif | |
875d43e7 | 696 | #ifdef CONFIG_64BIT |
1da177e4 LT |
697 | "dla $at,1f\n\t" |
698 | #endif | |
699 | "cache %0,($at)\n\t" | |
700 | "nop; nop; nop\n" | |
701 | "1:\n\t" | |
702 | ".set pop" | |
703 | : | |
704 | : "i" (Hit_Invalidate_I)); | |
705 | } | |
706 | if (MIPS_CACHE_SYNC_WAR) | |
707 | __asm__ __volatile__ ("sync"); | |
708 | } | |
709 | ||
710 | static void r4k_flush_cache_sigtramp(unsigned long addr) | |
711 | { | |
48a26e60 | 712 | r4k_on_each_cpu(local_r4k_flush_cache_sigtramp, (void *) addr); |
1da177e4 LT |
713 | } |
714 | ||
715 | static void r4k_flush_icache_all(void) | |
716 | { | |
717 | if (cpu_has_vtag_icache) | |
718 | r4k_blast_icache(); | |
719 | } | |
720 | ||
d9cdc901 RB |
721 | struct flush_kernel_vmap_range_args { |
722 | unsigned long vaddr; | |
723 | int size; | |
724 | }; | |
725 | ||
726 | static inline void local_r4k_flush_kernel_vmap_range(void *args) | |
727 | { | |
728 | struct flush_kernel_vmap_range_args *vmra = args; | |
729 | unsigned long vaddr = vmra->vaddr; | |
730 | int size = vmra->size; | |
731 | ||
732 | /* | |
733 | * Aliases only affect the primary caches so don't bother with | |
734 | * S-caches or T-caches. | |
735 | */ | |
736 | if (cpu_has_safe_index_cacheops && size >= dcache_size) | |
737 | r4k_blast_dcache(); | |
738 | else { | |
739 | R4600_HIT_CACHEOP_WAR_IMPL; | |
740 | blast_dcache_range(vaddr, vaddr + size); | |
741 | } | |
742 | } | |
743 | ||
744 | static void r4k_flush_kernel_vmap_range(unsigned long vaddr, int size) | |
745 | { | |
746 | struct flush_kernel_vmap_range_args args; | |
747 | ||
748 | args.vaddr = (unsigned long) vaddr; | |
749 | args.size = size; | |
750 | ||
751 | r4k_on_each_cpu(local_r4k_flush_kernel_vmap_range, &args); | |
752 | } | |
753 | ||
1da177e4 LT |
754 | static inline void rm7k_erratum31(void) |
755 | { | |
756 | const unsigned long ic_lsize = 32; | |
757 | unsigned long addr; | |
758 | ||
759 | /* RM7000 erratum #31. The icache is screwed at startup. */ | |
760 | write_c0_taglo(0); | |
761 | write_c0_taghi(0); | |
762 | ||
763 | for (addr = INDEX_BASE; addr <= INDEX_BASE + 4096; addr += ic_lsize) { | |
764 | __asm__ __volatile__ ( | |
d8748a3a | 765 | ".set push\n\t" |
1da177e4 LT |
766 | ".set noreorder\n\t" |
767 | ".set mips3\n\t" | |
768 | "cache\t%1, 0(%0)\n\t" | |
769 | "cache\t%1, 0x1000(%0)\n\t" | |
770 | "cache\t%1, 0x2000(%0)\n\t" | |
771 | "cache\t%1, 0x3000(%0)\n\t" | |
772 | "cache\t%2, 0(%0)\n\t" | |
773 | "cache\t%2, 0x1000(%0)\n\t" | |
774 | "cache\t%2, 0x2000(%0)\n\t" | |
775 | "cache\t%2, 0x3000(%0)\n\t" | |
776 | "cache\t%1, 0(%0)\n\t" | |
777 | "cache\t%1, 0x1000(%0)\n\t" | |
778 | "cache\t%1, 0x2000(%0)\n\t" | |
779 | "cache\t%1, 0x3000(%0)\n\t" | |
d8748a3a | 780 | ".set pop\n" |
1da177e4 LT |
781 | : |
782 | : "r" (addr), "i" (Index_Store_Tag_I), "i" (Fill)); | |
783 | } | |
784 | } | |
785 | ||
006a851b SH |
786 | static inline void alias_74k_erratum(struct cpuinfo_mips *c) |
787 | { | |
788 | /* | |
789 | * Early versions of the 74K do not update the cache tags on a | |
790 | * vtag miss/ptag hit which can occur in the case of KSEG0/KUSEG | |
791 | * aliases. In this case it is better to treat the cache as always | |
792 | * having aliases. | |
793 | */ | |
794 | if ((c->processor_id & 0xff) <= PRID_REV_ENCODE_332(2, 4, 0)) | |
795 | c->dcache.flags |= MIPS_CACHE_VTAG; | |
796 | if ((c->processor_id & 0xff) == PRID_REV_ENCODE_332(2, 4, 0)) | |
797 | write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND); | |
798 | if (((c->processor_id & 0xff00) == PRID_IMP_1074K) && | |
799 | ((c->processor_id & 0xff) <= PRID_REV_ENCODE_332(1, 1, 0))) { | |
800 | c->dcache.flags |= MIPS_CACHE_VTAG; | |
801 | write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND); | |
802 | } | |
803 | } | |
804 | ||
078a55fc | 805 | static char *way_string[] = { NULL, "direct mapped", "2-way", |
1da177e4 LT |
806 | "3-way", "4-way", "5-way", "6-way", "7-way", "8-way" |
807 | }; | |
808 | ||
078a55fc | 809 | static void probe_pcache(void) |
1da177e4 LT |
810 | { |
811 | struct cpuinfo_mips *c = ¤t_cpu_data; | |
812 | unsigned int config = read_c0_config(); | |
813 | unsigned int prid = read_c0_prid(); | |
814 | unsigned long config1; | |
815 | unsigned int lsize; | |
816 | ||
817 | switch (c->cputype) { | |
818 | case CPU_R4600: /* QED style two way caches? */ | |
819 | case CPU_R4700: | |
820 | case CPU_R5000: | |
821 | case CPU_NEVADA: | |
822 | icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); | |
823 | c->icache.linesz = 16 << ((config & CONF_IB) >> 5); | |
824 | c->icache.ways = 2; | |
3c68da79 | 825 | c->icache.waybit = __ffs(icache_size/2); |
1da177e4 LT |
826 | |
827 | dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); | |
828 | c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); | |
829 | c->dcache.ways = 2; | |
3c68da79 | 830 | c->dcache.waybit= __ffs(dcache_size/2); |
1da177e4 LT |
831 | |
832 | c->options |= MIPS_CPU_CACHE_CDEX_P; | |
833 | break; | |
834 | ||
835 | case CPU_R5432: | |
836 | case CPU_R5500: | |
837 | icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); | |
838 | c->icache.linesz = 16 << ((config & CONF_IB) >> 5); | |
839 | c->icache.ways = 2; | |
840 | c->icache.waybit= 0; | |
841 | ||
842 | dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); | |
843 | c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); | |
844 | c->dcache.ways = 2; | |
845 | c->dcache.waybit = 0; | |
846 | ||
5864810b | 847 | c->options |= MIPS_CPU_CACHE_CDEX_P | MIPS_CPU_PREFETCH; |
1da177e4 LT |
848 | break; |
849 | ||
850 | case CPU_TX49XX: | |
851 | icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); | |
852 | c->icache.linesz = 16 << ((config & CONF_IB) >> 5); | |
853 | c->icache.ways = 4; | |
854 | c->icache.waybit= 0; | |
855 | ||
856 | dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); | |
857 | c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); | |
858 | c->dcache.ways = 4; | |
859 | c->dcache.waybit = 0; | |
860 | ||
861 | c->options |= MIPS_CPU_CACHE_CDEX_P; | |
de862b48 | 862 | c->options |= MIPS_CPU_PREFETCH; |
1da177e4 LT |
863 | break; |
864 | ||
865 | case CPU_R4000PC: | |
866 | case CPU_R4000SC: | |
867 | case CPU_R4000MC: | |
868 | case CPU_R4400PC: | |
869 | case CPU_R4400SC: | |
870 | case CPU_R4400MC: | |
871 | case CPU_R4300: | |
872 | icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); | |
873 | c->icache.linesz = 16 << ((config & CONF_IB) >> 5); | |
874 | c->icache.ways = 1; | |
70342287 | 875 | c->icache.waybit = 0; /* doesn't matter */ |
1da177e4 LT |
876 | |
877 | dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); | |
878 | c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); | |
879 | c->dcache.ways = 1; | |
880 | c->dcache.waybit = 0; /* does not matter */ | |
881 | ||
882 | c->options |= MIPS_CPU_CACHE_CDEX_P; | |
883 | break; | |
884 | ||
885 | case CPU_R10000: | |
886 | case CPU_R12000: | |
44d921b2 | 887 | case CPU_R14000: |
1da177e4 LT |
888 | icache_size = 1 << (12 + ((config & R10K_CONF_IC) >> 29)); |
889 | c->icache.linesz = 64; | |
890 | c->icache.ways = 2; | |
891 | c->icache.waybit = 0; | |
892 | ||
893 | dcache_size = 1 << (12 + ((config & R10K_CONF_DC) >> 26)); | |
894 | c->dcache.linesz = 32; | |
895 | c->dcache.ways = 2; | |
896 | c->dcache.waybit = 0; | |
897 | ||
898 | c->options |= MIPS_CPU_PREFETCH; | |
899 | break; | |
900 | ||
901 | case CPU_VR4133: | |
2874fe55 | 902 | write_c0_config(config & ~VR41_CONF_P4K); |
1da177e4 LT |
903 | case CPU_VR4131: |
904 | /* Workaround for cache instruction bug of VR4131 */ | |
905 | if (c->processor_id == 0x0c80U || c->processor_id == 0x0c81U || | |
906 | c->processor_id == 0x0c82U) { | |
4e8ab361 YY |
907 | config |= 0x00400000U; |
908 | if (c->processor_id == 0x0c80U) | |
909 | config |= VR41_CONF_BP; | |
1da177e4 | 910 | write_c0_config(config); |
1058ecda YY |
911 | } else |
912 | c->options |= MIPS_CPU_CACHE_CDEX_P; | |
913 | ||
1da177e4 LT |
914 | icache_size = 1 << (10 + ((config & CONF_IC) >> 9)); |
915 | c->icache.linesz = 16 << ((config & CONF_IB) >> 5); | |
916 | c->icache.ways = 2; | |
3c68da79 | 917 | c->icache.waybit = __ffs(icache_size/2); |
1da177e4 LT |
918 | |
919 | dcache_size = 1 << (10 + ((config & CONF_DC) >> 6)); | |
920 | c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); | |
921 | c->dcache.ways = 2; | |
3c68da79 | 922 | c->dcache.waybit = __ffs(dcache_size/2); |
1da177e4 LT |
923 | break; |
924 | ||
925 | case CPU_VR41XX: | |
926 | case CPU_VR4111: | |
927 | case CPU_VR4121: | |
928 | case CPU_VR4122: | |
929 | case CPU_VR4181: | |
930 | case CPU_VR4181A: | |
931 | icache_size = 1 << (10 + ((config & CONF_IC) >> 9)); | |
932 | c->icache.linesz = 16 << ((config & CONF_IB) >> 5); | |
933 | c->icache.ways = 1; | |
70342287 | 934 | c->icache.waybit = 0; /* doesn't matter */ |
1da177e4 LT |
935 | |
936 | dcache_size = 1 << (10 + ((config & CONF_DC) >> 6)); | |
937 | c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); | |
938 | c->dcache.ways = 1; | |
939 | c->dcache.waybit = 0; /* does not matter */ | |
940 | ||
941 | c->options |= MIPS_CPU_CACHE_CDEX_P; | |
942 | break; | |
943 | ||
944 | case CPU_RM7000: | |
945 | rm7k_erratum31(); | |
946 | ||
1da177e4 LT |
947 | icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); |
948 | c->icache.linesz = 16 << ((config & CONF_IB) >> 5); | |
949 | c->icache.ways = 4; | |
3c68da79 | 950 | c->icache.waybit = __ffs(icache_size / c->icache.ways); |
1da177e4 LT |
951 | |
952 | dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); | |
953 | c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); | |
954 | c->dcache.ways = 4; | |
3c68da79 | 955 | c->dcache.waybit = __ffs(dcache_size / c->dcache.ways); |
1da177e4 | 956 | |
1da177e4 | 957 | c->options |= MIPS_CPU_CACHE_CDEX_P; |
1da177e4 LT |
958 | c->options |= MIPS_CPU_PREFETCH; |
959 | break; | |
960 | ||
2a21c730 FZ |
961 | case CPU_LOONGSON2: |
962 | icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); | |
963 | c->icache.linesz = 16 << ((config & CONF_IB) >> 5); | |
964 | if (prid & 0x3) | |
965 | c->icache.ways = 4; | |
966 | else | |
967 | c->icache.ways = 2; | |
968 | c->icache.waybit = 0; | |
969 | ||
970 | dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); | |
971 | c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); | |
972 | if (prid & 0x3) | |
973 | c->dcache.ways = 4; | |
974 | else | |
975 | c->dcache.ways = 2; | |
976 | c->dcache.waybit = 0; | |
977 | break; | |
978 | ||
1da177e4 LT |
979 | default: |
980 | if (!(config & MIPS_CONF_M)) | |
981 | panic("Don't know how to probe P-caches on this cpu."); | |
982 | ||
983 | /* | |
984 | * So we seem to be a MIPS32 or MIPS64 CPU | |
985 | * So let's probe the I-cache ... | |
986 | */ | |
987 | config1 = read_c0_config1(); | |
988 | ||
989 | if ((lsize = ((config1 >> 19) & 7))) | |
990 | c->icache.linesz = 2 << lsize; | |
991 | else | |
992 | c->icache.linesz = lsize; | |
dc34b05f | 993 | c->icache.sets = 32 << (((config1 >> 22) + 1) & 7); |
1da177e4 LT |
994 | c->icache.ways = 1 + ((config1 >> 16) & 7); |
995 | ||
996 | icache_size = c->icache.sets * | |
70342287 RB |
997 | c->icache.ways * |
998 | c->icache.linesz; | |
3c68da79 | 999 | c->icache.waybit = __ffs(icache_size/c->icache.ways); |
1da177e4 LT |
1000 | |
1001 | if (config & 0x8) /* VI bit */ | |
1002 | c->icache.flags |= MIPS_CACHE_VTAG; | |
1003 | ||
1004 | /* | |
1005 | * Now probe the MIPS32 / MIPS64 data cache. | |
1006 | */ | |
1007 | c->dcache.flags = 0; | |
1008 | ||
1009 | if ((lsize = ((config1 >> 10) & 7))) | |
1010 | c->dcache.linesz = 2 << lsize; | |
1011 | else | |
1012 | c->dcache.linesz= lsize; | |
dc34b05f | 1013 | c->dcache.sets = 32 << (((config1 >> 13) + 1) & 7); |
1da177e4 LT |
1014 | c->dcache.ways = 1 + ((config1 >> 7) & 7); |
1015 | ||
1016 | dcache_size = c->dcache.sets * | |
70342287 RB |
1017 | c->dcache.ways * |
1018 | c->dcache.linesz; | |
3c68da79 | 1019 | c->dcache.waybit = __ffs(dcache_size/c->dcache.ways); |
1da177e4 LT |
1020 | |
1021 | c->options |= MIPS_CPU_PREFETCH; | |
1022 | break; | |
1023 | } | |
1024 | ||
1025 | /* | |
1026 | * Processor configuration sanity check for the R4000SC erratum | |
70342287 | 1027 | * #5. With page sizes larger than 32kB there is no possibility |
1da177e4 LT |
1028 | * to get a VCE exception anymore so we don't care about this |
1029 | * misconfiguration. The case is rather theoretical anyway; | |
1030 | * presumably no vendor is shipping his hardware in the "bad" | |
1031 | * configuration. | |
1032 | */ | |
1033 | if ((prid & 0xff00) == PRID_IMP_R4000 && (prid & 0xff) < 0x40 && | |
1034 | !(config & CONF_SC) && c->icache.linesz != 16 && | |
1035 | PAGE_SIZE <= 0x8000) | |
1036 | panic("Improper R4000SC processor configuration detected"); | |
1037 | ||
1038 | /* compute a couple of other cache variables */ | |
1039 | c->icache.waysize = icache_size / c->icache.ways; | |
1040 | c->dcache.waysize = dcache_size / c->dcache.ways; | |
1041 | ||
73f40352 CD |
1042 | c->icache.sets = c->icache.linesz ? |
1043 | icache_size / (c->icache.linesz * c->icache.ways) : 0; | |
1044 | c->dcache.sets = c->dcache.linesz ? | |
1045 | dcache_size / (c->dcache.linesz * c->dcache.ways) : 0; | |
1da177e4 LT |
1046 | |
1047 | /* | |
1048 | * R10000 and R12000 P-caches are odd in a positive way. They're 32kB | |
1049 | * 2-way virtually indexed so normally would suffer from aliases. So | |
1050 | * normally they'd suffer from aliases but magic in the hardware deals | |
1051 | * with that for us so we don't need to take care ourselves. | |
1052 | */ | |
d1e344e5 | 1053 | switch (c->cputype) { |
a95970f3 | 1054 | case CPU_20KC: |
505403b6 | 1055 | case CPU_25KF: |
641e97f3 RB |
1056 | case CPU_SB1: |
1057 | case CPU_SB1A: | |
efa0f81c | 1058 | case CPU_XLR: |
de62893b | 1059 | c->dcache.flags |= MIPS_CACHE_PINDEX; |
641e97f3 RB |
1060 | break; |
1061 | ||
d1e344e5 RB |
1062 | case CPU_R10000: |
1063 | case CPU_R12000: | |
44d921b2 | 1064 | case CPU_R14000: |
d1e344e5 | 1065 | break; |
641e97f3 | 1066 | |
113c62d9 | 1067 | case CPU_M14KC: |
f8fa4811 | 1068 | case CPU_M14KEC: |
d1e344e5 | 1069 | case CPU_24K: |
98a41de9 | 1070 | case CPU_34K: |
2e78ae3f | 1071 | case CPU_74K: |
39b8d525 | 1072 | case CPU_1004K: |
006a851b SH |
1073 | if (c->cputype == CPU_74K) |
1074 | alias_74k_erratum(c); | |
beab375a RB |
1075 | if ((read_c0_config7() & (1 << 16))) { |
1076 | /* effectively physically indexed dcache, | |
1077 | thus no virtual aliases. */ | |
1078 | c->dcache.flags |= MIPS_CACHE_PINDEX; | |
1079 | break; | |
1080 | } | |
d1e344e5 | 1081 | default: |
beab375a RB |
1082 | if (c->dcache.waysize > PAGE_SIZE) |
1083 | c->dcache.flags |= MIPS_CACHE_ALIASES; | |
d1e344e5 | 1084 | } |
1da177e4 LT |
1085 | |
1086 | switch (c->cputype) { | |
1087 | case CPU_20KC: | |
1088 | /* | |
1089 | * Some older 20Kc chips doesn't have the 'VI' bit in | |
1090 | * the config register. | |
1091 | */ | |
1092 | c->icache.flags |= MIPS_CACHE_VTAG; | |
1093 | break; | |
1094 | ||
270717a8 | 1095 | case CPU_ALCHEMY: |
1da177e4 LT |
1096 | c->icache.flags |= MIPS_CACHE_IC_F_DC; |
1097 | break; | |
1098 | } | |
1099 | ||
70342287 | 1100 | #ifdef CONFIG_CPU_LOONGSON2 |
2a21c730 FZ |
1101 | /* |
1102 | * LOONGSON2 has 4 way icache, but when using indexed cache op, | |
1103 | * one op will act on all 4 ways | |
1104 | */ | |
1105 | c->icache.ways = 1; | |
1106 | #endif | |
1107 | ||
1da177e4 LT |
1108 | printk("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n", |
1109 | icache_size >> 10, | |
7fc7316a | 1110 | c->icache.flags & MIPS_CACHE_VTAG ? "VIVT" : "VIPT", |
1da177e4 LT |
1111 | way_string[c->icache.ways], c->icache.linesz); |
1112 | ||
64bfca5c RB |
1113 | printk("Primary data cache %ldkB, %s, %s, %s, linesize %d bytes\n", |
1114 | dcache_size >> 10, way_string[c->dcache.ways], | |
1115 | (c->dcache.flags & MIPS_CACHE_PINDEX) ? "PIPT" : "VIPT", | |
1116 | (c->dcache.flags & MIPS_CACHE_ALIASES) ? | |
1117 | "cache aliases" : "no aliases", | |
1118 | c->dcache.linesz); | |
1da177e4 LT |
1119 | } |
1120 | ||
1121 | /* | |
1122 | * If you even _breathe_ on this function, look at the gcc output and make sure | |
1123 | * it does not pop things on and off the stack for the cache sizing loop that | |
1124 | * executes in KSEG1 space or else you will crash and burn badly. You have | |
1125 | * been warned. | |
1126 | */ | |
078a55fc | 1127 | static int probe_scache(void) |
1da177e4 | 1128 | { |
1da177e4 LT |
1129 | unsigned long flags, addr, begin, end, pow2; |
1130 | unsigned int config = read_c0_config(); | |
1131 | struct cpuinfo_mips *c = ¤t_cpu_data; | |
1da177e4 LT |
1132 | |
1133 | if (config & CONF_SC) | |
1134 | return 0; | |
1135 | ||
e001e528 | 1136 | begin = (unsigned long) &_stext; |
1da177e4 LT |
1137 | begin &= ~((4 * 1024 * 1024) - 1); |
1138 | end = begin + (4 * 1024 * 1024); | |
1139 | ||
1140 | /* | |
1141 | * This is such a bitch, you'd think they would make it easy to do | |
1142 | * this. Away you daemons of stupidity! | |
1143 | */ | |
1144 | local_irq_save(flags); | |
1145 | ||
1146 | /* Fill each size-multiple cache line with a valid tag. */ | |
1147 | pow2 = (64 * 1024); | |
1148 | for (addr = begin; addr < end; addr = (begin + pow2)) { | |
1149 | unsigned long *p = (unsigned long *) addr; | |
1150 | __asm__ __volatile__("nop" : : "r" (*p)); /* whee... */ | |
1151 | pow2 <<= 1; | |
1152 | } | |
1153 | ||
1154 | /* Load first line with zero (therefore invalid) tag. */ | |
1155 | write_c0_taglo(0); | |
1156 | write_c0_taghi(0); | |
1157 | __asm__ __volatile__("nop; nop; nop; nop;"); /* avoid the hazard */ | |
1158 | cache_op(Index_Store_Tag_I, begin); | |
1159 | cache_op(Index_Store_Tag_D, begin); | |
1160 | cache_op(Index_Store_Tag_SD, begin); | |
1161 | ||
1162 | /* Now search for the wrap around point. */ | |
1163 | pow2 = (128 * 1024); | |
1da177e4 LT |
1164 | for (addr = begin + (128 * 1024); addr < end; addr = begin + pow2) { |
1165 | cache_op(Index_Load_Tag_SD, addr); | |
1166 | __asm__ __volatile__("nop; nop; nop; nop;"); /* hazard... */ | |
1167 | if (!read_c0_taglo()) | |
1168 | break; | |
1169 | pow2 <<= 1; | |
1170 | } | |
1171 | local_irq_restore(flags); | |
1172 | addr -= begin; | |
1173 | ||
1174 | scache_size = addr; | |
1175 | c->scache.linesz = 16 << ((config & R4K_CONF_SB) >> 22); | |
1176 | c->scache.ways = 1; | |
1177 | c->dcache.waybit = 0; /* does not matter */ | |
1178 | ||
1179 | return 1; | |
1180 | } | |
1181 | ||
2a21c730 FZ |
1182 | #if defined(CONFIG_CPU_LOONGSON2) |
1183 | static void __init loongson2_sc_init(void) | |
1184 | { | |
1185 | struct cpuinfo_mips *c = ¤t_cpu_data; | |
1186 | ||
1187 | scache_size = 512*1024; | |
1188 | c->scache.linesz = 32; | |
1189 | c->scache.ways = 4; | |
1190 | c->scache.waybit = 0; | |
1191 | c->scache.waysize = scache_size / (c->scache.ways); | |
1192 | c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways); | |
1193 | pr_info("Unified secondary cache %ldkB %s, linesize %d bytes.\n", | |
1194 | scache_size >> 10, way_string[c->scache.ways], c->scache.linesz); | |
1195 | ||
1196 | c->options |= MIPS_CPU_INCLUSIVE_CACHES; | |
1197 | } | |
1198 | #endif | |
1199 | ||
1da177e4 LT |
1200 | extern int r5k_sc_init(void); |
1201 | extern int rm7k_sc_init(void); | |
9318c51a | 1202 | extern int mips_sc_init(void); |
1da177e4 | 1203 | |
078a55fc | 1204 | static void setup_scache(void) |
1da177e4 LT |
1205 | { |
1206 | struct cpuinfo_mips *c = ¤t_cpu_data; | |
1207 | unsigned int config = read_c0_config(); | |
1da177e4 LT |
1208 | int sc_present = 0; |
1209 | ||
1210 | /* | |
1211 | * Do the probing thing on R4000SC and R4400SC processors. Other | |
1212 | * processors don't have a S-cache that would be relevant to the | |
603e82ed | 1213 | * Linux memory management. |
1da177e4 LT |
1214 | */ |
1215 | switch (c->cputype) { | |
1216 | case CPU_R4000SC: | |
1217 | case CPU_R4000MC: | |
1218 | case CPU_R4400SC: | |
1219 | case CPU_R4400MC: | |
ba5187db | 1220 | sc_present = run_uncached(probe_scache); |
1da177e4 LT |
1221 | if (sc_present) |
1222 | c->options |= MIPS_CPU_CACHE_CDEX_S; | |
1223 | break; | |
1224 | ||
1225 | case CPU_R10000: | |
1226 | case CPU_R12000: | |
44d921b2 | 1227 | case CPU_R14000: |
1da177e4 LT |
1228 | scache_size = 0x80000 << ((config & R10K_CONF_SS) >> 16); |
1229 | c->scache.linesz = 64 << ((config >> 13) & 1); | |
1230 | c->scache.ways = 2; | |
1231 | c->scache.waybit= 0; | |
1232 | sc_present = 1; | |
1233 | break; | |
1234 | ||
1235 | case CPU_R5000: | |
1236 | case CPU_NEVADA: | |
1237 | #ifdef CONFIG_R5000_CPU_SCACHE | |
1238 | r5k_sc_init(); | |
1239 | #endif | |
70342287 | 1240 | return; |
1da177e4 LT |
1241 | |
1242 | case CPU_RM7000: | |
1da177e4 LT |
1243 | #ifdef CONFIG_RM7000_CPU_SCACHE |
1244 | rm7k_sc_init(); | |
1245 | #endif | |
1246 | return; | |
1247 | ||
2a21c730 FZ |
1248 | #if defined(CONFIG_CPU_LOONGSON2) |
1249 | case CPU_LOONGSON2: | |
1250 | loongson2_sc_init(); | |
1251 | return; | |
1252 | #endif | |
a3d4fb2d J |
1253 | case CPU_XLP: |
1254 | /* don't need to worry about L2, fully coherent */ | |
1255 | return; | |
2a21c730 | 1256 | |
1da177e4 | 1257 | default: |
adb37892 DCZ |
1258 | if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 | |
1259 | MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)) { | |
9318c51a CD |
1260 | #ifdef CONFIG_MIPS_CPU_SCACHE |
1261 | if (mips_sc_init ()) { | |
1262 | scache_size = c->scache.ways * c->scache.sets * c->scache.linesz; | |
1263 | printk("MIPS secondary cache %ldkB, %s, linesize %d bytes.\n", | |
1264 | scache_size >> 10, | |
1265 | way_string[c->scache.ways], c->scache.linesz); | |
1266 | } | |
1267 | #else | |
1268 | if (!(c->scache.flags & MIPS_CACHE_NOT_PRESENT)) | |
1269 | panic("Dunno how to handle MIPS32 / MIPS64 second level cache"); | |
1270 | #endif | |
1271 | return; | |
1272 | } | |
1da177e4 LT |
1273 | sc_present = 0; |
1274 | } | |
1275 | ||
1276 | if (!sc_present) | |
1277 | return; | |
1278 | ||
1da177e4 LT |
1279 | /* compute a couple of other cache variables */ |
1280 | c->scache.waysize = scache_size / c->scache.ways; | |
1281 | ||
1282 | c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways); | |
1283 | ||
1284 | printk("Unified secondary cache %ldkB %s, linesize %d bytes.\n", | |
1285 | scache_size >> 10, way_string[c->scache.ways], c->scache.linesz); | |
1286 | ||
fc5d2d27 | 1287 | c->options |= MIPS_CPU_INCLUSIVE_CACHES; |
1da177e4 LT |
1288 | } |
1289 | ||
9370b351 SS |
1290 | void au1x00_fixup_config_od(void) |
1291 | { | |
1292 | /* | |
1293 | * c0_config.od (bit 19) was write only (and read as 0) | |
1294 | * on the early revisions of Alchemy SOCs. It disables the bus | |
1295 | * transaction overlapping and needs to be set to fix various errata. | |
1296 | */ | |
1297 | switch (read_c0_prid()) { | |
1298 | case 0x00030100: /* Au1000 DA */ | |
1299 | case 0x00030201: /* Au1000 HA */ | |
1300 | case 0x00030202: /* Au1000 HB */ | |
1301 | case 0x01030200: /* Au1500 AB */ | |
1302 | /* | |
1303 | * Au1100 errata actually keeps silence about this bit, so we set it | |
1304 | * just in case for those revisions that require it to be set according | |
270717a8 | 1305 | * to the (now gone) cpu table. |
9370b351 SS |
1306 | */ |
1307 | case 0x02030200: /* Au1100 AB */ | |
1308 | case 0x02030201: /* Au1100 BA */ | |
1309 | case 0x02030202: /* Au1100 BC */ | |
1310 | set_c0_config(1 << 19); | |
1311 | break; | |
1312 | } | |
1313 | } | |
1314 | ||
89052bd7 RB |
1315 | /* CP0 hazard avoidance. */ |
1316 | #define NXP_BARRIER() \ | |
1317 | __asm__ __volatile__( \ | |
1318 | ".set noreorder\n\t" \ | |
1319 | "nop; nop; nop; nop; nop; nop;\n\t" \ | |
1320 | ".set reorder\n\t") | |
1321 | ||
1322 | static void nxp_pr4450_fixup_config(void) | |
1323 | { | |
1324 | unsigned long config0; | |
1325 | ||
1326 | config0 = read_c0_config(); | |
1327 | ||
1328 | /* clear all three cache coherency fields */ | |
1329 | config0 &= ~(0x7 | (7 << 25) | (7 << 28)); | |
1330 | config0 |= (((_page_cachable_default >> _CACHE_SHIFT) << 0) | | |
1331 | ((_page_cachable_default >> _CACHE_SHIFT) << 25) | | |
1332 | ((_page_cachable_default >> _CACHE_SHIFT) << 28)); | |
1333 | write_c0_config(config0); | |
1334 | NXP_BARRIER(); | |
1335 | } | |
1336 | ||
078a55fc | 1337 | static int cca = -1; |
35133692 CD |
1338 | |
1339 | static int __init cca_setup(char *str) | |
1340 | { | |
1341 | get_option(&str, &cca); | |
1342 | ||
b5b64f2b | 1343 | return 0; |
35133692 CD |
1344 | } |
1345 | ||
b5b64f2b | 1346 | early_param("cca", cca_setup); |
35133692 | 1347 | |
078a55fc | 1348 | static void coherency_setup(void) |
1da177e4 | 1349 | { |
35133692 CD |
1350 | if (cca < 0 || cca > 7) |
1351 | cca = read_c0_config() & CONF_CM_CMASK; | |
1352 | _page_cachable_default = cca << _CACHE_SHIFT; | |
1353 | ||
1354 | pr_debug("Using cache attribute %d\n", cca); | |
1355 | change_c0_config(CONF_CM_CMASK, cca); | |
1da177e4 LT |
1356 | |
1357 | /* | |
1358 | * c0_status.cu=0 specifies that updates by the sc instruction use | |
1359 | * the coherency mode specified by the TLB; 1 means cachable | |
1360 | * coherent update on write will be used. Not all processors have | |
1361 | * this bit and; some wire it to zero, others like Toshiba had the | |
1362 | * silly idea of putting something else there ... | |
1363 | */ | |
10cc3529 | 1364 | switch (current_cpu_type()) { |
1da177e4 LT |
1365 | case CPU_R4000PC: |
1366 | case CPU_R4000SC: | |
1367 | case CPU_R4000MC: | |
1368 | case CPU_R4400PC: | |
1369 | case CPU_R4400SC: | |
1370 | case CPU_R4400MC: | |
1371 | clear_c0_config(CONF_CU); | |
1372 | break; | |
9370b351 | 1373 | /* |
df586d59 | 1374 | * We need to catch the early Alchemy SOCs with |
270717a8 ML |
1375 | * the write-only co_config.od bit and set it back to one on: |
1376 | * Au1000 rev DA, HA, HB; Au1100 AB, BA, BC, Au1500 AB | |
9370b351 | 1377 | */ |
270717a8 | 1378 | case CPU_ALCHEMY: |
9370b351 SS |
1379 | au1x00_fixup_config_od(); |
1380 | break; | |
89052bd7 RB |
1381 | |
1382 | case PRID_IMP_PR4450: | |
1383 | nxp_pr4450_fixup_config(); | |
1384 | break; | |
1da177e4 LT |
1385 | } |
1386 | } | |
1387 | ||
078a55fc | 1388 | static void r4k_cache_error_setup(void) |
1da177e4 | 1389 | { |
641e97f3 RB |
1390 | extern char __weak except_vec2_generic; |
1391 | extern char __weak except_vec2_sb1; | |
1da177e4 LT |
1392 | struct cpuinfo_mips *c = ¤t_cpu_data; |
1393 | ||
641e97f3 RB |
1394 | switch (c->cputype) { |
1395 | case CPU_SB1: | |
1396 | case CPU_SB1A: | |
1397 | set_uncached_handler(0x100, &except_vec2_sb1, 0x80); | |
1398 | break; | |
1399 | ||
1400 | default: | |
1401 | set_uncached_handler(0x100, &except_vec2_generic, 0x80); | |
1402 | break; | |
1403 | } | |
9cd9669b DD |
1404 | } |
1405 | ||
078a55fc | 1406 | void r4k_cache_init(void) |
9cd9669b DD |
1407 | { |
1408 | extern void build_clear_page(void); | |
1409 | extern void build_copy_page(void); | |
1410 | struct cpuinfo_mips *c = ¤t_cpu_data; | |
1da177e4 LT |
1411 | |
1412 | probe_pcache(); | |
1413 | setup_scache(); | |
1414 | ||
1da177e4 LT |
1415 | r4k_blast_dcache_page_setup(); |
1416 | r4k_blast_dcache_page_indexed_setup(); | |
1417 | r4k_blast_dcache_setup(); | |
1418 | r4k_blast_icache_page_setup(); | |
1419 | r4k_blast_icache_page_indexed_setup(); | |
1420 | r4k_blast_icache_setup(); | |
1421 | r4k_blast_scache_page_setup(); | |
1422 | r4k_blast_scache_page_indexed_setup(); | |
1423 | r4k_blast_scache_setup(); | |
1424 | ||
1425 | /* | |
1426 | * Some MIPS32 and MIPS64 processors have physically indexed caches. | |
1427 | * This code supports virtually indexed processors and will be | |
1428 | * unnecessarily inefficient on physically indexed processors. | |
1429 | */ | |
73f40352 CD |
1430 | if (c->dcache.linesz) |
1431 | shm_align_mask = max_t( unsigned long, | |
1432 | c->dcache.sets * c->dcache.linesz - 1, | |
1433 | PAGE_SIZE - 1); | |
1434 | else | |
1435 | shm_align_mask = PAGE_SIZE-1; | |
9c5a3d72 RB |
1436 | |
1437 | __flush_cache_vmap = r4k__flush_cache_vmap; | |
1438 | __flush_cache_vunmap = r4k__flush_cache_vunmap; | |
1439 | ||
db813fe5 | 1440 | flush_cache_all = cache_noop; |
1da177e4 LT |
1441 | __flush_cache_all = r4k___flush_cache_all; |
1442 | flush_cache_mm = r4k_flush_cache_mm; | |
1443 | flush_cache_page = r4k_flush_cache_page; | |
1da177e4 LT |
1444 | flush_cache_range = r4k_flush_cache_range; |
1445 | ||
d9cdc901 RB |
1446 | __flush_kernel_vmap_range = r4k_flush_kernel_vmap_range; |
1447 | ||
1da177e4 LT |
1448 | flush_cache_sigtramp = r4k_flush_cache_sigtramp; |
1449 | flush_icache_all = r4k_flush_icache_all; | |
7e3bfc7c | 1450 | local_flush_data_cache_page = local_r4k_flush_data_cache_page; |
1da177e4 LT |
1451 | flush_data_cache_page = r4k_flush_data_cache_page; |
1452 | flush_icache_range = r4k_flush_icache_range; | |
e0cee3ee | 1453 | local_flush_icache_range = local_r4k_flush_icache_range; |
1da177e4 | 1454 | |
39b8d525 RB |
1455 | #if defined(CONFIG_DMA_NONCOHERENT) |
1456 | if (coherentio) { | |
1457 | _dma_cache_wback_inv = (void *)cache_noop; | |
1458 | _dma_cache_wback = (void *)cache_noop; | |
1459 | _dma_cache_inv = (void *)cache_noop; | |
1460 | } else { | |
1461 | _dma_cache_wback_inv = r4k_dma_cache_wback_inv; | |
1462 | _dma_cache_wback = r4k_dma_cache_wback_inv; | |
1463 | _dma_cache_inv = r4k_dma_cache_inv; | |
1464 | } | |
1da177e4 LT |
1465 | #endif |
1466 | ||
1da177e4 LT |
1467 | build_clear_page(); |
1468 | build_copy_page(); | |
b6d92b4a SH |
1469 | |
1470 | /* | |
1471 | * We want to run CMP kernels on core with and without coherent | |
1472 | * caches. Therefore, do not use CONFIG_MIPS_CMP to decide whether | |
1473 | * or not to flush caches. | |
1474 | */ | |
1d40cfcd | 1475 | local_r4k___flush_cache_all(NULL); |
b6d92b4a | 1476 | |
1d40cfcd | 1477 | coherency_setup(); |
9cd9669b | 1478 | board_cache_error_setup = r4k_cache_error_setup; |
1da177e4 | 1479 | } |