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1da177e4 LT |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * Copyright (C) 1994 - 2003 by Ralf Baechle | |
7 | */ | |
8 | #include <linux/config.h> | |
9 | #include <linux/init.h> | |
10 | #include <linux/kernel.h> | |
11 | #include <linux/module.h> | |
12 | #include <linux/sched.h> | |
13 | #include <linux/mm.h> | |
14 | ||
15 | #include <asm/cacheflush.h> | |
16 | #include <asm/processor.h> | |
17 | #include <asm/cpu.h> | |
18 | #include <asm/cpu-features.h> | |
19 | ||
20 | /* Cache operations. */ | |
21 | void (*flush_cache_all)(void); | |
22 | void (*__flush_cache_all)(void); | |
23 | void (*flush_cache_mm)(struct mm_struct *mm); | |
24 | void (*flush_cache_range)(struct vm_area_struct *vma, unsigned long start, | |
25 | unsigned long end); | |
53de0d47 RB |
26 | void (*flush_cache_page)(struct vm_area_struct *vma, unsigned long page, |
27 | unsigned long pfn); | |
fe00f943 RB |
28 | void (*flush_icache_range)(unsigned long __user start, |
29 | unsigned long __user end); | |
1da177e4 LT |
30 | void (*flush_icache_page)(struct vm_area_struct *vma, struct page *page); |
31 | ||
32 | /* MIPS specific cache operations */ | |
33 | void (*flush_cache_sigtramp)(unsigned long addr); | |
34 | void (*flush_data_cache_page)(unsigned long addr); | |
35 | void (*flush_icache_all)(void); | |
36 | ||
9ff77c46 RB |
37 | EXPORT_SYMBOL(flush_data_cache_page); |
38 | ||
1da177e4 LT |
39 | #ifdef CONFIG_DMA_NONCOHERENT |
40 | ||
41 | /* DMA cache operations. */ | |
42 | void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size); | |
43 | void (*_dma_cache_wback)(unsigned long start, unsigned long size); | |
44 | void (*_dma_cache_inv)(unsigned long start, unsigned long size); | |
45 | ||
46 | EXPORT_SYMBOL(_dma_cache_wback_inv); | |
47 | EXPORT_SYMBOL(_dma_cache_wback); | |
48 | EXPORT_SYMBOL(_dma_cache_inv); | |
49 | ||
50 | #endif /* CONFIG_DMA_NONCOHERENT */ | |
51 | ||
52 | /* | |
53 | * We could optimize the case where the cache argument is not BCACHE but | |
54 | * that seems very atypical use ... | |
55 | */ | |
fe00f943 RB |
56 | asmlinkage int sys_cacheflush(unsigned long __user addr, |
57 | unsigned long bytes, unsigned int cache) | |
1da177e4 | 58 | { |
fe00f943 | 59 | if (!access_ok(VERIFY_WRITE, (void __user *) addr, bytes)) |
1da177e4 LT |
60 | return -EFAULT; |
61 | ||
62 | flush_icache_range(addr, addr + bytes); | |
63 | ||
64 | return 0; | |
65 | } | |
66 | ||
67 | void __flush_dcache_page(struct page *page) | |
68 | { | |
69 | struct address_space *mapping = page_mapping(page); | |
70 | unsigned long addr; | |
71 | ||
72 | if (mapping && !mapping_mapped(mapping)) { | |
73 | SetPageDcacheDirty(page); | |
74 | return; | |
75 | } | |
76 | ||
77 | /* | |
78 | * We could delay the flush for the !page_mapping case too. But that | |
79 | * case is for exec env/arg pages and those are %99 certainly going to | |
80 | * get faulted into the tlb (and thus flushed) anyways. | |
81 | */ | |
82 | addr = (unsigned long) page_address(page); | |
83 | flush_data_cache_page(addr); | |
84 | } | |
85 | ||
86 | EXPORT_SYMBOL(__flush_dcache_page); | |
87 | ||
88 | void __update_cache(struct vm_area_struct *vma, unsigned long address, | |
89 | pte_t pte) | |
90 | { | |
91 | struct page *page; | |
92 | unsigned long pfn, addr; | |
93 | ||
94 | pfn = pte_pfn(pte); | |
95 | if (pfn_valid(pfn) && (page = pfn_to_page(pfn), page_mapping(page)) && | |
96 | Page_dcache_dirty(page)) { | |
97 | if (pages_do_alias((unsigned long)page_address(page), | |
98 | address & PAGE_MASK)) { | |
99 | addr = (unsigned long) page_address(page); | |
100 | flush_data_cache_page(addr); | |
101 | } | |
102 | ||
103 | ClearPageDcacheDirty(page); | |
104 | } | |
105 | } | |
106 | ||
02cf2119 RB |
107 | #define __weak __attribute__((weak)) |
108 | ||
109 | static char cache_panic[] __initdata = "Yeee, unsupported cache architecture."; | |
1da177e4 LT |
110 | |
111 | void __init cpu_cache_init(void) | |
112 | { | |
02cf2119 RB |
113 | if (cpu_has_3k_cache) { |
114 | extern void __weak r3k_cache_init(void); | |
115 | ||
116 | r3k_cache_init(); | |
117 | return; | |
118 | } | |
119 | if (cpu_has_6k_cache) { | |
120 | extern void __weak r6k_cache_init(void); | |
121 | ||
122 | r6k_cache_init(); | |
123 | return; | |
1da177e4 | 124 | } |
02cf2119 RB |
125 | if (cpu_has_4k_cache) { |
126 | extern void __weak r4k_cache_init(void); | |
127 | ||
128 | r4k_cache_init(); | |
129 | return; | |
130 | } | |
131 | if (cpu_has_8k_cache) { | |
132 | extern void __weak r8k_cache_init(void); | |
133 | ||
134 | r8k_cache_init(); | |
135 | return; | |
136 | } | |
137 | if (cpu_has_tx39_cache) { | |
138 | extern void __weak tx39_cache_init(void); | |
139 | ||
140 | tx39_cache_init(); | |
141 | return; | |
142 | } | |
143 | if (cpu_has_sb1_cache) { | |
144 | extern void __weak sb1_cache_init(void); | |
145 | ||
146 | sb1_cache_init(); | |
147 | return; | |
148 | } | |
149 | ||
150 | panic(cache_panic); | |
1da177e4 | 151 | } |