[deliverable/linux.git] / arch / mips / mm / sc-mips.c

/*
 * Copyright (C) 2006 Chris Dearman (chris@mips.com),
 */
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/mm.h>

#include <asm/cpu-type.h>
#include <asm/mipsregs.h>
#include <asm/bcache.h>
#include <asm/cacheops.h>
#include <asm/page.h>
#include <asm/pgtable.h>
#include <asm/mmu_context.h>
#include <asm/r4kcache.h>

/*
 * MIPS32/MIPS64 L2 cache handling
 */

/*
 * Writeback and invalidate the secondary cache before DMA.
 */
static void mips_sc_wback_inv(unsigned long addr, unsigned long size)
{
	blast_scache_range(addr, addr + size);
}

/*
 * Invalidate the secondary cache before DMA.
 */
static void mips_sc_inv(unsigned long addr, unsigned long size)
{
	unsigned long lsize = cpu_scache_line_size();
	unsigned long almask = ~(lsize - 1);

	cache_op(Hit_Writeback_Inv_SD, addr & almask);
	cache_op(Hit_Writeback_Inv_SD, (addr + size - 1) & almask);
	blast_inv_scache_range(addr, addr + size);
}

static void mips_sc_enable(void)
{
	/* L2 cache is permanently enabled */
}

static void mips_sc_disable(void)
{
	/* L2 cache is permanently enabled */
}

static struct bcache_ops mips_sc_ops = {
	.bc_enable = mips_sc_enable,
	.bc_disable = mips_sc_disable,
	.bc_wback_inv = mips_sc_wback_inv,
	.bc_inv = mips_sc_inv
};

/*
 * Check if the L2 cache controller is activated on a particular platform.
 * MTI's L2 controller and the L2 cache controller of Broadcom's BMIPS
 * cores both use c0_config2's bit 12 as "L2 Bypass" bit, that is the
 * cache being disabled.  However there is no guarantee for this to be
 * true on all platforms.  In an act of stupidity the spec defined bits
 * 12..15 as implementation defined so below function will eventually have
 * to be replaced by a platform specific probe.
 */
static inline int mips_sc_is_activated(struct cpuinfo_mips *c)
{
	unsigned int config2 = read_c0_config2();
	unsigned int tmp;

	/* Check the bypass bit (L2B) */
	switch (current_cpu_type()) {
	case CPU_34K:
	case CPU_74K:
	case CPU_1004K:
	case CPU_1074K:
	case CPU_INTERAPTIV:
	case CPU_PROAPTIV:
	case CPU_P5600:
	case CPU_BMIPS5000:
		if (config2 & (1 << 12))
			return 0;
	}

	tmp = (config2 >> 4) & 0x0f;
	if (0 < tmp && tmp <= 7)
		c->scache.linesz = 2 << tmp;
	else
		return 0;
	return 1;
}

static inline int __init mips_sc_probe(void)
{
	struct cpuinfo_mips *c = &current_cpu_data;
	unsigned int config1, config2;
	unsigned int tmp;

	/* Mark as not present until probe completed */
	c->scache.flags |= MIPS_CACHE_NOT_PRESENT;

	/* Ignore anything but MIPSxx processors */
	if (!(c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |
			      MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)))
		return 0;

	/* Does this MIPS32/MIPS64 CPU have a config2 register? */
	config1 = read_c0_config1();
	if (!(config1 & MIPS_CONF_M))
		return 0;

	config2 = read_c0_config2();

	if (!mips_sc_is_activated(c))
		return 0;

	tmp = (config2 >> 8) & 0x0f;
	if (0 <= tmp && tmp <= 7)
		c->scache.sets = 64 << tmp;
	else
		return 0;

	tmp = (config2 >> 0) & 0x0f;
	if (0 <= tmp && tmp <= 7)
		c->scache.ways = tmp + 1;
	else
		return 0;

	c->scache.waysize = c->scache.sets * c->scache.linesz;
	c->scache.waybit = __ffs(c->scache.waysize);

	c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;

	return 1;
}

int mips_sc_init(void)
{
	int found = mips_sc_probe();
	if (found) {
		mips_sc_enable();
		bcops = &mips_sc_ops;
	}
	return found;
}
Commit	Line	Data
9318c51a CD	1	/*
	2	* Copyright (C) 2006 Chris Dearman (chris@mips.com),
	3	*/
	4	#include <linux/init.h>
	5	#include <linux/kernel.h>
	6	#include <linux/sched.h>
	7	#include <linux/mm.h>
	8
69f24d17	9	#include <asm/cpu-type.h>
9318c51a CD	10	#include <asm/mipsregs.h>
	11	#include <asm/bcache.h>
	12	#include <asm/cacheops.h>
	13	#include <asm/page.h>
	14	#include <asm/pgtable.h>
9318c51a CD	15	#include <asm/mmu_context.h>
	16	#include <asm/r4kcache.h>
	17
	18	/*
	19	* MIPS32/MIPS64 L2 cache handling
	20	*/
	21
	22	/*
	23	* Writeback and invalidate the secondary cache before DMA.
	24	*/
	25	static void mips_sc_wback_inv(unsigned long addr, unsigned long size)
	26	{
a2c2bc4b	27	blast_scache_range(addr, addr + size);
9318c51a CD	28	}
	29
	30	/*
	31	* Invalidate the secondary cache before DMA.
	32	*/
	33	static void mips_sc_inv(unsigned long addr, unsigned long size)
	34	{
96983ffe KC	35	unsigned long lsize = cpu_scache_line_size();
	36	unsigned long almask = ~(lsize - 1);
	37
	38	cache_op(Hit_Writeback_Inv_SD, addr & almask);
	39	cache_op(Hit_Writeback_Inv_SD, (addr + size - 1) & almask);
a2c2bc4b	40	blast_inv_scache_range(addr, addr + size);
9318c51a CD	41	}
	42
	43	static void mips_sc_enable(void)
	44	{
	45	/* L2 cache is permanently enabled */
	46	}
	47
	48	static void mips_sc_disable(void)
	49	{
	50	/* L2 cache is permanently enabled */
	51	}
	52
	53	static struct bcache_ops mips_sc_ops = {
	54	.bc_enable = mips_sc_enable,
	55	.bc_disable = mips_sc_disable,
	56	.bc_wback_inv = mips_sc_wback_inv,
	57	.bc_inv = mips_sc_inv
	58	};
	59
ea31a6b2 KC	60	/*
	61	* Check if the L2 cache controller is activated on a particular platform.
	62	* MTI's L2 controller and the L2 cache controller of Broadcom's BMIPS
	63	* cores both use c0_config2's bit 12 as "L2 Bypass" bit, that is the
	64	* cache being disabled. However there is no guarantee for this to be
	65	* true on all platforms. In an act of stupidity the spec defined bits
	66	* 12..15 as implementation defined so below function will eventually have
	67	* to be replaced by a platform specific probe.
	68	*/
	69	static inline int mips_sc_is_activated(struct cpuinfo_mips *c)
	70	{
081d835f KC	71	unsigned int config2 = read_c0_config2();
	72	unsigned int tmp;
	73
ea31a6b2	74	/* Check the bypass bit (L2B) */
69f24d17	75	switch (current_cpu_type()) {
ea31a6b2 KC	76	case CPU_34K:
	77	case CPU_74K:
	78	case CPU_1004K:
442e14a2	79	case CPU_1074K:
26ab96df	80	case CPU_INTERAPTIV:
708ac4b8	81	case CPU_PROAPTIV:
aced4cbd	82	case CPU_P5600:
ea31a6b2 KC	83	case CPU_BMIPS5000:
	84	if (config2 & (1 << 12))
	85	return 0;
	86	}
	87
	88	tmp = (config2 >> 4) & 0x0f;
	89	if (0 < tmp && tmp <= 7)
	90	c->scache.linesz = 2 << tmp;
	91	else
	92	return 0;
081d835f	93	return 1;
ea31a6b2 KC	94	}
ea31a6b2 KC	95
9318c51a CD	96	static inline int __init mips_sc_probe(void)
	97	{
	98	struct cpuinfo_mips *c = &current_cpu_data;
	99	unsigned int config1, config2;
	100	unsigned int tmp;
	101
	102	/* Mark as not present until probe completed */
	103	c->scache.flags \|= MIPS_CACHE_NOT_PRESENT;
	104
	105	/* Ignore anything but MIPSxx processors */
adb37892 DCZ	106	if (!(c->isa_level & (MIPS_CPU_ISA_M32R1 \| MIPS_CPU_ISA_M32R2 \|
adb37892 DCZ	107	MIPS_CPU_ISA_M64R1 \| MIPS_CPU_ISA_M64R2)))
9318c51a CD	108	return 0;
	109
	110	/* Does this MIPS32/MIPS64 CPU have a config2 register? */
	111	config1 = read_c0_config1();
	112	if (!(config1 & MIPS_CONF_M))
	113	return 0;
	114
	115	config2 = read_c0_config2();
ea31a6b2 KC	116
ea31a6b2 KC	117	if (!mips_sc_is_activated(c))
9318c51a CD	118	return 0;
	119
	120	tmp = (config2 >> 8) & 0x0f;
	121	if (0 <= tmp && tmp <= 7)
	122	c->scache.sets = 64 << tmp;
	123	else
	124	return 0;
	125
	126	tmp = (config2 >> 0) & 0x0f;
	127	if (0 <= tmp && tmp <= 7)
	128	c->scache.ways = tmp + 1;
	129	else
	130	return 0;
	131
	132	c->scache.waysize = c->scache.sets * c->scache.linesz;
a2c2bc4b	133	c->scache.waybit = __ffs(c->scache.waysize);
9318c51a CD	134
	135	c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
	136
	137	return 1;
	138	}
	139
078a55fc	140	int mips_sc_init(void)
9318c51a	141	{
49a89efb	142	int found = mips_sc_probe();
9318c51a CD	143	if (found) {
	144	mips_sc_enable();
	145	bcops = &mips_sc_ops;
	146	}
	147	return found;
	148	}