Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * Synthesize TLB refill handlers at runtime. | |
7 | * | |
70342287 RB |
8 | * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer |
9 | * Copyright (C) 2005, 2007, 2008, 2009 Maciej W. Rozycki | |
41c594ab | 10 | * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org) |
fd062c84 | 11 | * Copyright (C) 2008, 2009 Cavium Networks, Inc. |
113c62d9 | 12 | * Copyright (C) 2011 MIPS Technologies, Inc. |
41c594ab RB |
13 | * |
14 | * ... and the days got worse and worse and now you see | |
15 | * I've gone completly out of my mind. | |
16 | * | |
17 | * They're coming to take me a away haha | |
18 | * they're coming to take me a away hoho hihi haha | |
19 | * to the funny farm where code is beautiful all the time ... | |
20 | * | |
21 | * (Condolences to Napoleon XIV) | |
1da177e4 LT |
22 | */ |
23 | ||
95affdda | 24 | #include <linux/bug.h> |
1da177e4 LT |
25 | #include <linux/kernel.h> |
26 | #include <linux/types.h> | |
631330f5 | 27 | #include <linux/smp.h> |
1da177e4 LT |
28 | #include <linux/string.h> |
29 | #include <linux/init.h> | |
3d8bfdd0 | 30 | #include <linux/cache.h> |
1da177e4 | 31 | |
3d8bfdd0 | 32 | #include <asm/cacheflush.h> |
69f24d17 | 33 | #include <asm/cpu-type.h> |
3d8bfdd0 | 34 | #include <asm/pgtable.h> |
1da177e4 | 35 | #include <asm/war.h> |
3482d713 | 36 | #include <asm/uasm.h> |
b81947c6 | 37 | #include <asm/setup.h> |
e30ec452 | 38 | |
1ec56329 DD |
39 | /* |
40 | * TLB load/store/modify handlers. | |
41 | * | |
42 | * Only the fastpath gets synthesized at runtime, the slowpath for | |
43 | * do_page_fault remains normal asm. | |
44 | */ | |
45 | extern void tlb_do_page_fault_0(void); | |
46 | extern void tlb_do_page_fault_1(void); | |
47 | ||
bf28607f DD |
48 | struct work_registers { |
49 | int r1; | |
50 | int r2; | |
51 | int r3; | |
52 | }; | |
53 | ||
54 | struct tlb_reg_save { | |
55 | unsigned long a; | |
56 | unsigned long b; | |
57 | } ____cacheline_aligned_in_smp; | |
58 | ||
59 | static struct tlb_reg_save handler_reg_save[NR_CPUS]; | |
1ec56329 | 60 | |
aeffdbba | 61 | static inline int r45k_bvahwbug(void) |
1da177e4 LT |
62 | { |
63 | /* XXX: We should probe for the presence of this bug, but we don't. */ | |
64 | return 0; | |
65 | } | |
66 | ||
aeffdbba | 67 | static inline int r4k_250MHZhwbug(void) |
1da177e4 LT |
68 | { |
69 | /* XXX: We should probe for the presence of this bug, but we don't. */ | |
70 | return 0; | |
71 | } | |
72 | ||
aeffdbba | 73 | static inline int __maybe_unused bcm1250_m3_war(void) |
1da177e4 LT |
74 | { |
75 | return BCM1250_M3_WAR; | |
76 | } | |
77 | ||
aeffdbba | 78 | static inline int __maybe_unused r10000_llsc_war(void) |
1da177e4 LT |
79 | { |
80 | return R10000_LLSC_WAR; | |
81 | } | |
82 | ||
cc33ae43 DD |
83 | static int use_bbit_insns(void) |
84 | { | |
85 | switch (current_cpu_type()) { | |
86 | case CPU_CAVIUM_OCTEON: | |
87 | case CPU_CAVIUM_OCTEON_PLUS: | |
88 | case CPU_CAVIUM_OCTEON2: | |
4723b20a | 89 | case CPU_CAVIUM_OCTEON3: |
cc33ae43 DD |
90 | return 1; |
91 | default: | |
92 | return 0; | |
93 | } | |
94 | } | |
95 | ||
2c8c53e2 DD |
96 | static int use_lwx_insns(void) |
97 | { | |
98 | switch (current_cpu_type()) { | |
99 | case CPU_CAVIUM_OCTEON2: | |
4723b20a | 100 | case CPU_CAVIUM_OCTEON3: |
2c8c53e2 DD |
101 | return 1; |
102 | default: | |
103 | return 0; | |
104 | } | |
105 | } | |
106 | #if defined(CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE) && \ | |
107 | CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0 | |
108 | static bool scratchpad_available(void) | |
109 | { | |
110 | return true; | |
111 | } | |
112 | static int scratchpad_offset(int i) | |
113 | { | |
114 | /* | |
115 | * CVMSEG starts at address -32768 and extends for | |
116 | * CAVIUM_OCTEON_CVMSEG_SIZE 128 byte cache lines. | |
117 | */ | |
118 | i += 1; /* Kernel use starts at the top and works down. */ | |
119 | return CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128 - (8 * i) - 32768; | |
120 | } | |
121 | #else | |
122 | static bool scratchpad_available(void) | |
123 | { | |
124 | return false; | |
125 | } | |
126 | static int scratchpad_offset(int i) | |
127 | { | |
128 | BUG(); | |
e1c87d2a DD |
129 | /* Really unreachable, but evidently some GCC want this. */ |
130 | return 0; | |
2c8c53e2 DD |
131 | } |
132 | #endif | |
8df5beac MR |
133 | /* |
134 | * Found by experiment: At least some revisions of the 4kc throw under | |
135 | * some circumstances a machine check exception, triggered by invalid | |
136 | * values in the index register. Delaying the tlbp instruction until | |
137 | * after the next branch, plus adding an additional nop in front of | |
138 | * tlbwi/tlbwr avoids the invalid index register values. Nobody knows | |
139 | * why; it's not an issue caused by the core RTL. | |
140 | * | |
141 | */ | |
078a55fc | 142 | static int m4kc_tlbp_war(void) |
8df5beac MR |
143 | { |
144 | return (current_cpu_data.processor_id & 0xffff00) == | |
145 | (PRID_COMP_MIPS | PRID_IMP_4KC); | |
146 | } | |
147 | ||
e30ec452 | 148 | /* Handle labels (which must be positive integers). */ |
1da177e4 | 149 | enum label_id { |
e30ec452 | 150 | label_second_part = 1, |
1da177e4 LT |
151 | label_leave, |
152 | label_vmalloc, | |
153 | label_vmalloc_done, | |
02a54177 RB |
154 | label_tlbw_hazard_0, |
155 | label_split = label_tlbw_hazard_0 + 8, | |
6dd9344c DD |
156 | label_tlbl_goaround1, |
157 | label_tlbl_goaround2, | |
1da177e4 LT |
158 | label_nopage_tlbl, |
159 | label_nopage_tlbs, | |
160 | label_nopage_tlbm, | |
161 | label_smp_pgtable_change, | |
162 | label_r3000_write_probe_fail, | |
1ec56329 | 163 | label_large_segbits_fault, |
aa1762f4 | 164 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
fd062c84 DD |
165 | label_tlb_huge_update, |
166 | #endif | |
1da177e4 LT |
167 | }; |
168 | ||
e30ec452 TS |
169 | UASM_L_LA(_second_part) |
170 | UASM_L_LA(_leave) | |
e30ec452 TS |
171 | UASM_L_LA(_vmalloc) |
172 | UASM_L_LA(_vmalloc_done) | |
02a54177 | 173 | /* _tlbw_hazard_x is handled differently. */ |
e30ec452 | 174 | UASM_L_LA(_split) |
6dd9344c DD |
175 | UASM_L_LA(_tlbl_goaround1) |
176 | UASM_L_LA(_tlbl_goaround2) | |
e30ec452 TS |
177 | UASM_L_LA(_nopage_tlbl) |
178 | UASM_L_LA(_nopage_tlbs) | |
179 | UASM_L_LA(_nopage_tlbm) | |
180 | UASM_L_LA(_smp_pgtable_change) | |
181 | UASM_L_LA(_r3000_write_probe_fail) | |
1ec56329 | 182 | UASM_L_LA(_large_segbits_fault) |
aa1762f4 | 183 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
fd062c84 DD |
184 | UASM_L_LA(_tlb_huge_update) |
185 | #endif | |
656be92f | 186 | |
078a55fc | 187 | static int hazard_instance; |
02a54177 | 188 | |
078a55fc | 189 | static void uasm_bgezl_hazard(u32 **p, struct uasm_reloc **r, int instance) |
02a54177 RB |
190 | { |
191 | switch (instance) { | |
192 | case 0 ... 7: | |
193 | uasm_il_bgezl(p, r, 0, label_tlbw_hazard_0 + instance); | |
194 | return; | |
195 | default: | |
196 | BUG(); | |
197 | } | |
198 | } | |
199 | ||
078a55fc | 200 | static void uasm_bgezl_label(struct uasm_label **l, u32 **p, int instance) |
02a54177 RB |
201 | { |
202 | switch (instance) { | |
203 | case 0 ... 7: | |
204 | uasm_build_label(l, *p, label_tlbw_hazard_0 + instance); | |
205 | break; | |
206 | default: | |
207 | BUG(); | |
208 | } | |
209 | } | |
210 | ||
92b1e6a6 | 211 | /* |
a2c763e0 RB |
212 | * pgtable bits are assigned dynamically depending on processor feature |
213 | * and statically based on kernel configuration. This spits out the actual | |
70342287 | 214 | * values the kernel is using. Required to make sense from disassembled |
a2c763e0 | 215 | * TLB exception handlers. |
92b1e6a6 | 216 | */ |
a2c763e0 RB |
217 | static void output_pgtable_bits_defines(void) |
218 | { | |
219 | #define pr_define(fmt, ...) \ | |
220 | pr_debug("#define " fmt, ##__VA_ARGS__) | |
221 | ||
222 | pr_debug("#include <asm/asm.h>\n"); | |
223 | pr_debug("#include <asm/regdef.h>\n"); | |
224 | pr_debug("\n"); | |
225 | ||
226 | pr_define("_PAGE_PRESENT_SHIFT %d\n", _PAGE_PRESENT_SHIFT); | |
227 | pr_define("_PAGE_READ_SHIFT %d\n", _PAGE_READ_SHIFT); | |
228 | pr_define("_PAGE_WRITE_SHIFT %d\n", _PAGE_WRITE_SHIFT); | |
229 | pr_define("_PAGE_ACCESSED_SHIFT %d\n", _PAGE_ACCESSED_SHIFT); | |
230 | pr_define("_PAGE_MODIFIED_SHIFT %d\n", _PAGE_MODIFIED_SHIFT); | |
970d032f | 231 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
a2c763e0 | 232 | pr_define("_PAGE_HUGE_SHIFT %d\n", _PAGE_HUGE_SHIFT); |
970d032f | 233 | pr_define("_PAGE_SPLITTING_SHIFT %d\n", _PAGE_SPLITTING_SHIFT); |
a2c763e0 RB |
234 | #endif |
235 | if (cpu_has_rixi) { | |
236 | #ifdef _PAGE_NO_EXEC_SHIFT | |
237 | pr_define("_PAGE_NO_EXEC_SHIFT %d\n", _PAGE_NO_EXEC_SHIFT); | |
238 | #endif | |
239 | #ifdef _PAGE_NO_READ_SHIFT | |
240 | pr_define("_PAGE_NO_READ_SHIFT %d\n", _PAGE_NO_READ_SHIFT); | |
241 | #endif | |
242 | } | |
243 | pr_define("_PAGE_GLOBAL_SHIFT %d\n", _PAGE_GLOBAL_SHIFT); | |
244 | pr_define("_PAGE_VALID_SHIFT %d\n", _PAGE_VALID_SHIFT); | |
245 | pr_define("_PAGE_DIRTY_SHIFT %d\n", _PAGE_DIRTY_SHIFT); | |
246 | pr_define("_PFN_SHIFT %d\n", _PFN_SHIFT); | |
247 | pr_debug("\n"); | |
248 | } | |
249 | ||
250 | static inline void dump_handler(const char *symbol, const u32 *handler, int count) | |
92b1e6a6 FBH |
251 | { |
252 | int i; | |
253 | ||
a2c763e0 RB |
254 | pr_debug("LEAF(%s)\n", symbol); |
255 | ||
92b1e6a6 FBH |
256 | pr_debug("\t.set push\n"); |
257 | pr_debug("\t.set noreorder\n"); | |
258 | ||
259 | for (i = 0; i < count; i++) | |
a2c763e0 | 260 | pr_debug("\t.word\t0x%08x\t\t# %p\n", handler[i], &handler[i]); |
92b1e6a6 | 261 | |
a2c763e0 RB |
262 | pr_debug("\t.set\tpop\n"); |
263 | ||
264 | pr_debug("\tEND(%s)\n", symbol); | |
92b1e6a6 FBH |
265 | } |
266 | ||
1da177e4 LT |
267 | /* The only general purpose registers allowed in TLB handlers. */ |
268 | #define K0 26 | |
269 | #define K1 27 | |
270 | ||
271 | /* Some CP0 registers */ | |
41c594ab RB |
272 | #define C0_INDEX 0, 0 |
273 | #define C0_ENTRYLO0 2, 0 | |
274 | #define C0_TCBIND 2, 2 | |
275 | #define C0_ENTRYLO1 3, 0 | |
276 | #define C0_CONTEXT 4, 0 | |
fd062c84 | 277 | #define C0_PAGEMASK 5, 0 |
41c594ab RB |
278 | #define C0_BADVADDR 8, 0 |
279 | #define C0_ENTRYHI 10, 0 | |
280 | #define C0_EPC 14, 0 | |
281 | #define C0_XCONTEXT 20, 0 | |
1da177e4 | 282 | |
875d43e7 | 283 | #ifdef CONFIG_64BIT |
e30ec452 | 284 | # define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_XCONTEXT) |
1da177e4 | 285 | #else |
e30ec452 | 286 | # define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_CONTEXT) |
1da177e4 LT |
287 | #endif |
288 | ||
289 | /* The worst case length of the handler is around 18 instructions for | |
290 | * R3000-style TLBs and up to 63 instructions for R4000-style TLBs. | |
291 | * Maximum space available is 32 instructions for R3000 and 64 | |
292 | * instructions for R4000. | |
293 | * | |
294 | * We deliberately chose a buffer size of 128, so we won't scribble | |
295 | * over anything important on overflow before we panic. | |
296 | */ | |
078a55fc | 297 | static u32 tlb_handler[128]; |
1da177e4 LT |
298 | |
299 | /* simply assume worst case size for labels and relocs */ | |
078a55fc PG |
300 | static struct uasm_label labels[128]; |
301 | static struct uasm_reloc relocs[128]; | |
1da177e4 | 302 | |
078a55fc | 303 | static int check_for_high_segbits; |
3d8bfdd0 | 304 | |
078a55fc | 305 | static unsigned int kscratch_used_mask; |
3d8bfdd0 | 306 | |
7777b939 J |
307 | static inline int __maybe_unused c0_kscratch(void) |
308 | { | |
309 | switch (current_cpu_type()) { | |
310 | case CPU_XLP: | |
311 | case CPU_XLR: | |
312 | return 22; | |
313 | default: | |
314 | return 31; | |
315 | } | |
316 | } | |
317 | ||
078a55fc | 318 | static int allocate_kscratch(void) |
3d8bfdd0 DD |
319 | { |
320 | int r; | |
321 | unsigned int a = cpu_data[0].kscratch_mask & ~kscratch_used_mask; | |
322 | ||
323 | r = ffs(a); | |
324 | ||
325 | if (r == 0) | |
326 | return -1; | |
327 | ||
328 | r--; /* make it zero based */ | |
329 | ||
330 | kscratch_used_mask |= (1 << r); | |
331 | ||
332 | return r; | |
333 | } | |
334 | ||
078a55fc PG |
335 | static int scratch_reg; |
336 | static int pgd_reg; | |
2c8c53e2 DD |
337 | enum vmalloc64_mode {not_refill, refill_scratch, refill_noscratch}; |
338 | ||
078a55fc | 339 | static struct work_registers build_get_work_registers(u32 **p) |
bf28607f DD |
340 | { |
341 | struct work_registers r; | |
342 | ||
0e6ecc1a | 343 | if (scratch_reg >= 0) { |
bf28607f | 344 | /* Save in CPU local C0_KScratch? */ |
7777b939 | 345 | UASM_i_MTC0(p, 1, c0_kscratch(), scratch_reg); |
bf28607f DD |
346 | r.r1 = K0; |
347 | r.r2 = K1; | |
348 | r.r3 = 1; | |
349 | return r; | |
350 | } | |
351 | ||
352 | if (num_possible_cpus() > 1) { | |
bf28607f | 353 | /* Get smp_processor_id */ |
c2377a42 J |
354 | UASM_i_CPUID_MFC0(p, K0, SMP_CPUID_REG); |
355 | UASM_i_SRL_SAFE(p, K0, K0, SMP_CPUID_REGSHIFT); | |
bf28607f DD |
356 | |
357 | /* handler_reg_save index in K0 */ | |
358 | UASM_i_SLL(p, K0, K0, ilog2(sizeof(struct tlb_reg_save))); | |
359 | ||
360 | UASM_i_LA(p, K1, (long)&handler_reg_save); | |
361 | UASM_i_ADDU(p, K0, K0, K1); | |
362 | } else { | |
363 | UASM_i_LA(p, K0, (long)&handler_reg_save); | |
364 | } | |
365 | /* K0 now points to save area, save $1 and $2 */ | |
366 | UASM_i_SW(p, 1, offsetof(struct tlb_reg_save, a), K0); | |
367 | UASM_i_SW(p, 2, offsetof(struct tlb_reg_save, b), K0); | |
368 | ||
369 | r.r1 = K1; | |
370 | r.r2 = 1; | |
371 | r.r3 = 2; | |
372 | return r; | |
373 | } | |
374 | ||
078a55fc | 375 | static void build_restore_work_registers(u32 **p) |
bf28607f | 376 | { |
0e6ecc1a | 377 | if (scratch_reg >= 0) { |
7777b939 | 378 | UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg); |
bf28607f DD |
379 | return; |
380 | } | |
381 | /* K0 already points to save area, restore $1 and $2 */ | |
382 | UASM_i_LW(p, 1, offsetof(struct tlb_reg_save, a), K0); | |
383 | UASM_i_LW(p, 2, offsetof(struct tlb_reg_save, b), K0); | |
384 | } | |
385 | ||
2c8c53e2 | 386 | #ifndef CONFIG_MIPS_PGD_C0_CONTEXT |
3d8bfdd0 | 387 | |
82622284 DD |
388 | /* |
389 | * CONFIG_MIPS_PGD_C0_CONTEXT implies 64 bit and lack of pgd_current, | |
390 | * we cannot do r3000 under these circumstances. | |
3d8bfdd0 DD |
391 | * |
392 | * Declare pgd_current here instead of including mmu_context.h to avoid type | |
393 | * conflicts for tlbmiss_handler_setup_pgd | |
82622284 | 394 | */ |
3d8bfdd0 | 395 | extern unsigned long pgd_current[]; |
82622284 | 396 | |
1da177e4 LT |
397 | /* |
398 | * The R3000 TLB handler is simple. | |
399 | */ | |
078a55fc | 400 | static void build_r3000_tlb_refill_handler(void) |
1da177e4 LT |
401 | { |
402 | long pgdc = (long)pgd_current; | |
403 | u32 *p; | |
404 | ||
405 | memset(tlb_handler, 0, sizeof(tlb_handler)); | |
406 | p = tlb_handler; | |
407 | ||
e30ec452 TS |
408 | uasm_i_mfc0(&p, K0, C0_BADVADDR); |
409 | uasm_i_lui(&p, K1, uasm_rel_hi(pgdc)); /* cp0 delay */ | |
410 | uasm_i_lw(&p, K1, uasm_rel_lo(pgdc), K1); | |
411 | uasm_i_srl(&p, K0, K0, 22); /* load delay */ | |
412 | uasm_i_sll(&p, K0, K0, 2); | |
413 | uasm_i_addu(&p, K1, K1, K0); | |
414 | uasm_i_mfc0(&p, K0, C0_CONTEXT); | |
415 | uasm_i_lw(&p, K1, 0, K1); /* cp0 delay */ | |
416 | uasm_i_andi(&p, K0, K0, 0xffc); /* load delay */ | |
417 | uasm_i_addu(&p, K1, K1, K0); | |
418 | uasm_i_lw(&p, K0, 0, K1); | |
419 | uasm_i_nop(&p); /* load delay */ | |
420 | uasm_i_mtc0(&p, K0, C0_ENTRYLO0); | |
421 | uasm_i_mfc0(&p, K1, C0_EPC); /* cp0 delay */ | |
422 | uasm_i_tlbwr(&p); /* cp0 delay */ | |
423 | uasm_i_jr(&p, K1); | |
424 | uasm_i_rfe(&p); /* branch delay */ | |
1da177e4 LT |
425 | |
426 | if (p > tlb_handler + 32) | |
427 | panic("TLB refill handler space exceeded"); | |
428 | ||
e30ec452 TS |
429 | pr_debug("Wrote TLB refill handler (%u instructions).\n", |
430 | (unsigned int)(p - tlb_handler)); | |
1da177e4 | 431 | |
91b05e67 | 432 | memcpy((void *)ebase, tlb_handler, 0x80); |
92b1e6a6 | 433 | |
a2c763e0 | 434 | dump_handler("r3000_tlb_refill", (u32 *)ebase, 32); |
1da177e4 | 435 | } |
82622284 | 436 | #endif /* CONFIG_MIPS_PGD_C0_CONTEXT */ |
1da177e4 LT |
437 | |
438 | /* | |
439 | * The R4000 TLB handler is much more complicated. We have two | |
440 | * consecutive handler areas with 32 instructions space each. | |
441 | * Since they aren't used at the same time, we can overflow in the | |
442 | * other one.To keep things simple, we first assume linear space, | |
443 | * then we relocate it to the final handler layout as needed. | |
444 | */ | |
078a55fc | 445 | static u32 final_handler[64]; |
1da177e4 LT |
446 | |
447 | /* | |
448 | * Hazards | |
449 | * | |
450 | * From the IDT errata for the QED RM5230 (Nevada), processor revision 1.0: | |
451 | * 2. A timing hazard exists for the TLBP instruction. | |
452 | * | |
70342287 RB |
453 | * stalling_instruction |
454 | * TLBP | |
1da177e4 LT |
455 | * |
456 | * The JTLB is being read for the TLBP throughout the stall generated by the | |
457 | * previous instruction. This is not really correct as the stalling instruction | |
458 | * can modify the address used to access the JTLB. The failure symptom is that | |
459 | * the TLBP instruction will use an address created for the stalling instruction | |
460 | * and not the address held in C0_ENHI and thus report the wrong results. | |
461 | * | |
462 | * The software work-around is to not allow the instruction preceding the TLBP | |
463 | * to stall - make it an NOP or some other instruction guaranteed not to stall. | |
464 | * | |
70342287 | 465 | * Errata 2 will not be fixed. This errata is also on the R5000. |
1da177e4 LT |
466 | * |
467 | * As if we MIPS hackers wouldn't know how to nop pipelines happy ... | |
468 | */ | |
078a55fc | 469 | static void __maybe_unused build_tlb_probe_entry(u32 **p) |
1da177e4 | 470 | { |
10cc3529 | 471 | switch (current_cpu_type()) { |
326e2e1a | 472 | /* Found by experiment: R4600 v2.0/R4700 needs this, too. */ |
f5b4d956 | 473 | case CPU_R4600: |
326e2e1a | 474 | case CPU_R4700: |
1da177e4 | 475 | case CPU_R5000: |
1da177e4 | 476 | case CPU_NEVADA: |
e30ec452 TS |
477 | uasm_i_nop(p); |
478 | uasm_i_tlbp(p); | |
1da177e4 LT |
479 | break; |
480 | ||
481 | default: | |
e30ec452 | 482 | uasm_i_tlbp(p); |
1da177e4 LT |
483 | break; |
484 | } | |
485 | } | |
486 | ||
487 | /* | |
488 | * Write random or indexed TLB entry, and care about the hazards from | |
25985edc | 489 | * the preceding mtc0 and for the following eret. |
1da177e4 LT |
490 | */ |
491 | enum tlb_write_entry { tlb_random, tlb_indexed }; | |
492 | ||
078a55fc PG |
493 | static void build_tlb_write_entry(u32 **p, struct uasm_label **l, |
494 | struct uasm_reloc **r, | |
495 | enum tlb_write_entry wmode) | |
1da177e4 LT |
496 | { |
497 | void(*tlbw)(u32 **) = NULL; | |
498 | ||
499 | switch (wmode) { | |
e30ec452 TS |
500 | case tlb_random: tlbw = uasm_i_tlbwr; break; |
501 | case tlb_indexed: tlbw = uasm_i_tlbwi; break; | |
1da177e4 LT |
502 | } |
503 | ||
161548bf | 504 | if (cpu_has_mips_r2) { |
625c0a21 SH |
505 | /* |
506 | * The architecture spec says an ehb is required here, | |
507 | * but a number of cores do not have the hazard and | |
508 | * using an ehb causes an expensive pipeline stall. | |
509 | */ | |
510 | switch (current_cpu_type()) { | |
511 | case CPU_M14KC: | |
512 | case CPU_74K: | |
513 | break; | |
514 | ||
515 | default: | |
41f0e4d0 | 516 | uasm_i_ehb(p); |
625c0a21 SH |
517 | break; |
518 | } | |
161548bf RB |
519 | tlbw(p); |
520 | return; | |
521 | } | |
522 | ||
10cc3529 | 523 | switch (current_cpu_type()) { |
1da177e4 LT |
524 | case CPU_R4000PC: |
525 | case CPU_R4000SC: | |
526 | case CPU_R4000MC: | |
527 | case CPU_R4400PC: | |
528 | case CPU_R4400SC: | |
529 | case CPU_R4400MC: | |
530 | /* | |
531 | * This branch uses up a mtc0 hazard nop slot and saves | |
532 | * two nops after the tlbw instruction. | |
533 | */ | |
02a54177 | 534 | uasm_bgezl_hazard(p, r, hazard_instance); |
1da177e4 | 535 | tlbw(p); |
02a54177 RB |
536 | uasm_bgezl_label(l, p, hazard_instance); |
537 | hazard_instance++; | |
e30ec452 | 538 | uasm_i_nop(p); |
1da177e4 LT |
539 | break; |
540 | ||
541 | case CPU_R4600: | |
542 | case CPU_R4700: | |
e30ec452 | 543 | uasm_i_nop(p); |
2c93e12c | 544 | tlbw(p); |
e30ec452 | 545 | uasm_i_nop(p); |
2c93e12c MR |
546 | break; |
547 | ||
359187d6 | 548 | case CPU_R5000: |
359187d6 RB |
549 | case CPU_NEVADA: |
550 | uasm_i_nop(p); /* QED specifies 2 nops hazard */ | |
551 | uasm_i_nop(p); /* QED specifies 2 nops hazard */ | |
552 | tlbw(p); | |
553 | break; | |
554 | ||
2c93e12c | 555 | case CPU_R4300: |
1da177e4 LT |
556 | case CPU_5KC: |
557 | case CPU_TX49XX: | |
bdf21b18 | 558 | case CPU_PR4450: |
efa0f81c | 559 | case CPU_XLR: |
e30ec452 | 560 | uasm_i_nop(p); |
1da177e4 LT |
561 | tlbw(p); |
562 | break; | |
563 | ||
564 | case CPU_R10000: | |
565 | case CPU_R12000: | |
44d921b2 | 566 | case CPU_R14000: |
1da177e4 | 567 | case CPU_4KC: |
b1ec4c8e | 568 | case CPU_4KEC: |
113c62d9 | 569 | case CPU_M14KC: |
f8fa4811 | 570 | case CPU_M14KEC: |
1da177e4 | 571 | case CPU_SB1: |
93ce2f52 | 572 | case CPU_SB1A: |
1da177e4 LT |
573 | case CPU_4KSC: |
574 | case CPU_20KC: | |
575 | case CPU_25KF: | |
602977b0 KC |
576 | case CPU_BMIPS32: |
577 | case CPU_BMIPS3300: | |
578 | case CPU_BMIPS4350: | |
579 | case CPU_BMIPS4380: | |
580 | case CPU_BMIPS5000: | |
2a21c730 | 581 | case CPU_LOONGSON2: |
a644b277 | 582 | case CPU_R5500: |
8df5beac | 583 | if (m4kc_tlbp_war()) |
e30ec452 | 584 | uasm_i_nop(p); |
2f794d09 | 585 | case CPU_ALCHEMY: |
1da177e4 LT |
586 | tlbw(p); |
587 | break; | |
588 | ||
1da177e4 | 589 | case CPU_RM7000: |
e30ec452 TS |
590 | uasm_i_nop(p); |
591 | uasm_i_nop(p); | |
592 | uasm_i_nop(p); | |
593 | uasm_i_nop(p); | |
1da177e4 LT |
594 | tlbw(p); |
595 | break; | |
596 | ||
1da177e4 LT |
597 | case CPU_VR4111: |
598 | case CPU_VR4121: | |
599 | case CPU_VR4122: | |
600 | case CPU_VR4181: | |
601 | case CPU_VR4181A: | |
e30ec452 TS |
602 | uasm_i_nop(p); |
603 | uasm_i_nop(p); | |
1da177e4 | 604 | tlbw(p); |
e30ec452 TS |
605 | uasm_i_nop(p); |
606 | uasm_i_nop(p); | |
1da177e4 LT |
607 | break; |
608 | ||
609 | case CPU_VR4131: | |
610 | case CPU_VR4133: | |
7623debf | 611 | case CPU_R5432: |
e30ec452 TS |
612 | uasm_i_nop(p); |
613 | uasm_i_nop(p); | |
1da177e4 LT |
614 | tlbw(p); |
615 | break; | |
616 | ||
83ccf69d LPC |
617 | case CPU_JZRISC: |
618 | tlbw(p); | |
619 | uasm_i_nop(p); | |
620 | break; | |
621 | ||
1da177e4 LT |
622 | default: |
623 | panic("No TLB refill handler yet (CPU type: %d)", | |
624 | current_cpu_data.cputype); | |
625 | break; | |
626 | } | |
627 | } | |
628 | ||
078a55fc PG |
629 | static __maybe_unused void build_convert_pte_to_entrylo(u32 **p, |
630 | unsigned int reg) | |
fd062c84 | 631 | { |
05857c64 | 632 | if (cpu_has_rixi) { |
748e787e | 633 | UASM_i_ROTR(p, reg, reg, ilog2(_PAGE_GLOBAL)); |
6dd9344c DD |
634 | } else { |
635 | #ifdef CONFIG_64BIT_PHYS_ADDR | |
3be6022c | 636 | uasm_i_dsrl_safe(p, reg, reg, ilog2(_PAGE_GLOBAL)); |
6dd9344c DD |
637 | #else |
638 | UASM_i_SRL(p, reg, reg, ilog2(_PAGE_GLOBAL)); | |
639 | #endif | |
640 | } | |
641 | } | |
fd062c84 | 642 | |
aa1762f4 | 643 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
fd062c84 | 644 | |
078a55fc PG |
645 | static void build_restore_pagemask(u32 **p, struct uasm_reloc **r, |
646 | unsigned int tmp, enum label_id lid, | |
647 | int restore_scratch) | |
6dd9344c | 648 | { |
2c8c53e2 DD |
649 | if (restore_scratch) { |
650 | /* Reset default page size */ | |
651 | if (PM_DEFAULT_MASK >> 16) { | |
652 | uasm_i_lui(p, tmp, PM_DEFAULT_MASK >> 16); | |
653 | uasm_i_ori(p, tmp, tmp, PM_DEFAULT_MASK & 0xffff); | |
654 | uasm_i_mtc0(p, tmp, C0_PAGEMASK); | |
655 | uasm_il_b(p, r, lid); | |
656 | } else if (PM_DEFAULT_MASK) { | |
657 | uasm_i_ori(p, tmp, 0, PM_DEFAULT_MASK); | |
658 | uasm_i_mtc0(p, tmp, C0_PAGEMASK); | |
659 | uasm_il_b(p, r, lid); | |
660 | } else { | |
661 | uasm_i_mtc0(p, 0, C0_PAGEMASK); | |
662 | uasm_il_b(p, r, lid); | |
663 | } | |
0e6ecc1a | 664 | if (scratch_reg >= 0) |
7777b939 | 665 | UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg); |
2c8c53e2 DD |
666 | else |
667 | UASM_i_LW(p, 1, scratchpad_offset(0), 0); | |
fd062c84 | 668 | } else { |
2c8c53e2 DD |
669 | /* Reset default page size */ |
670 | if (PM_DEFAULT_MASK >> 16) { | |
671 | uasm_i_lui(p, tmp, PM_DEFAULT_MASK >> 16); | |
672 | uasm_i_ori(p, tmp, tmp, PM_DEFAULT_MASK & 0xffff); | |
673 | uasm_il_b(p, r, lid); | |
674 | uasm_i_mtc0(p, tmp, C0_PAGEMASK); | |
675 | } else if (PM_DEFAULT_MASK) { | |
676 | uasm_i_ori(p, tmp, 0, PM_DEFAULT_MASK); | |
677 | uasm_il_b(p, r, lid); | |
678 | uasm_i_mtc0(p, tmp, C0_PAGEMASK); | |
679 | } else { | |
680 | uasm_il_b(p, r, lid); | |
681 | uasm_i_mtc0(p, 0, C0_PAGEMASK); | |
682 | } | |
fd062c84 DD |
683 | } |
684 | } | |
685 | ||
078a55fc PG |
686 | static void build_huge_tlb_write_entry(u32 **p, struct uasm_label **l, |
687 | struct uasm_reloc **r, | |
688 | unsigned int tmp, | |
689 | enum tlb_write_entry wmode, | |
690 | int restore_scratch) | |
6dd9344c DD |
691 | { |
692 | /* Set huge page tlb entry size */ | |
693 | uasm_i_lui(p, tmp, PM_HUGE_MASK >> 16); | |
694 | uasm_i_ori(p, tmp, tmp, PM_HUGE_MASK & 0xffff); | |
695 | uasm_i_mtc0(p, tmp, C0_PAGEMASK); | |
696 | ||
697 | build_tlb_write_entry(p, l, r, wmode); | |
698 | ||
2c8c53e2 | 699 | build_restore_pagemask(p, r, tmp, label_leave, restore_scratch); |
6dd9344c DD |
700 | } |
701 | ||
fd062c84 DD |
702 | /* |
703 | * Check if Huge PTE is present, if so then jump to LABEL. | |
704 | */ | |
078a55fc | 705 | static void |
fd062c84 | 706 | build_is_huge_pte(u32 **p, struct uasm_reloc **r, unsigned int tmp, |
078a55fc | 707 | unsigned int pmd, int lid) |
fd062c84 DD |
708 | { |
709 | UASM_i_LW(p, tmp, 0, pmd); | |
cc33ae43 DD |
710 | if (use_bbit_insns()) { |
711 | uasm_il_bbit1(p, r, tmp, ilog2(_PAGE_HUGE), lid); | |
712 | } else { | |
713 | uasm_i_andi(p, tmp, tmp, _PAGE_HUGE); | |
714 | uasm_il_bnez(p, r, tmp, lid); | |
715 | } | |
fd062c84 DD |
716 | } |
717 | ||
078a55fc PG |
718 | static void build_huge_update_entries(u32 **p, unsigned int pte, |
719 | unsigned int tmp) | |
fd062c84 DD |
720 | { |
721 | int small_sequence; | |
722 | ||
723 | /* | |
724 | * A huge PTE describes an area the size of the | |
725 | * configured huge page size. This is twice the | |
726 | * of the large TLB entry size we intend to use. | |
727 | * A TLB entry half the size of the configured | |
728 | * huge page size is configured into entrylo0 | |
729 | * and entrylo1 to cover the contiguous huge PTE | |
730 | * address space. | |
731 | */ | |
732 | small_sequence = (HPAGE_SIZE >> 7) < 0x10000; | |
733 | ||
70342287 | 734 | /* We can clobber tmp. It isn't used after this.*/ |
fd062c84 DD |
735 | if (!small_sequence) |
736 | uasm_i_lui(p, tmp, HPAGE_SIZE >> (7 + 16)); | |
737 | ||
6dd9344c | 738 | build_convert_pte_to_entrylo(p, pte); |
9b8c3891 | 739 | UASM_i_MTC0(p, pte, C0_ENTRYLO0); /* load it */ |
fd062c84 DD |
740 | /* convert to entrylo1 */ |
741 | if (small_sequence) | |
742 | UASM_i_ADDIU(p, pte, pte, HPAGE_SIZE >> 7); | |
743 | else | |
744 | UASM_i_ADDU(p, pte, pte, tmp); | |
745 | ||
9b8c3891 | 746 | UASM_i_MTC0(p, pte, C0_ENTRYLO1); /* load it */ |
fd062c84 DD |
747 | } |
748 | ||
078a55fc PG |
749 | static void build_huge_handler_tail(u32 **p, struct uasm_reloc **r, |
750 | struct uasm_label **l, | |
751 | unsigned int pte, | |
752 | unsigned int ptr) | |
fd062c84 DD |
753 | { |
754 | #ifdef CONFIG_SMP | |
755 | UASM_i_SC(p, pte, 0, ptr); | |
756 | uasm_il_beqz(p, r, pte, label_tlb_huge_update); | |
757 | UASM_i_LW(p, pte, 0, ptr); /* Needed because SC killed our PTE */ | |
758 | #else | |
759 | UASM_i_SW(p, pte, 0, ptr); | |
760 | #endif | |
761 | build_huge_update_entries(p, pte, ptr); | |
2c8c53e2 | 762 | build_huge_tlb_write_entry(p, l, r, pte, tlb_indexed, 0); |
fd062c84 | 763 | } |
aa1762f4 | 764 | #endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */ |
fd062c84 | 765 | |
875d43e7 | 766 | #ifdef CONFIG_64BIT |
1da177e4 LT |
767 | /* |
768 | * TMP and PTR are scratch. | |
769 | * TMP will be clobbered, PTR will hold the pmd entry. | |
770 | */ | |
078a55fc | 771 | static void |
e30ec452 | 772 | build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, |
1da177e4 LT |
773 | unsigned int tmp, unsigned int ptr) |
774 | { | |
82622284 | 775 | #ifndef CONFIG_MIPS_PGD_C0_CONTEXT |
1da177e4 | 776 | long pgdc = (long)pgd_current; |
82622284 | 777 | #endif |
1da177e4 LT |
778 | /* |
779 | * The vmalloc handling is not in the hotpath. | |
780 | */ | |
e30ec452 | 781 | uasm_i_dmfc0(p, tmp, C0_BADVADDR); |
1ec56329 DD |
782 | |
783 | if (check_for_high_segbits) { | |
784 | /* | |
785 | * The kernel currently implicitely assumes that the | |
786 | * MIPS SEGBITS parameter for the processor is | |
787 | * (PGDIR_SHIFT+PGDIR_BITS) or less, and will never | |
788 | * allocate virtual addresses outside the maximum | |
789 | * range for SEGBITS = (PGDIR_SHIFT+PGDIR_BITS). But | |
790 | * that doesn't prevent user code from accessing the | |
791 | * higher xuseg addresses. Here, we make sure that | |
792 | * everything but the lower xuseg addresses goes down | |
793 | * the module_alloc/vmalloc path. | |
794 | */ | |
795 | uasm_i_dsrl_safe(p, ptr, tmp, PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3); | |
796 | uasm_il_bnez(p, r, ptr, label_vmalloc); | |
797 | } else { | |
798 | uasm_il_bltz(p, r, tmp, label_vmalloc); | |
799 | } | |
e30ec452 | 800 | /* No uasm_i_nop needed here, since the next insn doesn't touch TMP. */ |
1da177e4 | 801 | |
82622284 | 802 | #ifdef CONFIG_MIPS_PGD_C0_CONTEXT |
3d8bfdd0 DD |
803 | if (pgd_reg != -1) { |
804 | /* pgd is in pgd_reg */ | |
7777b939 | 805 | UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg); |
3d8bfdd0 DD |
806 | } else { |
807 | /* | |
808 | * &pgd << 11 stored in CONTEXT [23..63]. | |
809 | */ | |
810 | UASM_i_MFC0(p, ptr, C0_CONTEXT); | |
811 | ||
812 | /* Clear lower 23 bits of context. */ | |
813 | uasm_i_dins(p, ptr, 0, 0, 23); | |
814 | ||
70342287 | 815 | /* 1 0 1 0 1 << 6 xkphys cached */ |
3d8bfdd0 DD |
816 | uasm_i_ori(p, ptr, ptr, 0x540); |
817 | uasm_i_drotr(p, ptr, ptr, 11); | |
818 | } | |
82622284 | 819 | #elif defined(CONFIG_SMP) |
c2377a42 J |
820 | UASM_i_CPUID_MFC0(p, ptr, SMP_CPUID_REG); |
821 | uasm_i_dsrl_safe(p, ptr, ptr, SMP_CPUID_PTRSHIFT); | |
e30ec452 TS |
822 | UASM_i_LA_mostly(p, tmp, pgdc); |
823 | uasm_i_daddu(p, ptr, ptr, tmp); | |
824 | uasm_i_dmfc0(p, tmp, C0_BADVADDR); | |
825 | uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr); | |
1da177e4 | 826 | #else |
e30ec452 TS |
827 | UASM_i_LA_mostly(p, ptr, pgdc); |
828 | uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr); | |
1da177e4 LT |
829 | #endif |
830 | ||
e30ec452 | 831 | uasm_l_vmalloc_done(l, *p); |
242954b5 | 832 | |
3be6022c DD |
833 | /* get pgd offset in bytes */ |
834 | uasm_i_dsrl_safe(p, tmp, tmp, PGDIR_SHIFT - 3); | |
e30ec452 TS |
835 | |
836 | uasm_i_andi(p, tmp, tmp, (PTRS_PER_PGD - 1)<<3); | |
837 | uasm_i_daddu(p, ptr, ptr, tmp); /* add in pgd offset */ | |
325f8a0a | 838 | #ifndef __PAGETABLE_PMD_FOLDED |
e30ec452 TS |
839 | uasm_i_dmfc0(p, tmp, C0_BADVADDR); /* get faulting address */ |
840 | uasm_i_ld(p, ptr, 0, ptr); /* get pmd pointer */ | |
3be6022c | 841 | uasm_i_dsrl_safe(p, tmp, tmp, PMD_SHIFT-3); /* get pmd offset in bytes */ |
e30ec452 TS |
842 | uasm_i_andi(p, tmp, tmp, (PTRS_PER_PMD - 1)<<3); |
843 | uasm_i_daddu(p, ptr, ptr, tmp); /* add in pmd offset */ | |
325f8a0a | 844 | #endif |
1da177e4 LT |
845 | } |
846 | ||
847 | /* | |
848 | * BVADDR is the faulting address, PTR is scratch. | |
849 | * PTR will hold the pgd for vmalloc. | |
850 | */ | |
078a55fc | 851 | static void |
e30ec452 | 852 | build_get_pgd_vmalloc64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, |
1ec56329 DD |
853 | unsigned int bvaddr, unsigned int ptr, |
854 | enum vmalloc64_mode mode) | |
1da177e4 LT |
855 | { |
856 | long swpd = (long)swapper_pg_dir; | |
1ec56329 DD |
857 | int single_insn_swpd; |
858 | int did_vmalloc_branch = 0; | |
859 | ||
860 | single_insn_swpd = uasm_in_compat_space_p(swpd) && !uasm_rel_lo(swpd); | |
1da177e4 | 861 | |
e30ec452 | 862 | uasm_l_vmalloc(l, *p); |
1da177e4 | 863 | |
2c8c53e2 | 864 | if (mode != not_refill && check_for_high_segbits) { |
1ec56329 DD |
865 | if (single_insn_swpd) { |
866 | uasm_il_bltz(p, r, bvaddr, label_vmalloc_done); | |
867 | uasm_i_lui(p, ptr, uasm_rel_hi(swpd)); | |
868 | did_vmalloc_branch = 1; | |
869 | /* fall through */ | |
870 | } else { | |
871 | uasm_il_bgez(p, r, bvaddr, label_large_segbits_fault); | |
872 | } | |
873 | } | |
874 | if (!did_vmalloc_branch) { | |
875 | if (uasm_in_compat_space_p(swpd) && !uasm_rel_lo(swpd)) { | |
876 | uasm_il_b(p, r, label_vmalloc_done); | |
877 | uasm_i_lui(p, ptr, uasm_rel_hi(swpd)); | |
878 | } else { | |
879 | UASM_i_LA_mostly(p, ptr, swpd); | |
880 | uasm_il_b(p, r, label_vmalloc_done); | |
881 | if (uasm_in_compat_space_p(swpd)) | |
882 | uasm_i_addiu(p, ptr, ptr, uasm_rel_lo(swpd)); | |
883 | else | |
884 | uasm_i_daddiu(p, ptr, ptr, uasm_rel_lo(swpd)); | |
885 | } | |
886 | } | |
2c8c53e2 | 887 | if (mode != not_refill && check_for_high_segbits) { |
1ec56329 DD |
888 | uasm_l_large_segbits_fault(l, *p); |
889 | /* | |
890 | * We get here if we are an xsseg address, or if we are | |
891 | * an xuseg address above (PGDIR_SHIFT+PGDIR_BITS) boundary. | |
892 | * | |
893 | * Ignoring xsseg (assume disabled so would generate | |
894 | * (address errors?), the only remaining possibility | |
895 | * is the upper xuseg addresses. On processors with | |
896 | * TLB_SEGBITS <= PGDIR_SHIFT+PGDIR_BITS, these | |
897 | * addresses would have taken an address error. We try | |
898 | * to mimic that here by taking a load/istream page | |
899 | * fault. | |
900 | */ | |
901 | UASM_i_LA(p, ptr, (unsigned long)tlb_do_page_fault_0); | |
902 | uasm_i_jr(p, ptr); | |
2c8c53e2 DD |
903 | |
904 | if (mode == refill_scratch) { | |
0e6ecc1a | 905 | if (scratch_reg >= 0) |
7777b939 | 906 | UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg); |
2c8c53e2 DD |
907 | else |
908 | UASM_i_LW(p, 1, scratchpad_offset(0), 0); | |
909 | } else { | |
910 | uasm_i_nop(p); | |
911 | } | |
1da177e4 LT |
912 | } |
913 | } | |
914 | ||
875d43e7 | 915 | #else /* !CONFIG_64BIT */ |
1da177e4 LT |
916 | |
917 | /* | |
918 | * TMP and PTR are scratch. | |
919 | * TMP will be clobbered, PTR will hold the pgd entry. | |
920 | */ | |
078a55fc | 921 | static void __maybe_unused |
1da177e4 LT |
922 | build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr) |
923 | { | |
924 | long pgdc = (long)pgd_current; | |
925 | ||
926 | /* 32 bit SMP has smp_processor_id() stored in CONTEXT. */ | |
927 | #ifdef CONFIG_SMP | |
c2377a42 | 928 | uasm_i_mfc0(p, ptr, SMP_CPUID_REG); |
e30ec452 | 929 | UASM_i_LA_mostly(p, tmp, pgdc); |
c2377a42 | 930 | uasm_i_srl(p, ptr, ptr, SMP_CPUID_PTRSHIFT); |
e30ec452 | 931 | uasm_i_addu(p, ptr, tmp, ptr); |
1da177e4 | 932 | #else |
e30ec452 | 933 | UASM_i_LA_mostly(p, ptr, pgdc); |
1da177e4 | 934 | #endif |
e30ec452 TS |
935 | uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */ |
936 | uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr); | |
937 | uasm_i_srl(p, tmp, tmp, PGDIR_SHIFT); /* get pgd only bits */ | |
938 | uasm_i_sll(p, tmp, tmp, PGD_T_LOG2); | |
939 | uasm_i_addu(p, ptr, ptr, tmp); /* add in pgd offset */ | |
1da177e4 LT |
940 | } |
941 | ||
875d43e7 | 942 | #endif /* !CONFIG_64BIT */ |
1da177e4 | 943 | |
078a55fc | 944 | static void build_adjust_context(u32 **p, unsigned int ctx) |
1da177e4 | 945 | { |
242954b5 | 946 | unsigned int shift = 4 - (PTE_T_LOG2 + 1) + PAGE_SHIFT - 12; |
1da177e4 LT |
947 | unsigned int mask = (PTRS_PER_PTE / 2 - 1) << (PTE_T_LOG2 + 1); |
948 | ||
10cc3529 | 949 | switch (current_cpu_type()) { |
1da177e4 LT |
950 | case CPU_VR41XX: |
951 | case CPU_VR4111: | |
952 | case CPU_VR4121: | |
953 | case CPU_VR4122: | |
954 | case CPU_VR4131: | |
955 | case CPU_VR4181: | |
956 | case CPU_VR4181A: | |
957 | case CPU_VR4133: | |
958 | shift += 2; | |
959 | break; | |
960 | ||
961 | default: | |
962 | break; | |
963 | } | |
964 | ||
965 | if (shift) | |
e30ec452 TS |
966 | UASM_i_SRL(p, ctx, ctx, shift); |
967 | uasm_i_andi(p, ctx, ctx, mask); | |
1da177e4 LT |
968 | } |
969 | ||
078a55fc | 970 | static void build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr) |
1da177e4 LT |
971 | { |
972 | /* | |
973 | * Bug workaround for the Nevada. It seems as if under certain | |
974 | * circumstances the move from cp0_context might produce a | |
975 | * bogus result when the mfc0 instruction and its consumer are | |
976 | * in a different cacheline or a load instruction, probably any | |
977 | * memory reference, is between them. | |
978 | */ | |
10cc3529 | 979 | switch (current_cpu_type()) { |
1da177e4 | 980 | case CPU_NEVADA: |
e30ec452 | 981 | UASM_i_LW(p, ptr, 0, ptr); |
1da177e4 LT |
982 | GET_CONTEXT(p, tmp); /* get context reg */ |
983 | break; | |
984 | ||
985 | default: | |
986 | GET_CONTEXT(p, tmp); /* get context reg */ | |
e30ec452 | 987 | UASM_i_LW(p, ptr, 0, ptr); |
1da177e4 LT |
988 | break; |
989 | } | |
990 | ||
991 | build_adjust_context(p, tmp); | |
e30ec452 | 992 | UASM_i_ADDU(p, ptr, ptr, tmp); /* add in offset */ |
1da177e4 LT |
993 | } |
994 | ||
078a55fc | 995 | static void build_update_entries(u32 **p, unsigned int tmp, unsigned int ptep) |
1da177e4 LT |
996 | { |
997 | /* | |
998 | * 64bit address support (36bit on a 32bit CPU) in a 32bit | |
999 | * Kernel is a special case. Only a few CPUs use it. | |
1000 | */ | |
1001 | #ifdef CONFIG_64BIT_PHYS_ADDR | |
1002 | if (cpu_has_64bits) { | |
e30ec452 TS |
1003 | uasm_i_ld(p, tmp, 0, ptep); /* get even pte */ |
1004 | uasm_i_ld(p, ptep, sizeof(pte_t), ptep); /* get odd pte */ | |
05857c64 | 1005 | if (cpu_has_rixi) { |
748e787e | 1006 | UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL)); |
6dd9344c | 1007 | UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */ |
748e787e | 1008 | UASM_i_ROTR(p, ptep, ptep, ilog2(_PAGE_GLOBAL)); |
6dd9344c | 1009 | } else { |
3be6022c | 1010 | uasm_i_dsrl_safe(p, tmp, tmp, ilog2(_PAGE_GLOBAL)); /* convert to entrylo0 */ |
6dd9344c | 1011 | UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */ |
3be6022c | 1012 | uasm_i_dsrl_safe(p, ptep, ptep, ilog2(_PAGE_GLOBAL)); /* convert to entrylo1 */ |
6dd9344c | 1013 | } |
9b8c3891 | 1014 | UASM_i_MTC0(p, ptep, C0_ENTRYLO1); /* load it */ |
1da177e4 LT |
1015 | } else { |
1016 | int pte_off_even = sizeof(pte_t) / 2; | |
1017 | int pte_off_odd = pte_off_even + sizeof(pte_t); | |
1018 | ||
1019 | /* The pte entries are pre-shifted */ | |
e30ec452 | 1020 | uasm_i_lw(p, tmp, pte_off_even, ptep); /* get even pte */ |
9b8c3891 | 1021 | UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */ |
e30ec452 | 1022 | uasm_i_lw(p, ptep, pte_off_odd, ptep); /* get odd pte */ |
9b8c3891 | 1023 | UASM_i_MTC0(p, ptep, C0_ENTRYLO1); /* load it */ |
1da177e4 LT |
1024 | } |
1025 | #else | |
e30ec452 TS |
1026 | UASM_i_LW(p, tmp, 0, ptep); /* get even pte */ |
1027 | UASM_i_LW(p, ptep, sizeof(pte_t), ptep); /* get odd pte */ | |
1da177e4 LT |
1028 | if (r45k_bvahwbug()) |
1029 | build_tlb_probe_entry(p); | |
05857c64 | 1030 | if (cpu_has_rixi) { |
748e787e | 1031 | UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL)); |
6dd9344c DD |
1032 | if (r4k_250MHZhwbug()) |
1033 | UASM_i_MTC0(p, 0, C0_ENTRYLO0); | |
1034 | UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */ | |
748e787e | 1035 | UASM_i_ROTR(p, ptep, ptep, ilog2(_PAGE_GLOBAL)); |
6dd9344c DD |
1036 | } else { |
1037 | UASM_i_SRL(p, tmp, tmp, ilog2(_PAGE_GLOBAL)); /* convert to entrylo0 */ | |
1038 | if (r4k_250MHZhwbug()) | |
1039 | UASM_i_MTC0(p, 0, C0_ENTRYLO0); | |
1040 | UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */ | |
1041 | UASM_i_SRL(p, ptep, ptep, ilog2(_PAGE_GLOBAL)); /* convert to entrylo1 */ | |
1042 | if (r45k_bvahwbug()) | |
1043 | uasm_i_mfc0(p, tmp, C0_INDEX); | |
1044 | } | |
1da177e4 | 1045 | if (r4k_250MHZhwbug()) |
9b8c3891 DD |
1046 | UASM_i_MTC0(p, 0, C0_ENTRYLO1); |
1047 | UASM_i_MTC0(p, ptep, C0_ENTRYLO1); /* load it */ | |
1da177e4 LT |
1048 | #endif |
1049 | } | |
1050 | ||
2c8c53e2 DD |
1051 | struct mips_huge_tlb_info { |
1052 | int huge_pte; | |
1053 | int restore_scratch; | |
1054 | }; | |
1055 | ||
078a55fc | 1056 | static struct mips_huge_tlb_info |
2c8c53e2 DD |
1057 | build_fast_tlb_refill_handler (u32 **p, struct uasm_label **l, |
1058 | struct uasm_reloc **r, unsigned int tmp, | |
7777b939 | 1059 | unsigned int ptr, int c0_scratch_reg) |
2c8c53e2 DD |
1060 | { |
1061 | struct mips_huge_tlb_info rv; | |
1062 | unsigned int even, odd; | |
1063 | int vmalloc_branch_delay_filled = 0; | |
1064 | const int scratch = 1; /* Our extra working register */ | |
1065 | ||
1066 | rv.huge_pte = scratch; | |
1067 | rv.restore_scratch = 0; | |
1068 | ||
1069 | if (check_for_high_segbits) { | |
1070 | UASM_i_MFC0(p, tmp, C0_BADVADDR); | |
1071 | ||
1072 | if (pgd_reg != -1) | |
7777b939 | 1073 | UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg); |
2c8c53e2 DD |
1074 | else |
1075 | UASM_i_MFC0(p, ptr, C0_CONTEXT); | |
1076 | ||
7777b939 J |
1077 | if (c0_scratch_reg >= 0) |
1078 | UASM_i_MTC0(p, scratch, c0_kscratch(), c0_scratch_reg); | |
2c8c53e2 DD |
1079 | else |
1080 | UASM_i_SW(p, scratch, scratchpad_offset(0), 0); | |
1081 | ||
1082 | uasm_i_dsrl_safe(p, scratch, tmp, | |
1083 | PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3); | |
1084 | uasm_il_bnez(p, r, scratch, label_vmalloc); | |
1085 | ||
1086 | if (pgd_reg == -1) { | |
1087 | vmalloc_branch_delay_filled = 1; | |
1088 | /* Clear lower 23 bits of context. */ | |
1089 | uasm_i_dins(p, ptr, 0, 0, 23); | |
1090 | } | |
1091 | } else { | |
1092 | if (pgd_reg != -1) | |
7777b939 | 1093 | UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg); |
2c8c53e2 DD |
1094 | else |
1095 | UASM_i_MFC0(p, ptr, C0_CONTEXT); | |
1096 | ||
1097 | UASM_i_MFC0(p, tmp, C0_BADVADDR); | |
1098 | ||
7777b939 J |
1099 | if (c0_scratch_reg >= 0) |
1100 | UASM_i_MTC0(p, scratch, c0_kscratch(), c0_scratch_reg); | |
2c8c53e2 DD |
1101 | else |
1102 | UASM_i_SW(p, scratch, scratchpad_offset(0), 0); | |
1103 | ||
1104 | if (pgd_reg == -1) | |
1105 | /* Clear lower 23 bits of context. */ | |
1106 | uasm_i_dins(p, ptr, 0, 0, 23); | |
1107 | ||
1108 | uasm_il_bltz(p, r, tmp, label_vmalloc); | |
1109 | } | |
1110 | ||
1111 | if (pgd_reg == -1) { | |
1112 | vmalloc_branch_delay_filled = 1; | |
70342287 | 1113 | /* 1 0 1 0 1 << 6 xkphys cached */ |
2c8c53e2 DD |
1114 | uasm_i_ori(p, ptr, ptr, 0x540); |
1115 | uasm_i_drotr(p, ptr, ptr, 11); | |
1116 | } | |
1117 | ||
1118 | #ifdef __PAGETABLE_PMD_FOLDED | |
1119 | #define LOC_PTEP scratch | |
1120 | #else | |
1121 | #define LOC_PTEP ptr | |
1122 | #endif | |
1123 | ||
1124 | if (!vmalloc_branch_delay_filled) | |
1125 | /* get pgd offset in bytes */ | |
1126 | uasm_i_dsrl_safe(p, scratch, tmp, PGDIR_SHIFT - 3); | |
1127 | ||
1128 | uasm_l_vmalloc_done(l, *p); | |
1129 | ||
1130 | /* | |
70342287 RB |
1131 | * tmp ptr |
1132 | * fall-through case = badvaddr *pgd_current | |
1133 | * vmalloc case = badvaddr swapper_pg_dir | |
2c8c53e2 DD |
1134 | */ |
1135 | ||
1136 | if (vmalloc_branch_delay_filled) | |
1137 | /* get pgd offset in bytes */ | |
1138 | uasm_i_dsrl_safe(p, scratch, tmp, PGDIR_SHIFT - 3); | |
1139 | ||
1140 | #ifdef __PAGETABLE_PMD_FOLDED | |
1141 | GET_CONTEXT(p, tmp); /* get context reg */ | |
1142 | #endif | |
1143 | uasm_i_andi(p, scratch, scratch, (PTRS_PER_PGD - 1) << 3); | |
1144 | ||
1145 | if (use_lwx_insns()) { | |
1146 | UASM_i_LWX(p, LOC_PTEP, scratch, ptr); | |
1147 | } else { | |
1148 | uasm_i_daddu(p, ptr, ptr, scratch); /* add in pgd offset */ | |
1149 | uasm_i_ld(p, LOC_PTEP, 0, ptr); /* get pmd pointer */ | |
1150 | } | |
1151 | ||
1152 | #ifndef __PAGETABLE_PMD_FOLDED | |
1153 | /* get pmd offset in bytes */ | |
1154 | uasm_i_dsrl_safe(p, scratch, tmp, PMD_SHIFT - 3); | |
1155 | uasm_i_andi(p, scratch, scratch, (PTRS_PER_PMD - 1) << 3); | |
1156 | GET_CONTEXT(p, tmp); /* get context reg */ | |
1157 | ||
1158 | if (use_lwx_insns()) { | |
1159 | UASM_i_LWX(p, scratch, scratch, ptr); | |
1160 | } else { | |
1161 | uasm_i_daddu(p, ptr, ptr, scratch); /* add in pmd offset */ | |
1162 | UASM_i_LW(p, scratch, 0, ptr); | |
1163 | } | |
1164 | #endif | |
1165 | /* Adjust the context during the load latency. */ | |
1166 | build_adjust_context(p, tmp); | |
1167 | ||
aa1762f4 | 1168 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
2c8c53e2 DD |
1169 | uasm_il_bbit1(p, r, scratch, ilog2(_PAGE_HUGE), label_tlb_huge_update); |
1170 | /* | |
1171 | * The in the LWX case we don't want to do the load in the | |
70342287 | 1172 | * delay slot. It cannot issue in the same cycle and may be |
2c8c53e2 DD |
1173 | * speculative and unneeded. |
1174 | */ | |
1175 | if (use_lwx_insns()) | |
1176 | uasm_i_nop(p); | |
aa1762f4 | 1177 | #endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */ |
2c8c53e2 DD |
1178 | |
1179 | ||
1180 | /* build_update_entries */ | |
1181 | if (use_lwx_insns()) { | |
1182 | even = ptr; | |
1183 | odd = tmp; | |
1184 | UASM_i_LWX(p, even, scratch, tmp); | |
1185 | UASM_i_ADDIU(p, tmp, tmp, sizeof(pte_t)); | |
1186 | UASM_i_LWX(p, odd, scratch, tmp); | |
1187 | } else { | |
1188 | UASM_i_ADDU(p, ptr, scratch, tmp); /* add in offset */ | |
1189 | even = tmp; | |
1190 | odd = ptr; | |
1191 | UASM_i_LW(p, even, 0, ptr); /* get even pte */ | |
1192 | UASM_i_LW(p, odd, sizeof(pte_t), ptr); /* get odd pte */ | |
1193 | } | |
05857c64 | 1194 | if (cpu_has_rixi) { |
748e787e | 1195 | uasm_i_drotr(p, even, even, ilog2(_PAGE_GLOBAL)); |
2c8c53e2 | 1196 | UASM_i_MTC0(p, even, C0_ENTRYLO0); /* load it */ |
748e787e | 1197 | uasm_i_drotr(p, odd, odd, ilog2(_PAGE_GLOBAL)); |
2c8c53e2 DD |
1198 | } else { |
1199 | uasm_i_dsrl_safe(p, even, even, ilog2(_PAGE_GLOBAL)); | |
1200 | UASM_i_MTC0(p, even, C0_ENTRYLO0); /* load it */ | |
1201 | uasm_i_dsrl_safe(p, odd, odd, ilog2(_PAGE_GLOBAL)); | |
1202 | } | |
1203 | UASM_i_MTC0(p, odd, C0_ENTRYLO1); /* load it */ | |
1204 | ||
7777b939 J |
1205 | if (c0_scratch_reg >= 0) { |
1206 | UASM_i_MFC0(p, scratch, c0_kscratch(), c0_scratch_reg); | |
2c8c53e2 DD |
1207 | build_tlb_write_entry(p, l, r, tlb_random); |
1208 | uasm_l_leave(l, *p); | |
1209 | rv.restore_scratch = 1; | |
1210 | } else if (PAGE_SHIFT == 14 || PAGE_SHIFT == 13) { | |
1211 | build_tlb_write_entry(p, l, r, tlb_random); | |
1212 | uasm_l_leave(l, *p); | |
1213 | UASM_i_LW(p, scratch, scratchpad_offset(0), 0); | |
1214 | } else { | |
1215 | UASM_i_LW(p, scratch, scratchpad_offset(0), 0); | |
1216 | build_tlb_write_entry(p, l, r, tlb_random); | |
1217 | uasm_l_leave(l, *p); | |
1218 | rv.restore_scratch = 1; | |
1219 | } | |
1220 | ||
1221 | uasm_i_eret(p); /* return from trap */ | |
1222 | ||
1223 | return rv; | |
1224 | } | |
1225 | ||
e6f72d3a DD |
1226 | /* |
1227 | * For a 64-bit kernel, we are using the 64-bit XTLB refill exception | |
1228 | * because EXL == 0. If we wrap, we can also use the 32 instruction | |
1229 | * slots before the XTLB refill exception handler which belong to the | |
1230 | * unused TLB refill exception. | |
1231 | */ | |
1232 | #define MIPS64_REFILL_INSNS 32 | |
1233 | ||
078a55fc | 1234 | static void build_r4000_tlb_refill_handler(void) |
1da177e4 LT |
1235 | { |
1236 | u32 *p = tlb_handler; | |
e30ec452 TS |
1237 | struct uasm_label *l = labels; |
1238 | struct uasm_reloc *r = relocs; | |
1da177e4 LT |
1239 | u32 *f; |
1240 | unsigned int final_len; | |
4a9040f4 RB |
1241 | struct mips_huge_tlb_info htlb_info __maybe_unused; |
1242 | enum vmalloc64_mode vmalloc_mode __maybe_unused; | |
1da177e4 LT |
1243 | |
1244 | memset(tlb_handler, 0, sizeof(tlb_handler)); | |
1245 | memset(labels, 0, sizeof(labels)); | |
1246 | memset(relocs, 0, sizeof(relocs)); | |
1247 | memset(final_handler, 0, sizeof(final_handler)); | |
1248 | ||
0e6ecc1a | 1249 | if ((scratch_reg >= 0 || scratchpad_available()) && use_bbit_insns()) { |
2c8c53e2 DD |
1250 | htlb_info = build_fast_tlb_refill_handler(&p, &l, &r, K0, K1, |
1251 | scratch_reg); | |
1252 | vmalloc_mode = refill_scratch; | |
1253 | } else { | |
1254 | htlb_info.huge_pte = K0; | |
1255 | htlb_info.restore_scratch = 0; | |
1256 | vmalloc_mode = refill_noscratch; | |
1257 | /* | |
1258 | * create the plain linear handler | |
1259 | */ | |
1260 | if (bcm1250_m3_war()) { | |
1261 | unsigned int segbits = 44; | |
1262 | ||
1263 | uasm_i_dmfc0(&p, K0, C0_BADVADDR); | |
1264 | uasm_i_dmfc0(&p, K1, C0_ENTRYHI); | |
1265 | uasm_i_xor(&p, K0, K0, K1); | |
1266 | uasm_i_dsrl_safe(&p, K1, K0, 62); | |
1267 | uasm_i_dsrl_safe(&p, K0, K0, 12 + 1); | |
1268 | uasm_i_dsll_safe(&p, K0, K0, 64 + 12 + 1 - segbits); | |
1269 | uasm_i_or(&p, K0, K0, K1); | |
1270 | uasm_il_bnez(&p, &r, K0, label_leave); | |
1271 | /* No need for uasm_i_nop */ | |
1272 | } | |
1da177e4 | 1273 | |
875d43e7 | 1274 | #ifdef CONFIG_64BIT |
2c8c53e2 | 1275 | build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */ |
1da177e4 | 1276 | #else |
2c8c53e2 | 1277 | build_get_pgde32(&p, K0, K1); /* get pgd in K1 */ |
1da177e4 LT |
1278 | #endif |
1279 | ||
aa1762f4 | 1280 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
2c8c53e2 | 1281 | build_is_huge_pte(&p, &r, K0, K1, label_tlb_huge_update); |
fd062c84 DD |
1282 | #endif |
1283 | ||
2c8c53e2 DD |
1284 | build_get_ptep(&p, K0, K1); |
1285 | build_update_entries(&p, K0, K1); | |
1286 | build_tlb_write_entry(&p, &l, &r, tlb_random); | |
1287 | uasm_l_leave(&l, p); | |
1288 | uasm_i_eret(&p); /* return from trap */ | |
1289 | } | |
aa1762f4 | 1290 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
fd062c84 | 1291 | uasm_l_tlb_huge_update(&l, p); |
2c8c53e2 DD |
1292 | build_huge_update_entries(&p, htlb_info.huge_pte, K1); |
1293 | build_huge_tlb_write_entry(&p, &l, &r, K0, tlb_random, | |
1294 | htlb_info.restore_scratch); | |
fd062c84 DD |
1295 | #endif |
1296 | ||
875d43e7 | 1297 | #ifdef CONFIG_64BIT |
2c8c53e2 | 1298 | build_get_pgd_vmalloc64(&p, &l, &r, K0, K1, vmalloc_mode); |
1da177e4 LT |
1299 | #endif |
1300 | ||
1301 | /* | |
1302 | * Overflow check: For the 64bit handler, we need at least one | |
1303 | * free instruction slot for the wrap-around branch. In worst | |
1304 | * case, if the intended insertion point is a delay slot, we | |
4b3f686d | 1305 | * need three, with the second nop'ed and the third being |
1da177e4 LT |
1306 | * unused. |
1307 | */ | |
2a21c730 FZ |
1308 | /* Loongson2 ebase is different than r4k, we have more space */ |
1309 | #if defined(CONFIG_32BIT) || defined(CONFIG_CPU_LOONGSON2) | |
1da177e4 LT |
1310 | if ((p - tlb_handler) > 64) |
1311 | panic("TLB refill handler space exceeded"); | |
1312 | #else | |
e6f72d3a DD |
1313 | if (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 1) |
1314 | || (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 3) | |
1315 | && uasm_insn_has_bdelay(relocs, | |
1316 | tlb_handler + MIPS64_REFILL_INSNS - 3))) | |
1da177e4 LT |
1317 | panic("TLB refill handler space exceeded"); |
1318 | #endif | |
1319 | ||
1320 | /* | |
1321 | * Now fold the handler in the TLB refill handler space. | |
1322 | */ | |
2a21c730 | 1323 | #if defined(CONFIG_32BIT) || defined(CONFIG_CPU_LOONGSON2) |
1da177e4 LT |
1324 | f = final_handler; |
1325 | /* Simplest case, just copy the handler. */ | |
e30ec452 | 1326 | uasm_copy_handler(relocs, labels, tlb_handler, p, f); |
1da177e4 | 1327 | final_len = p - tlb_handler; |
875d43e7 | 1328 | #else /* CONFIG_64BIT */ |
e6f72d3a DD |
1329 | f = final_handler + MIPS64_REFILL_INSNS; |
1330 | if ((p - tlb_handler) <= MIPS64_REFILL_INSNS) { | |
1da177e4 | 1331 | /* Just copy the handler. */ |
e30ec452 | 1332 | uasm_copy_handler(relocs, labels, tlb_handler, p, f); |
1da177e4 LT |
1333 | final_len = p - tlb_handler; |
1334 | } else { | |
aa1762f4 | 1335 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
fd062c84 | 1336 | const enum label_id ls = label_tlb_huge_update; |
95affdda DD |
1337 | #else |
1338 | const enum label_id ls = label_vmalloc; | |
1339 | #endif | |
1340 | u32 *split; | |
1341 | int ov = 0; | |
1342 | int i; | |
1343 | ||
1344 | for (i = 0; i < ARRAY_SIZE(labels) && labels[i].lab != ls; i++) | |
1345 | ; | |
1346 | BUG_ON(i == ARRAY_SIZE(labels)); | |
1347 | split = labels[i].addr; | |
1da177e4 LT |
1348 | |
1349 | /* | |
95affdda | 1350 | * See if we have overflown one way or the other. |
1da177e4 | 1351 | */ |
95affdda DD |
1352 | if (split > tlb_handler + MIPS64_REFILL_INSNS || |
1353 | split < p - MIPS64_REFILL_INSNS) | |
1354 | ov = 1; | |
1355 | ||
1356 | if (ov) { | |
1357 | /* | |
1358 | * Split two instructions before the end. One | |
1359 | * for the branch and one for the instruction | |
1360 | * in the delay slot. | |
1361 | */ | |
1362 | split = tlb_handler + MIPS64_REFILL_INSNS - 2; | |
1363 | ||
1364 | /* | |
1365 | * If the branch would fall in a delay slot, | |
1366 | * we must back up an additional instruction | |
1367 | * so that it is no longer in a delay slot. | |
1368 | */ | |
1369 | if (uasm_insn_has_bdelay(relocs, split - 1)) | |
1370 | split--; | |
1371 | } | |
1da177e4 | 1372 | /* Copy first part of the handler. */ |
e30ec452 | 1373 | uasm_copy_handler(relocs, labels, tlb_handler, split, f); |
1da177e4 LT |
1374 | f += split - tlb_handler; |
1375 | ||
95affdda DD |
1376 | if (ov) { |
1377 | /* Insert branch. */ | |
1378 | uasm_l_split(&l, final_handler); | |
1379 | uasm_il_b(&f, &r, label_split); | |
1380 | if (uasm_insn_has_bdelay(relocs, split)) | |
1381 | uasm_i_nop(&f); | |
1382 | else { | |
1383 | uasm_copy_handler(relocs, labels, | |
1384 | split, split + 1, f); | |
1385 | uasm_move_labels(labels, f, f + 1, -1); | |
1386 | f++; | |
1387 | split++; | |
1388 | } | |
1da177e4 LT |
1389 | } |
1390 | ||
1391 | /* Copy the rest of the handler. */ | |
e30ec452 | 1392 | uasm_copy_handler(relocs, labels, split, p, final_handler); |
e6f72d3a DD |
1393 | final_len = (f - (final_handler + MIPS64_REFILL_INSNS)) + |
1394 | (p - split); | |
1da177e4 | 1395 | } |
875d43e7 | 1396 | #endif /* CONFIG_64BIT */ |
1da177e4 | 1397 | |
e30ec452 TS |
1398 | uasm_resolve_relocs(relocs, labels); |
1399 | pr_debug("Wrote TLB refill handler (%u instructions).\n", | |
1400 | final_len); | |
1da177e4 | 1401 | |
91b05e67 | 1402 | memcpy((void *)ebase, final_handler, 0x100); |
92b1e6a6 | 1403 | |
a2c763e0 | 1404 | dump_handler("r4000_tlb_refill", (u32 *)ebase, 64); |
1da177e4 LT |
1405 | } |
1406 | ||
6ba045f9 J |
1407 | extern u32 handle_tlbl[], handle_tlbl_end[]; |
1408 | extern u32 handle_tlbs[], handle_tlbs_end[]; | |
1409 | extern u32 handle_tlbm[], handle_tlbm_end[]; | |
1da177e4 | 1410 | |
3d8bfdd0 | 1411 | #ifdef CONFIG_MIPS_PGD_C0_CONTEXT |
6ba045f9 | 1412 | extern u32 tlbmiss_handler_setup_pgd[], tlbmiss_handler_setup_pgd_end[]; |
3d8bfdd0 | 1413 | |
078a55fc | 1414 | static void build_r4000_setup_pgd(void) |
3d8bfdd0 DD |
1415 | { |
1416 | const int a0 = 4; | |
1417 | const int a1 = 5; | |
38a997a7 | 1418 | u32 *p = tlbmiss_handler_setup_pgd; |
6ba045f9 J |
1419 | const int tlbmiss_handler_setup_pgd_size = |
1420 | tlbmiss_handler_setup_pgd_end - tlbmiss_handler_setup_pgd; | |
3d8bfdd0 DD |
1421 | struct uasm_label *l = labels; |
1422 | struct uasm_reloc *r = relocs; | |
1423 | ||
6ba045f9 J |
1424 | memset(tlbmiss_handler_setup_pgd, 0, tlbmiss_handler_setup_pgd_size * |
1425 | sizeof(tlbmiss_handler_setup_pgd[0])); | |
3d8bfdd0 DD |
1426 | memset(labels, 0, sizeof(labels)); |
1427 | memset(relocs, 0, sizeof(relocs)); | |
1428 | ||
1429 | pgd_reg = allocate_kscratch(); | |
1430 | ||
1431 | if (pgd_reg == -1) { | |
1432 | /* PGD << 11 in c0_Context */ | |
1433 | /* | |
1434 | * If it is a ckseg0 address, convert to a physical | |
1435 | * address. Shifting right by 29 and adding 4 will | |
1436 | * result in zero for these addresses. | |
1437 | * | |
1438 | */ | |
1439 | UASM_i_SRA(&p, a1, a0, 29); | |
1440 | UASM_i_ADDIU(&p, a1, a1, 4); | |
1441 | uasm_il_bnez(&p, &r, a1, label_tlbl_goaround1); | |
1442 | uasm_i_nop(&p); | |
1443 | uasm_i_dinsm(&p, a0, 0, 29, 64 - 29); | |
1444 | uasm_l_tlbl_goaround1(&l, p); | |
1445 | UASM_i_SLL(&p, a0, a0, 11); | |
1446 | uasm_i_jr(&p, 31); | |
1447 | UASM_i_MTC0(&p, a0, C0_CONTEXT); | |
1448 | } else { | |
1449 | /* PGD in c0_KScratch */ | |
1450 | uasm_i_jr(&p, 31); | |
7777b939 | 1451 | UASM_i_MTC0(&p, a0, c0_kscratch(), pgd_reg); |
3d8bfdd0 | 1452 | } |
6ba045f9 J |
1453 | if (p >= tlbmiss_handler_setup_pgd_end) |
1454 | panic("tlbmiss_handler_setup_pgd space exceeded"); | |
1455 | ||
3d8bfdd0 | 1456 | uasm_resolve_relocs(relocs, labels); |
6ba045f9 J |
1457 | pr_debug("Wrote tlbmiss_handler_setup_pgd (%u instructions).\n", |
1458 | (unsigned int)(p - tlbmiss_handler_setup_pgd)); | |
3d8bfdd0 | 1459 | |
6ba045f9 J |
1460 | dump_handler("tlbmiss_handler", tlbmiss_handler_setup_pgd, |
1461 | tlbmiss_handler_setup_pgd_size); | |
3d8bfdd0 DD |
1462 | } |
1463 | #endif | |
1da177e4 | 1464 | |
078a55fc | 1465 | static void |
bd1437e4 | 1466 | iPTE_LW(u32 **p, unsigned int pte, unsigned int ptr) |
1da177e4 LT |
1467 | { |
1468 | #ifdef CONFIG_SMP | |
1469 | # ifdef CONFIG_64BIT_PHYS_ADDR | |
1470 | if (cpu_has_64bits) | |
e30ec452 | 1471 | uasm_i_lld(p, pte, 0, ptr); |
1da177e4 LT |
1472 | else |
1473 | # endif | |
e30ec452 | 1474 | UASM_i_LL(p, pte, 0, ptr); |
1da177e4 LT |
1475 | #else |
1476 | # ifdef CONFIG_64BIT_PHYS_ADDR | |
1477 | if (cpu_has_64bits) | |
e30ec452 | 1478 | uasm_i_ld(p, pte, 0, ptr); |
1da177e4 LT |
1479 | else |
1480 | # endif | |
e30ec452 | 1481 | UASM_i_LW(p, pte, 0, ptr); |
1da177e4 LT |
1482 | #endif |
1483 | } | |
1484 | ||
078a55fc | 1485 | static void |
e30ec452 | 1486 | iPTE_SW(u32 **p, struct uasm_reloc **r, unsigned int pte, unsigned int ptr, |
63b2d2f4 | 1487 | unsigned int mode) |
1da177e4 | 1488 | { |
63b2d2f4 TS |
1489 | #ifdef CONFIG_64BIT_PHYS_ADDR |
1490 | unsigned int hwmode = mode & (_PAGE_VALID | _PAGE_DIRTY); | |
1491 | #endif | |
1492 | ||
e30ec452 | 1493 | uasm_i_ori(p, pte, pte, mode); |
1da177e4 LT |
1494 | #ifdef CONFIG_SMP |
1495 | # ifdef CONFIG_64BIT_PHYS_ADDR | |
1496 | if (cpu_has_64bits) | |
e30ec452 | 1497 | uasm_i_scd(p, pte, 0, ptr); |
1da177e4 LT |
1498 | else |
1499 | # endif | |
e30ec452 | 1500 | UASM_i_SC(p, pte, 0, ptr); |
1da177e4 LT |
1501 | |
1502 | if (r10000_llsc_war()) | |
e30ec452 | 1503 | uasm_il_beqzl(p, r, pte, label_smp_pgtable_change); |
1da177e4 | 1504 | else |
e30ec452 | 1505 | uasm_il_beqz(p, r, pte, label_smp_pgtable_change); |
1da177e4 LT |
1506 | |
1507 | # ifdef CONFIG_64BIT_PHYS_ADDR | |
1508 | if (!cpu_has_64bits) { | |
e30ec452 TS |
1509 | /* no uasm_i_nop needed */ |
1510 | uasm_i_ll(p, pte, sizeof(pte_t) / 2, ptr); | |
1511 | uasm_i_ori(p, pte, pte, hwmode); | |
1512 | uasm_i_sc(p, pte, sizeof(pte_t) / 2, ptr); | |
1513 | uasm_il_beqz(p, r, pte, label_smp_pgtable_change); | |
1514 | /* no uasm_i_nop needed */ | |
1515 | uasm_i_lw(p, pte, 0, ptr); | |
1da177e4 | 1516 | } else |
e30ec452 | 1517 | uasm_i_nop(p); |
1da177e4 | 1518 | # else |
e30ec452 | 1519 | uasm_i_nop(p); |
1da177e4 LT |
1520 | # endif |
1521 | #else | |
1522 | # ifdef CONFIG_64BIT_PHYS_ADDR | |
1523 | if (cpu_has_64bits) | |
e30ec452 | 1524 | uasm_i_sd(p, pte, 0, ptr); |
1da177e4 LT |
1525 | else |
1526 | # endif | |
e30ec452 | 1527 | UASM_i_SW(p, pte, 0, ptr); |
1da177e4 LT |
1528 | |
1529 | # ifdef CONFIG_64BIT_PHYS_ADDR | |
1530 | if (!cpu_has_64bits) { | |
e30ec452 TS |
1531 | uasm_i_lw(p, pte, sizeof(pte_t) / 2, ptr); |
1532 | uasm_i_ori(p, pte, pte, hwmode); | |
1533 | uasm_i_sw(p, pte, sizeof(pte_t) / 2, ptr); | |
1534 | uasm_i_lw(p, pte, 0, ptr); | |
1da177e4 LT |
1535 | } |
1536 | # endif | |
1537 | #endif | |
1538 | } | |
1539 | ||
1540 | /* | |
1541 | * Check if PTE is present, if not then jump to LABEL. PTR points to | |
1542 | * the page table where this PTE is located, PTE will be re-loaded | |
1543 | * with it's original value. | |
1544 | */ | |
078a55fc | 1545 | static void |
bd1437e4 | 1546 | build_pte_present(u32 **p, struct uasm_reloc **r, |
bf28607f | 1547 | int pte, int ptr, int scratch, enum label_id lid) |
1da177e4 | 1548 | { |
bf28607f DD |
1549 | int t = scratch >= 0 ? scratch : pte; |
1550 | ||
05857c64 | 1551 | if (cpu_has_rixi) { |
cc33ae43 DD |
1552 | if (use_bbit_insns()) { |
1553 | uasm_il_bbit0(p, r, pte, ilog2(_PAGE_PRESENT), lid); | |
1554 | uasm_i_nop(p); | |
1555 | } else { | |
bf28607f DD |
1556 | uasm_i_andi(p, t, pte, _PAGE_PRESENT); |
1557 | uasm_il_beqz(p, r, t, lid); | |
1558 | if (pte == t) | |
1559 | /* You lose the SMP race :-(*/ | |
1560 | iPTE_LW(p, pte, ptr); | |
cc33ae43 | 1561 | } |
6dd9344c | 1562 | } else { |
bf28607f DD |
1563 | uasm_i_andi(p, t, pte, _PAGE_PRESENT | _PAGE_READ); |
1564 | uasm_i_xori(p, t, t, _PAGE_PRESENT | _PAGE_READ); | |
1565 | uasm_il_bnez(p, r, t, lid); | |
1566 | if (pte == t) | |
1567 | /* You lose the SMP race :-(*/ | |
1568 | iPTE_LW(p, pte, ptr); | |
6dd9344c | 1569 | } |
1da177e4 LT |
1570 | } |
1571 | ||
1572 | /* Make PTE valid, store result in PTR. */ | |
078a55fc | 1573 | static void |
e30ec452 | 1574 | build_make_valid(u32 **p, struct uasm_reloc **r, unsigned int pte, |
1da177e4 LT |
1575 | unsigned int ptr) |
1576 | { | |
63b2d2f4 TS |
1577 | unsigned int mode = _PAGE_VALID | _PAGE_ACCESSED; |
1578 | ||
1579 | iPTE_SW(p, r, pte, ptr, mode); | |
1da177e4 LT |
1580 | } |
1581 | ||
1582 | /* | |
1583 | * Check if PTE can be written to, if not branch to LABEL. Regardless | |
1584 | * restore PTE with value from PTR when done. | |
1585 | */ | |
078a55fc | 1586 | static void |
bd1437e4 | 1587 | build_pte_writable(u32 **p, struct uasm_reloc **r, |
bf28607f DD |
1588 | unsigned int pte, unsigned int ptr, int scratch, |
1589 | enum label_id lid) | |
1da177e4 | 1590 | { |
bf28607f DD |
1591 | int t = scratch >= 0 ? scratch : pte; |
1592 | ||
1593 | uasm_i_andi(p, t, pte, _PAGE_PRESENT | _PAGE_WRITE); | |
1594 | uasm_i_xori(p, t, t, _PAGE_PRESENT | _PAGE_WRITE); | |
1595 | uasm_il_bnez(p, r, t, lid); | |
1596 | if (pte == t) | |
1597 | /* You lose the SMP race :-(*/ | |
cc33ae43 | 1598 | iPTE_LW(p, pte, ptr); |
bf28607f DD |
1599 | else |
1600 | uasm_i_nop(p); | |
1da177e4 LT |
1601 | } |
1602 | ||
1603 | /* Make PTE writable, update software status bits as well, then store | |
1604 | * at PTR. | |
1605 | */ | |
078a55fc | 1606 | static void |
e30ec452 | 1607 | build_make_write(u32 **p, struct uasm_reloc **r, unsigned int pte, |
1da177e4 LT |
1608 | unsigned int ptr) |
1609 | { | |
63b2d2f4 TS |
1610 | unsigned int mode = (_PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID |
1611 | | _PAGE_DIRTY); | |
1612 | ||
1613 | iPTE_SW(p, r, pte, ptr, mode); | |
1da177e4 LT |
1614 | } |
1615 | ||
1616 | /* | |
1617 | * Check if PTE can be modified, if not branch to LABEL. Regardless | |
1618 | * restore PTE with value from PTR when done. | |
1619 | */ | |
078a55fc | 1620 | static void |
bd1437e4 | 1621 | build_pte_modifiable(u32 **p, struct uasm_reloc **r, |
bf28607f DD |
1622 | unsigned int pte, unsigned int ptr, int scratch, |
1623 | enum label_id lid) | |
1da177e4 | 1624 | { |
cc33ae43 DD |
1625 | if (use_bbit_insns()) { |
1626 | uasm_il_bbit0(p, r, pte, ilog2(_PAGE_WRITE), lid); | |
1627 | uasm_i_nop(p); | |
1628 | } else { | |
bf28607f DD |
1629 | int t = scratch >= 0 ? scratch : pte; |
1630 | uasm_i_andi(p, t, pte, _PAGE_WRITE); | |
1631 | uasm_il_beqz(p, r, t, lid); | |
1632 | if (pte == t) | |
1633 | /* You lose the SMP race :-(*/ | |
1634 | iPTE_LW(p, pte, ptr); | |
cc33ae43 | 1635 | } |
1da177e4 LT |
1636 | } |
1637 | ||
82622284 | 1638 | #ifndef CONFIG_MIPS_PGD_C0_CONTEXT |
3d8bfdd0 DD |
1639 | |
1640 | ||
1da177e4 LT |
1641 | /* |
1642 | * R3000 style TLB load/store/modify handlers. | |
1643 | */ | |
1644 | ||
fded2e50 MR |
1645 | /* |
1646 | * This places the pte into ENTRYLO0 and writes it with tlbwi. | |
1647 | * Then it returns. | |
1648 | */ | |
078a55fc | 1649 | static void |
fded2e50 | 1650 | build_r3000_pte_reload_tlbwi(u32 **p, unsigned int pte, unsigned int tmp) |
1da177e4 | 1651 | { |
e30ec452 TS |
1652 | uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */ |
1653 | uasm_i_mfc0(p, tmp, C0_EPC); /* cp0 delay */ | |
1654 | uasm_i_tlbwi(p); | |
1655 | uasm_i_jr(p, tmp); | |
1656 | uasm_i_rfe(p); /* branch delay */ | |
1da177e4 LT |
1657 | } |
1658 | ||
1659 | /* | |
fded2e50 MR |
1660 | * This places the pte into ENTRYLO0 and writes it with tlbwi |
1661 | * or tlbwr as appropriate. This is because the index register | |
1662 | * may have the probe fail bit set as a result of a trap on a | |
1663 | * kseg2 access, i.e. without refill. Then it returns. | |
1da177e4 | 1664 | */ |
078a55fc | 1665 | static void |
e30ec452 TS |
1666 | build_r3000_tlb_reload_write(u32 **p, struct uasm_label **l, |
1667 | struct uasm_reloc **r, unsigned int pte, | |
1668 | unsigned int tmp) | |
1669 | { | |
1670 | uasm_i_mfc0(p, tmp, C0_INDEX); | |
1671 | uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */ | |
1672 | uasm_il_bltz(p, r, tmp, label_r3000_write_probe_fail); /* cp0 delay */ | |
1673 | uasm_i_mfc0(p, tmp, C0_EPC); /* branch delay */ | |
1674 | uasm_i_tlbwi(p); /* cp0 delay */ | |
1675 | uasm_i_jr(p, tmp); | |
1676 | uasm_i_rfe(p); /* branch delay */ | |
1677 | uasm_l_r3000_write_probe_fail(l, *p); | |
1678 | uasm_i_tlbwr(p); /* cp0 delay */ | |
1679 | uasm_i_jr(p, tmp); | |
1680 | uasm_i_rfe(p); /* branch delay */ | |
1da177e4 LT |
1681 | } |
1682 | ||
078a55fc | 1683 | static void |
1da177e4 LT |
1684 | build_r3000_tlbchange_handler_head(u32 **p, unsigned int pte, |
1685 | unsigned int ptr) | |
1686 | { | |
1687 | long pgdc = (long)pgd_current; | |
1688 | ||
e30ec452 TS |
1689 | uasm_i_mfc0(p, pte, C0_BADVADDR); |
1690 | uasm_i_lui(p, ptr, uasm_rel_hi(pgdc)); /* cp0 delay */ | |
1691 | uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr); | |
1692 | uasm_i_srl(p, pte, pte, 22); /* load delay */ | |
1693 | uasm_i_sll(p, pte, pte, 2); | |
1694 | uasm_i_addu(p, ptr, ptr, pte); | |
1695 | uasm_i_mfc0(p, pte, C0_CONTEXT); | |
1696 | uasm_i_lw(p, ptr, 0, ptr); /* cp0 delay */ | |
1697 | uasm_i_andi(p, pte, pte, 0xffc); /* load delay */ | |
1698 | uasm_i_addu(p, ptr, ptr, pte); | |
1699 | uasm_i_lw(p, pte, 0, ptr); | |
1700 | uasm_i_tlbp(p); /* load delay */ | |
1da177e4 LT |
1701 | } |
1702 | ||
078a55fc | 1703 | static void build_r3000_tlb_load_handler(void) |
1da177e4 LT |
1704 | { |
1705 | u32 *p = handle_tlbl; | |
6ba045f9 | 1706 | const int handle_tlbl_size = handle_tlbl_end - handle_tlbl; |
e30ec452 TS |
1707 | struct uasm_label *l = labels; |
1708 | struct uasm_reloc *r = relocs; | |
1da177e4 | 1709 | |
6ba045f9 | 1710 | memset(handle_tlbl, 0, handle_tlbl_size * sizeof(handle_tlbl[0])); |
1da177e4 LT |
1711 | memset(labels, 0, sizeof(labels)); |
1712 | memset(relocs, 0, sizeof(relocs)); | |
1713 | ||
1714 | build_r3000_tlbchange_handler_head(&p, K0, K1); | |
bf28607f | 1715 | build_pte_present(&p, &r, K0, K1, -1, label_nopage_tlbl); |
e30ec452 | 1716 | uasm_i_nop(&p); /* load delay */ |
1da177e4 | 1717 | build_make_valid(&p, &r, K0, K1); |
fded2e50 | 1718 | build_r3000_tlb_reload_write(&p, &l, &r, K0, K1); |
1da177e4 | 1719 | |
e30ec452 TS |
1720 | uasm_l_nopage_tlbl(&l, p); |
1721 | uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff); | |
1722 | uasm_i_nop(&p); | |
1da177e4 | 1723 | |
6ba045f9 | 1724 | if (p >= handle_tlbl_end) |
1da177e4 LT |
1725 | panic("TLB load handler fastpath space exceeded"); |
1726 | ||
e30ec452 TS |
1727 | uasm_resolve_relocs(relocs, labels); |
1728 | pr_debug("Wrote TLB load handler fastpath (%u instructions).\n", | |
1729 | (unsigned int)(p - handle_tlbl)); | |
1da177e4 | 1730 | |
6ba045f9 | 1731 | dump_handler("r3000_tlb_load", handle_tlbl, handle_tlbl_size); |
1da177e4 LT |
1732 | } |
1733 | ||
078a55fc | 1734 | static void build_r3000_tlb_store_handler(void) |
1da177e4 LT |
1735 | { |
1736 | u32 *p = handle_tlbs; | |
6ba045f9 | 1737 | const int handle_tlbs_size = handle_tlbs_end - handle_tlbs; |
e30ec452 TS |
1738 | struct uasm_label *l = labels; |
1739 | struct uasm_reloc *r = relocs; | |
1da177e4 | 1740 | |
6ba045f9 | 1741 | memset(handle_tlbs, 0, handle_tlbs_size * sizeof(handle_tlbs[0])); |
1da177e4 LT |
1742 | memset(labels, 0, sizeof(labels)); |
1743 | memset(relocs, 0, sizeof(relocs)); | |
1744 | ||
1745 | build_r3000_tlbchange_handler_head(&p, K0, K1); | |
bf28607f | 1746 | build_pte_writable(&p, &r, K0, K1, -1, label_nopage_tlbs); |
e30ec452 | 1747 | uasm_i_nop(&p); /* load delay */ |
1da177e4 | 1748 | build_make_write(&p, &r, K0, K1); |
fded2e50 | 1749 | build_r3000_tlb_reload_write(&p, &l, &r, K0, K1); |
1da177e4 | 1750 | |
e30ec452 TS |
1751 | uasm_l_nopage_tlbs(&l, p); |
1752 | uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); | |
1753 | uasm_i_nop(&p); | |
1da177e4 | 1754 | |
afc813ae | 1755 | if (p >= handle_tlbs_end) |
1da177e4 LT |
1756 | panic("TLB store handler fastpath space exceeded"); |
1757 | ||
e30ec452 TS |
1758 | uasm_resolve_relocs(relocs, labels); |
1759 | pr_debug("Wrote TLB store handler fastpath (%u instructions).\n", | |
1760 | (unsigned int)(p - handle_tlbs)); | |
1da177e4 | 1761 | |
6ba045f9 | 1762 | dump_handler("r3000_tlb_store", handle_tlbs, handle_tlbs_size); |
1da177e4 LT |
1763 | } |
1764 | ||
078a55fc | 1765 | static void build_r3000_tlb_modify_handler(void) |
1da177e4 LT |
1766 | { |
1767 | u32 *p = handle_tlbm; | |
6ba045f9 | 1768 | const int handle_tlbm_size = handle_tlbm_end - handle_tlbm; |
e30ec452 TS |
1769 | struct uasm_label *l = labels; |
1770 | struct uasm_reloc *r = relocs; | |
1da177e4 | 1771 | |
6ba045f9 | 1772 | memset(handle_tlbm, 0, handle_tlbm_size * sizeof(handle_tlbm[0])); |
1da177e4 LT |
1773 | memset(labels, 0, sizeof(labels)); |
1774 | memset(relocs, 0, sizeof(relocs)); | |
1775 | ||
1776 | build_r3000_tlbchange_handler_head(&p, K0, K1); | |
d954ffe3 | 1777 | build_pte_modifiable(&p, &r, K0, K1, -1, label_nopage_tlbm); |
e30ec452 | 1778 | uasm_i_nop(&p); /* load delay */ |
1da177e4 | 1779 | build_make_write(&p, &r, K0, K1); |
fded2e50 | 1780 | build_r3000_pte_reload_tlbwi(&p, K0, K1); |
1da177e4 | 1781 | |
e30ec452 TS |
1782 | uasm_l_nopage_tlbm(&l, p); |
1783 | uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); | |
1784 | uasm_i_nop(&p); | |
1da177e4 | 1785 | |
6ba045f9 | 1786 | if (p >= handle_tlbm_end) |
1da177e4 LT |
1787 | panic("TLB modify handler fastpath space exceeded"); |
1788 | ||
e30ec452 TS |
1789 | uasm_resolve_relocs(relocs, labels); |
1790 | pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n", | |
1791 | (unsigned int)(p - handle_tlbm)); | |
1da177e4 | 1792 | |
6ba045f9 | 1793 | dump_handler("r3000_tlb_modify", handle_tlbm, handle_tlbm_size); |
1da177e4 | 1794 | } |
82622284 | 1795 | #endif /* CONFIG_MIPS_PGD_C0_CONTEXT */ |
1da177e4 LT |
1796 | |
1797 | /* | |
1798 | * R4000 style TLB load/store/modify handlers. | |
1799 | */ | |
078a55fc | 1800 | static struct work_registers |
e30ec452 | 1801 | build_r4000_tlbchange_handler_head(u32 **p, struct uasm_label **l, |
bf28607f | 1802 | struct uasm_reloc **r) |
1da177e4 | 1803 | { |
bf28607f DD |
1804 | struct work_registers wr = build_get_work_registers(p); |
1805 | ||
875d43e7 | 1806 | #ifdef CONFIG_64BIT |
bf28607f | 1807 | build_get_pmde64(p, l, r, wr.r1, wr.r2); /* get pmd in ptr */ |
1da177e4 | 1808 | #else |
bf28607f | 1809 | build_get_pgde32(p, wr.r1, wr.r2); /* get pgd in ptr */ |
1da177e4 LT |
1810 | #endif |
1811 | ||
aa1762f4 | 1812 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
fd062c84 DD |
1813 | /* |
1814 | * For huge tlb entries, pmd doesn't contain an address but | |
1815 | * instead contains the tlb pte. Check the PAGE_HUGE bit and | |
1816 | * see if we need to jump to huge tlb processing. | |
1817 | */ | |
bf28607f | 1818 | build_is_huge_pte(p, r, wr.r1, wr.r2, label_tlb_huge_update); |
fd062c84 DD |
1819 | #endif |
1820 | ||
bf28607f DD |
1821 | UASM_i_MFC0(p, wr.r1, C0_BADVADDR); |
1822 | UASM_i_LW(p, wr.r2, 0, wr.r2); | |
1823 | UASM_i_SRL(p, wr.r1, wr.r1, PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2); | |
1824 | uasm_i_andi(p, wr.r1, wr.r1, (PTRS_PER_PTE - 1) << PTE_T_LOG2); | |
1825 | UASM_i_ADDU(p, wr.r2, wr.r2, wr.r1); | |
1da177e4 LT |
1826 | |
1827 | #ifdef CONFIG_SMP | |
e30ec452 TS |
1828 | uasm_l_smp_pgtable_change(l, *p); |
1829 | #endif | |
bf28607f | 1830 | iPTE_LW(p, wr.r1, wr.r2); /* get even pte */ |
8df5beac MR |
1831 | if (!m4kc_tlbp_war()) |
1832 | build_tlb_probe_entry(p); | |
bf28607f | 1833 | return wr; |
1da177e4 LT |
1834 | } |
1835 | ||
078a55fc | 1836 | static void |
e30ec452 TS |
1837 | build_r4000_tlbchange_handler_tail(u32 **p, struct uasm_label **l, |
1838 | struct uasm_reloc **r, unsigned int tmp, | |
1da177e4 LT |
1839 | unsigned int ptr) |
1840 | { | |
e30ec452 TS |
1841 | uasm_i_ori(p, ptr, ptr, sizeof(pte_t)); |
1842 | uasm_i_xori(p, ptr, ptr, sizeof(pte_t)); | |
1da177e4 LT |
1843 | build_update_entries(p, tmp, ptr); |
1844 | build_tlb_write_entry(p, l, r, tlb_indexed); | |
e30ec452 | 1845 | uasm_l_leave(l, *p); |
bf28607f | 1846 | build_restore_work_registers(p); |
e30ec452 | 1847 | uasm_i_eret(p); /* return from trap */ |
1da177e4 | 1848 | |
875d43e7 | 1849 | #ifdef CONFIG_64BIT |
1ec56329 | 1850 | build_get_pgd_vmalloc64(p, l, r, tmp, ptr, not_refill); |
1da177e4 LT |
1851 | #endif |
1852 | } | |
1853 | ||
078a55fc | 1854 | static void build_r4000_tlb_load_handler(void) |
1da177e4 LT |
1855 | { |
1856 | u32 *p = handle_tlbl; | |
6ba045f9 | 1857 | const int handle_tlbl_size = handle_tlbl_end - handle_tlbl; |
e30ec452 TS |
1858 | struct uasm_label *l = labels; |
1859 | struct uasm_reloc *r = relocs; | |
bf28607f | 1860 | struct work_registers wr; |
1da177e4 | 1861 | |
6ba045f9 | 1862 | memset(handle_tlbl, 0, handle_tlbl_size * sizeof(handle_tlbl[0])); |
1da177e4 LT |
1863 | memset(labels, 0, sizeof(labels)); |
1864 | memset(relocs, 0, sizeof(relocs)); | |
1865 | ||
1866 | if (bcm1250_m3_war()) { | |
3d45285d RB |
1867 | unsigned int segbits = 44; |
1868 | ||
1869 | uasm_i_dmfc0(&p, K0, C0_BADVADDR); | |
1870 | uasm_i_dmfc0(&p, K1, C0_ENTRYHI); | |
e30ec452 | 1871 | uasm_i_xor(&p, K0, K0, K1); |
3be6022c DD |
1872 | uasm_i_dsrl_safe(&p, K1, K0, 62); |
1873 | uasm_i_dsrl_safe(&p, K0, K0, 12 + 1); | |
1874 | uasm_i_dsll_safe(&p, K0, K0, 64 + 12 + 1 - segbits); | |
3d45285d | 1875 | uasm_i_or(&p, K0, K0, K1); |
e30ec452 TS |
1876 | uasm_il_bnez(&p, &r, K0, label_leave); |
1877 | /* No need for uasm_i_nop */ | |
1da177e4 LT |
1878 | } |
1879 | ||
bf28607f DD |
1880 | wr = build_r4000_tlbchange_handler_head(&p, &l, &r); |
1881 | build_pte_present(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbl); | |
8df5beac MR |
1882 | if (m4kc_tlbp_war()) |
1883 | build_tlb_probe_entry(&p); | |
6dd9344c | 1884 | |
05857c64 | 1885 | if (cpu_has_rixi) { |
6dd9344c DD |
1886 | /* |
1887 | * If the page is not _PAGE_VALID, RI or XI could not | |
1888 | * have triggered it. Skip the expensive test.. | |
1889 | */ | |
cc33ae43 | 1890 | if (use_bbit_insns()) { |
bf28607f | 1891 | uasm_il_bbit0(&p, &r, wr.r1, ilog2(_PAGE_VALID), |
cc33ae43 DD |
1892 | label_tlbl_goaround1); |
1893 | } else { | |
bf28607f DD |
1894 | uasm_i_andi(&p, wr.r3, wr.r1, _PAGE_VALID); |
1895 | uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround1); | |
cc33ae43 | 1896 | } |
6dd9344c DD |
1897 | uasm_i_nop(&p); |
1898 | ||
1899 | uasm_i_tlbr(&p); | |
73acc7df RB |
1900 | |
1901 | switch (current_cpu_type()) { | |
1902 | default: | |
1903 | if (cpu_has_mips_r2) { | |
1904 | uasm_i_ehb(&p); | |
1905 | ||
1906 | case CPU_CAVIUM_OCTEON: | |
1907 | case CPU_CAVIUM_OCTEON_PLUS: | |
1908 | case CPU_CAVIUM_OCTEON2: | |
1909 | break; | |
1910 | } | |
1911 | } | |
1912 | ||
6dd9344c | 1913 | /* Examine entrylo 0 or 1 based on ptr. */ |
cc33ae43 | 1914 | if (use_bbit_insns()) { |
bf28607f | 1915 | uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8); |
cc33ae43 | 1916 | } else { |
bf28607f DD |
1917 | uasm_i_andi(&p, wr.r3, wr.r2, sizeof(pte_t)); |
1918 | uasm_i_beqz(&p, wr.r3, 8); | |
cc33ae43 | 1919 | } |
bf28607f DD |
1920 | /* load it in the delay slot*/ |
1921 | UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO0); | |
1922 | /* load it if ptr is odd */ | |
1923 | UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO1); | |
6dd9344c | 1924 | /* |
bf28607f | 1925 | * If the entryLo (now in wr.r3) is valid (bit 1), RI or |
6dd9344c DD |
1926 | * XI must have triggered it. |
1927 | */ | |
cc33ae43 | 1928 | if (use_bbit_insns()) { |
bf28607f DD |
1929 | uasm_il_bbit1(&p, &r, wr.r3, 1, label_nopage_tlbl); |
1930 | uasm_i_nop(&p); | |
cc33ae43 DD |
1931 | uasm_l_tlbl_goaround1(&l, p); |
1932 | } else { | |
bf28607f DD |
1933 | uasm_i_andi(&p, wr.r3, wr.r3, 2); |
1934 | uasm_il_bnez(&p, &r, wr.r3, label_nopage_tlbl); | |
1935 | uasm_i_nop(&p); | |
cc33ae43 | 1936 | } |
bf28607f | 1937 | uasm_l_tlbl_goaround1(&l, p); |
6dd9344c | 1938 | } |
bf28607f DD |
1939 | build_make_valid(&p, &r, wr.r1, wr.r2); |
1940 | build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2); | |
1da177e4 | 1941 | |
aa1762f4 | 1942 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
fd062c84 DD |
1943 | /* |
1944 | * This is the entry point when build_r4000_tlbchange_handler_head | |
1945 | * spots a huge page. | |
1946 | */ | |
1947 | uasm_l_tlb_huge_update(&l, p); | |
bf28607f DD |
1948 | iPTE_LW(&p, wr.r1, wr.r2); |
1949 | build_pte_present(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbl); | |
fd062c84 | 1950 | build_tlb_probe_entry(&p); |
6dd9344c | 1951 | |
05857c64 | 1952 | if (cpu_has_rixi) { |
6dd9344c DD |
1953 | /* |
1954 | * If the page is not _PAGE_VALID, RI or XI could not | |
1955 | * have triggered it. Skip the expensive test.. | |
1956 | */ | |
cc33ae43 | 1957 | if (use_bbit_insns()) { |
bf28607f | 1958 | uasm_il_bbit0(&p, &r, wr.r1, ilog2(_PAGE_VALID), |
cc33ae43 DD |
1959 | label_tlbl_goaround2); |
1960 | } else { | |
bf28607f DD |
1961 | uasm_i_andi(&p, wr.r3, wr.r1, _PAGE_VALID); |
1962 | uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround2); | |
cc33ae43 | 1963 | } |
6dd9344c DD |
1964 | uasm_i_nop(&p); |
1965 | ||
1966 | uasm_i_tlbr(&p); | |
73acc7df RB |
1967 | |
1968 | switch (current_cpu_type()) { | |
1969 | default: | |
1970 | if (cpu_has_mips_r2) { | |
1971 | uasm_i_ehb(&p); | |
1972 | ||
1973 | case CPU_CAVIUM_OCTEON: | |
1974 | case CPU_CAVIUM_OCTEON_PLUS: | |
1975 | case CPU_CAVIUM_OCTEON2: | |
1976 | break; | |
1977 | } | |
1978 | } | |
1979 | ||
6dd9344c | 1980 | /* Examine entrylo 0 or 1 based on ptr. */ |
cc33ae43 | 1981 | if (use_bbit_insns()) { |
bf28607f | 1982 | uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8); |
cc33ae43 | 1983 | } else { |
bf28607f DD |
1984 | uasm_i_andi(&p, wr.r3, wr.r2, sizeof(pte_t)); |
1985 | uasm_i_beqz(&p, wr.r3, 8); | |
cc33ae43 | 1986 | } |
bf28607f DD |
1987 | /* load it in the delay slot*/ |
1988 | UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO0); | |
1989 | /* load it if ptr is odd */ | |
1990 | UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO1); | |
6dd9344c | 1991 | /* |
bf28607f | 1992 | * If the entryLo (now in wr.r3) is valid (bit 1), RI or |
6dd9344c DD |
1993 | * XI must have triggered it. |
1994 | */ | |
cc33ae43 | 1995 | if (use_bbit_insns()) { |
bf28607f | 1996 | uasm_il_bbit0(&p, &r, wr.r3, 1, label_tlbl_goaround2); |
cc33ae43 | 1997 | } else { |
bf28607f DD |
1998 | uasm_i_andi(&p, wr.r3, wr.r3, 2); |
1999 | uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround2); | |
cc33ae43 | 2000 | } |
0f4ccbc8 DD |
2001 | if (PM_DEFAULT_MASK == 0) |
2002 | uasm_i_nop(&p); | |
6dd9344c DD |
2003 | /* |
2004 | * We clobbered C0_PAGEMASK, restore it. On the other branch | |
2005 | * it is restored in build_huge_tlb_write_entry. | |
2006 | */ | |
bf28607f | 2007 | build_restore_pagemask(&p, &r, wr.r3, label_nopage_tlbl, 0); |
6dd9344c DD |
2008 | |
2009 | uasm_l_tlbl_goaround2(&l, p); | |
2010 | } | |
bf28607f DD |
2011 | uasm_i_ori(&p, wr.r1, wr.r1, (_PAGE_ACCESSED | _PAGE_VALID)); |
2012 | build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2); | |
fd062c84 DD |
2013 | #endif |
2014 | ||
e30ec452 | 2015 | uasm_l_nopage_tlbl(&l, p); |
bf28607f | 2016 | build_restore_work_registers(&p); |
2a0b24f5 SH |
2017 | #ifdef CONFIG_CPU_MICROMIPS |
2018 | if ((unsigned long)tlb_do_page_fault_0 & 1) { | |
2019 | uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_0)); | |
2020 | uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_0)); | |
2021 | uasm_i_jr(&p, K0); | |
2022 | } else | |
2023 | #endif | |
e30ec452 TS |
2024 | uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff); |
2025 | uasm_i_nop(&p); | |
1da177e4 | 2026 | |
6ba045f9 | 2027 | if (p >= handle_tlbl_end) |
1da177e4 LT |
2028 | panic("TLB load handler fastpath space exceeded"); |
2029 | ||
e30ec452 TS |
2030 | uasm_resolve_relocs(relocs, labels); |
2031 | pr_debug("Wrote TLB load handler fastpath (%u instructions).\n", | |
2032 | (unsigned int)(p - handle_tlbl)); | |
1da177e4 | 2033 | |
6ba045f9 | 2034 | dump_handler("r4000_tlb_load", handle_tlbl, handle_tlbl_size); |
1da177e4 LT |
2035 | } |
2036 | ||
078a55fc | 2037 | static void build_r4000_tlb_store_handler(void) |
1da177e4 LT |
2038 | { |
2039 | u32 *p = handle_tlbs; | |
6ba045f9 | 2040 | const int handle_tlbs_size = handle_tlbs_end - handle_tlbs; |
e30ec452 TS |
2041 | struct uasm_label *l = labels; |
2042 | struct uasm_reloc *r = relocs; | |
bf28607f | 2043 | struct work_registers wr; |
1da177e4 | 2044 | |
6ba045f9 | 2045 | memset(handle_tlbs, 0, handle_tlbs_size * sizeof(handle_tlbs[0])); |
1da177e4 LT |
2046 | memset(labels, 0, sizeof(labels)); |
2047 | memset(relocs, 0, sizeof(relocs)); | |
2048 | ||
bf28607f DD |
2049 | wr = build_r4000_tlbchange_handler_head(&p, &l, &r); |
2050 | build_pte_writable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbs); | |
8df5beac MR |
2051 | if (m4kc_tlbp_war()) |
2052 | build_tlb_probe_entry(&p); | |
bf28607f DD |
2053 | build_make_write(&p, &r, wr.r1, wr.r2); |
2054 | build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2); | |
1da177e4 | 2055 | |
aa1762f4 | 2056 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
fd062c84 DD |
2057 | /* |
2058 | * This is the entry point when | |
2059 | * build_r4000_tlbchange_handler_head spots a huge page. | |
2060 | */ | |
2061 | uasm_l_tlb_huge_update(&l, p); | |
bf28607f DD |
2062 | iPTE_LW(&p, wr.r1, wr.r2); |
2063 | build_pte_writable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbs); | |
fd062c84 | 2064 | build_tlb_probe_entry(&p); |
bf28607f | 2065 | uasm_i_ori(&p, wr.r1, wr.r1, |
fd062c84 | 2066 | _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY); |
bf28607f | 2067 | build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2); |
fd062c84 DD |
2068 | #endif |
2069 | ||
e30ec452 | 2070 | uasm_l_nopage_tlbs(&l, p); |
bf28607f | 2071 | build_restore_work_registers(&p); |
2a0b24f5 SH |
2072 | #ifdef CONFIG_CPU_MICROMIPS |
2073 | if ((unsigned long)tlb_do_page_fault_1 & 1) { | |
2074 | uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_1)); | |
2075 | uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_1)); | |
2076 | uasm_i_jr(&p, K0); | |
2077 | } else | |
2078 | #endif | |
e30ec452 TS |
2079 | uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); |
2080 | uasm_i_nop(&p); | |
1da177e4 | 2081 | |
6ba045f9 | 2082 | if (p >= handle_tlbs_end) |
1da177e4 LT |
2083 | panic("TLB store handler fastpath space exceeded"); |
2084 | ||
e30ec452 TS |
2085 | uasm_resolve_relocs(relocs, labels); |
2086 | pr_debug("Wrote TLB store handler fastpath (%u instructions).\n", | |
2087 | (unsigned int)(p - handle_tlbs)); | |
1da177e4 | 2088 | |
6ba045f9 | 2089 | dump_handler("r4000_tlb_store", handle_tlbs, handle_tlbs_size); |
1da177e4 LT |
2090 | } |
2091 | ||
078a55fc | 2092 | static void build_r4000_tlb_modify_handler(void) |
1da177e4 LT |
2093 | { |
2094 | u32 *p = handle_tlbm; | |
6ba045f9 | 2095 | const int handle_tlbm_size = handle_tlbm_end - handle_tlbm; |
e30ec452 TS |
2096 | struct uasm_label *l = labels; |
2097 | struct uasm_reloc *r = relocs; | |
bf28607f | 2098 | struct work_registers wr; |
1da177e4 | 2099 | |
6ba045f9 | 2100 | memset(handle_tlbm, 0, handle_tlbm_size * sizeof(handle_tlbm[0])); |
1da177e4 LT |
2101 | memset(labels, 0, sizeof(labels)); |
2102 | memset(relocs, 0, sizeof(relocs)); | |
2103 | ||
bf28607f DD |
2104 | wr = build_r4000_tlbchange_handler_head(&p, &l, &r); |
2105 | build_pte_modifiable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbm); | |
8df5beac MR |
2106 | if (m4kc_tlbp_war()) |
2107 | build_tlb_probe_entry(&p); | |
1da177e4 | 2108 | /* Present and writable bits set, set accessed and dirty bits. */ |
bf28607f DD |
2109 | build_make_write(&p, &r, wr.r1, wr.r2); |
2110 | build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2); | |
1da177e4 | 2111 | |
aa1762f4 | 2112 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
fd062c84 DD |
2113 | /* |
2114 | * This is the entry point when | |
2115 | * build_r4000_tlbchange_handler_head spots a huge page. | |
2116 | */ | |
2117 | uasm_l_tlb_huge_update(&l, p); | |
bf28607f DD |
2118 | iPTE_LW(&p, wr.r1, wr.r2); |
2119 | build_pte_modifiable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbm); | |
fd062c84 | 2120 | build_tlb_probe_entry(&p); |
bf28607f | 2121 | uasm_i_ori(&p, wr.r1, wr.r1, |
fd062c84 | 2122 | _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY); |
bf28607f | 2123 | build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2); |
fd062c84 DD |
2124 | #endif |
2125 | ||
e30ec452 | 2126 | uasm_l_nopage_tlbm(&l, p); |
bf28607f | 2127 | build_restore_work_registers(&p); |
2a0b24f5 SH |
2128 | #ifdef CONFIG_CPU_MICROMIPS |
2129 | if ((unsigned long)tlb_do_page_fault_1 & 1) { | |
2130 | uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_1)); | |
2131 | uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_1)); | |
2132 | uasm_i_jr(&p, K0); | |
2133 | } else | |
2134 | #endif | |
e30ec452 TS |
2135 | uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); |
2136 | uasm_i_nop(&p); | |
1da177e4 | 2137 | |
6ba045f9 | 2138 | if (p >= handle_tlbm_end) |
1da177e4 LT |
2139 | panic("TLB modify handler fastpath space exceeded"); |
2140 | ||
e30ec452 TS |
2141 | uasm_resolve_relocs(relocs, labels); |
2142 | pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n", | |
2143 | (unsigned int)(p - handle_tlbm)); | |
115f2a44 | 2144 | |
6ba045f9 | 2145 | dump_handler("r4000_tlb_modify", handle_tlbm, handle_tlbm_size); |
1da177e4 LT |
2146 | } |
2147 | ||
078a55fc | 2148 | static void flush_tlb_handlers(void) |
a3d9086b JG |
2149 | { |
2150 | local_flush_icache_range((unsigned long)handle_tlbl, | |
6ac5310e | 2151 | (unsigned long)handle_tlbl_end); |
a3d9086b | 2152 | local_flush_icache_range((unsigned long)handle_tlbs, |
6ac5310e | 2153 | (unsigned long)handle_tlbs_end); |
a3d9086b | 2154 | local_flush_icache_range((unsigned long)handle_tlbm, |
6ac5310e | 2155 | (unsigned long)handle_tlbm_end); |
a3d9086b | 2156 | #ifdef CONFIG_MIPS_PGD_C0_CONTEXT |
6ac5310e RB |
2157 | local_flush_icache_range((unsigned long)tlbmiss_handler_setup_pgd, |
2158 | (unsigned long)tlbmiss_handler_setup_pgd_end); | |
a3d9086b JG |
2159 | #endif |
2160 | } | |
2161 | ||
078a55fc | 2162 | void build_tlb_refill_handler(void) |
1da177e4 LT |
2163 | { |
2164 | /* | |
2165 | * The refill handler is generated per-CPU, multi-node systems | |
2166 | * may have local storage for it. The other handlers are only | |
2167 | * needed once. | |
2168 | */ | |
2169 | static int run_once = 0; | |
2170 | ||
a2c763e0 RB |
2171 | output_pgtable_bits_defines(); |
2172 | ||
1ec56329 DD |
2173 | #ifdef CONFIG_64BIT |
2174 | check_for_high_segbits = current_cpu_data.vmbits > (PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3); | |
2175 | #endif | |
2176 | ||
10cc3529 | 2177 | switch (current_cpu_type()) { |
1da177e4 LT |
2178 | case CPU_R2000: |
2179 | case CPU_R3000: | |
2180 | case CPU_R3000A: | |
2181 | case CPU_R3081E: | |
2182 | case CPU_TX3912: | |
2183 | case CPU_TX3922: | |
2184 | case CPU_TX3927: | |
82622284 | 2185 | #ifndef CONFIG_MIPS_PGD_C0_CONTEXT |
8759934e HC |
2186 | if (cpu_has_local_ebase) |
2187 | build_r3000_tlb_refill_handler(); | |
1da177e4 | 2188 | if (!run_once) { |
8759934e HC |
2189 | if (!cpu_has_local_ebase) |
2190 | build_r3000_tlb_refill_handler(); | |
1da177e4 LT |
2191 | build_r3000_tlb_load_handler(); |
2192 | build_r3000_tlb_store_handler(); | |
2193 | build_r3000_tlb_modify_handler(); | |
a3d9086b | 2194 | flush_tlb_handlers(); |
1da177e4 LT |
2195 | run_once++; |
2196 | } | |
82622284 DD |
2197 | #else |
2198 | panic("No R3000 TLB refill handler"); | |
2199 | #endif | |
1da177e4 LT |
2200 | break; |
2201 | ||
2202 | case CPU_R6000: | |
2203 | case CPU_R6000A: | |
2204 | panic("No R6000 TLB refill handler yet"); | |
2205 | break; | |
2206 | ||
2207 | case CPU_R8000: | |
2208 | panic("No R8000 TLB refill handler yet"); | |
2209 | break; | |
2210 | ||
2211 | default: | |
1da177e4 | 2212 | if (!run_once) { |
bf28607f | 2213 | scratch_reg = allocate_kscratch(); |
3d8bfdd0 DD |
2214 | #ifdef CONFIG_MIPS_PGD_C0_CONTEXT |
2215 | build_r4000_setup_pgd(); | |
2216 | #endif | |
1da177e4 LT |
2217 | build_r4000_tlb_load_handler(); |
2218 | build_r4000_tlb_store_handler(); | |
2219 | build_r4000_tlb_modify_handler(); | |
8759934e HC |
2220 | if (!cpu_has_local_ebase) |
2221 | build_r4000_tlb_refill_handler(); | |
a3d9086b | 2222 | flush_tlb_handlers(); |
1da177e4 LT |
2223 | run_once++; |
2224 | } | |
8759934e HC |
2225 | if (cpu_has_local_ebase) |
2226 | build_r4000_tlb_refill_handler(); | |
1da177e4 LT |
2227 | } |
2228 | } |