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1da177e4 LT |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * Synthesize TLB refill handlers at runtime. | |
7 | * | |
115f2a44 | 8 | * Copyright (C) 2004,2005,2006 by Thiemo Seufer |
fded2e50 | 9 | * Copyright (C) 2005 Maciej W. Rozycki |
41c594ab RB |
10 | * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org) |
11 | * | |
12 | * ... and the days got worse and worse and now you see | |
13 | * I've gone completly out of my mind. | |
14 | * | |
15 | * They're coming to take me a away haha | |
16 | * they're coming to take me a away hoho hihi haha | |
17 | * to the funny farm where code is beautiful all the time ... | |
18 | * | |
19 | * (Condolences to Napoleon XIV) | |
1da177e4 LT |
20 | */ |
21 | ||
22 | #include <stdarg.h> | |
23 | ||
1da177e4 LT |
24 | #include <linux/mm.h> |
25 | #include <linux/kernel.h> | |
26 | #include <linux/types.h> | |
27 | #include <linux/string.h> | |
28 | #include <linux/init.h> | |
29 | ||
30 | #include <asm/pgtable.h> | |
31 | #include <asm/cacheflush.h> | |
32 | #include <asm/mmu_context.h> | |
33 | #include <asm/inst.h> | |
34 | #include <asm/elf.h> | |
35 | #include <asm/smp.h> | |
36 | #include <asm/war.h> | |
37 | ||
1da177e4 LT |
38 | static __init int __attribute__((unused)) r45k_bvahwbug(void) |
39 | { | |
40 | /* XXX: We should probe for the presence of this bug, but we don't. */ | |
41 | return 0; | |
42 | } | |
43 | ||
44 | static __init int __attribute__((unused)) r4k_250MHZhwbug(void) | |
45 | { | |
46 | /* XXX: We should probe for the presence of this bug, but we don't. */ | |
47 | return 0; | |
48 | } | |
49 | ||
50 | static __init int __attribute__((unused)) bcm1250_m3_war(void) | |
51 | { | |
52 | return BCM1250_M3_WAR; | |
53 | } | |
54 | ||
55 | static __init int __attribute__((unused)) r10000_llsc_war(void) | |
56 | { | |
57 | return R10000_LLSC_WAR; | |
58 | } | |
59 | ||
60 | /* | |
61 | * A little micro-assembler, intended for TLB refill handler | |
62 | * synthesizing. It is intentionally kept simple, does only support | |
63 | * a subset of instructions, and does not try to hide pipeline effects | |
64 | * like branch delay slots. | |
65 | */ | |
66 | ||
67 | enum fields | |
68 | { | |
69 | RS = 0x001, | |
70 | RT = 0x002, | |
71 | RD = 0x004, | |
72 | RE = 0x008, | |
73 | SIMM = 0x010, | |
74 | UIMM = 0x020, | |
75 | BIMM = 0x040, | |
76 | JIMM = 0x080, | |
77 | FUNC = 0x100, | |
41c594ab | 78 | SET = 0x200 |
1da177e4 LT |
79 | }; |
80 | ||
81 | #define OP_MASK 0x2f | |
82 | #define OP_SH 26 | |
83 | #define RS_MASK 0x1f | |
84 | #define RS_SH 21 | |
85 | #define RT_MASK 0x1f | |
86 | #define RT_SH 16 | |
87 | #define RD_MASK 0x1f | |
88 | #define RD_SH 11 | |
89 | #define RE_MASK 0x1f | |
90 | #define RE_SH 6 | |
91 | #define IMM_MASK 0xffff | |
92 | #define IMM_SH 0 | |
93 | #define JIMM_MASK 0x3ffffff | |
94 | #define JIMM_SH 0 | |
95 | #define FUNC_MASK 0x2f | |
96 | #define FUNC_SH 0 | |
41c594ab RB |
97 | #define SET_MASK 0x7 |
98 | #define SET_SH 0 | |
1da177e4 LT |
99 | |
100 | enum opcode { | |
101 | insn_invalid, | |
102 | insn_addu, insn_addiu, insn_and, insn_andi, insn_beq, | |
103 | insn_beql, insn_bgez, insn_bgezl, insn_bltz, insn_bltzl, | |
104 | insn_bne, insn_daddu, insn_daddiu, insn_dmfc0, insn_dmtc0, | |
1b3a6e97 | 105 | insn_dsll, insn_dsll32, insn_dsra, insn_dsrl, |
1da177e4 LT |
106 | insn_dsubu, insn_eret, insn_j, insn_jal, insn_jr, insn_ld, |
107 | insn_ll, insn_lld, insn_lui, insn_lw, insn_mfc0, insn_mtc0, | |
108 | insn_ori, insn_rfe, insn_sc, insn_scd, insn_sd, insn_sll, | |
109 | insn_sra, insn_srl, insn_subu, insn_sw, insn_tlbp, insn_tlbwi, | |
110 | insn_tlbwr, insn_xor, insn_xori | |
111 | }; | |
112 | ||
113 | struct insn { | |
114 | enum opcode opcode; | |
115 | u32 match; | |
116 | enum fields fields; | |
117 | }; | |
118 | ||
119 | /* This macro sets the non-variable bits of an instruction. */ | |
120 | #define M(a, b, c, d, e, f) \ | |
121 | ((a) << OP_SH \ | |
122 | | (b) << RS_SH \ | |
123 | | (c) << RT_SH \ | |
124 | | (d) << RD_SH \ | |
125 | | (e) << RE_SH \ | |
126 | | (f) << FUNC_SH) | |
127 | ||
128 | static __initdata struct insn insn_table[] = { | |
129 | { insn_addiu, M(addiu_op,0,0,0,0,0), RS | RT | SIMM }, | |
130 | { insn_addu, M(spec_op,0,0,0,0,addu_op), RS | RT | RD }, | |
131 | { insn_and, M(spec_op,0,0,0,0,and_op), RS | RT | RD }, | |
132 | { insn_andi, M(andi_op,0,0,0,0,0), RS | RT | UIMM }, | |
133 | { insn_beq, M(beq_op,0,0,0,0,0), RS | RT | BIMM }, | |
134 | { insn_beql, M(beql_op,0,0,0,0,0), RS | RT | BIMM }, | |
135 | { insn_bgez, M(bcond_op,0,bgez_op,0,0,0), RS | BIMM }, | |
136 | { insn_bgezl, M(bcond_op,0,bgezl_op,0,0,0), RS | BIMM }, | |
137 | { insn_bltz, M(bcond_op,0,bltz_op,0,0,0), RS | BIMM }, | |
138 | { insn_bltzl, M(bcond_op,0,bltzl_op,0,0,0), RS | BIMM }, | |
139 | { insn_bne, M(bne_op,0,0,0,0,0), RS | RT | BIMM }, | |
140 | { insn_daddiu, M(daddiu_op,0,0,0,0,0), RS | RT | SIMM }, | |
141 | { insn_daddu, M(spec_op,0,0,0,0,daddu_op), RS | RT | RD }, | |
41c594ab RB |
142 | { insn_dmfc0, M(cop0_op,dmfc_op,0,0,0,0), RT | RD | SET}, |
143 | { insn_dmtc0, M(cop0_op,dmtc_op,0,0,0,0), RT | RD | SET}, | |
1da177e4 LT |
144 | { insn_dsll, M(spec_op,0,0,0,0,dsll_op), RT | RD | RE }, |
145 | { insn_dsll32, M(spec_op,0,0,0,0,dsll32_op), RT | RD | RE }, | |
146 | { insn_dsra, M(spec_op,0,0,0,0,dsra_op), RT | RD | RE }, | |
147 | { insn_dsrl, M(spec_op,0,0,0,0,dsrl_op), RT | RD | RE }, | |
1da177e4 LT |
148 | { insn_dsubu, M(spec_op,0,0,0,0,dsubu_op), RS | RT | RD }, |
149 | { insn_eret, M(cop0_op,cop_op,0,0,0,eret_op), 0 }, | |
150 | { insn_j, M(j_op,0,0,0,0,0), JIMM }, | |
151 | { insn_jal, M(jal_op,0,0,0,0,0), JIMM }, | |
152 | { insn_jr, M(spec_op,0,0,0,0,jr_op), RS }, | |
153 | { insn_ld, M(ld_op,0,0,0,0,0), RS | RT | SIMM }, | |
154 | { insn_ll, M(ll_op,0,0,0,0,0), RS | RT | SIMM }, | |
155 | { insn_lld, M(lld_op,0,0,0,0,0), RS | RT | SIMM }, | |
156 | { insn_lui, M(lui_op,0,0,0,0,0), RT | SIMM }, | |
157 | { insn_lw, M(lw_op,0,0,0,0,0), RS | RT | SIMM }, | |
41c594ab RB |
158 | { insn_mfc0, M(cop0_op,mfc_op,0,0,0,0), RT | RD | SET}, |
159 | { insn_mtc0, M(cop0_op,mtc_op,0,0,0,0), RT | RD | SET}, | |
1da177e4 LT |
160 | { insn_ori, M(ori_op,0,0,0,0,0), RS | RT | UIMM }, |
161 | { insn_rfe, M(cop0_op,cop_op,0,0,0,rfe_op), 0 }, | |
162 | { insn_sc, M(sc_op,0,0,0,0,0), RS | RT | SIMM }, | |
163 | { insn_scd, M(scd_op,0,0,0,0,0), RS | RT | SIMM }, | |
164 | { insn_sd, M(sd_op,0,0,0,0,0), RS | RT | SIMM }, | |
165 | { insn_sll, M(spec_op,0,0,0,0,sll_op), RT | RD | RE }, | |
166 | { insn_sra, M(spec_op,0,0,0,0,sra_op), RT | RD | RE }, | |
167 | { insn_srl, M(spec_op,0,0,0,0,srl_op), RT | RD | RE }, | |
168 | { insn_subu, M(spec_op,0,0,0,0,subu_op), RS | RT | RD }, | |
169 | { insn_sw, M(sw_op,0,0,0,0,0), RS | RT | SIMM }, | |
170 | { insn_tlbp, M(cop0_op,cop_op,0,0,0,tlbp_op), 0 }, | |
171 | { insn_tlbwi, M(cop0_op,cop_op,0,0,0,tlbwi_op), 0 }, | |
172 | { insn_tlbwr, M(cop0_op,cop_op,0,0,0,tlbwr_op), 0 }, | |
173 | { insn_xor, M(spec_op,0,0,0,0,xor_op), RS | RT | RD }, | |
174 | { insn_xori, M(xori_op,0,0,0,0,0), RS | RT | UIMM }, | |
175 | { insn_invalid, 0, 0 } | |
176 | }; | |
177 | ||
178 | #undef M | |
179 | ||
180 | static __init u32 build_rs(u32 arg) | |
181 | { | |
182 | if (arg & ~RS_MASK) | |
183 | printk(KERN_WARNING "TLB synthesizer field overflow\n"); | |
184 | ||
185 | return (arg & RS_MASK) << RS_SH; | |
186 | } | |
187 | ||
188 | static __init u32 build_rt(u32 arg) | |
189 | { | |
190 | if (arg & ~RT_MASK) | |
191 | printk(KERN_WARNING "TLB synthesizer field overflow\n"); | |
192 | ||
193 | return (arg & RT_MASK) << RT_SH; | |
194 | } | |
195 | ||
196 | static __init u32 build_rd(u32 arg) | |
197 | { | |
198 | if (arg & ~RD_MASK) | |
199 | printk(KERN_WARNING "TLB synthesizer field overflow\n"); | |
200 | ||
201 | return (arg & RD_MASK) << RD_SH; | |
202 | } | |
203 | ||
204 | static __init u32 build_re(u32 arg) | |
205 | { | |
206 | if (arg & ~RE_MASK) | |
207 | printk(KERN_WARNING "TLB synthesizer field overflow\n"); | |
208 | ||
209 | return (arg & RE_MASK) << RE_SH; | |
210 | } | |
211 | ||
212 | static __init u32 build_simm(s32 arg) | |
213 | { | |
214 | if (arg > 0x7fff || arg < -0x8000) | |
215 | printk(KERN_WARNING "TLB synthesizer field overflow\n"); | |
216 | ||
217 | return arg & 0xffff; | |
218 | } | |
219 | ||
220 | static __init u32 build_uimm(u32 arg) | |
221 | { | |
222 | if (arg & ~IMM_MASK) | |
223 | printk(KERN_WARNING "TLB synthesizer field overflow\n"); | |
224 | ||
225 | return arg & IMM_MASK; | |
226 | } | |
227 | ||
228 | static __init u32 build_bimm(s32 arg) | |
229 | { | |
230 | if (arg > 0x1ffff || arg < -0x20000) | |
231 | printk(KERN_WARNING "TLB synthesizer field overflow\n"); | |
232 | ||
233 | if (arg & 0x3) | |
234 | printk(KERN_WARNING "Invalid TLB synthesizer branch target\n"); | |
235 | ||
236 | return ((arg < 0) ? (1 << 15) : 0) | ((arg >> 2) & 0x7fff); | |
237 | } | |
238 | ||
239 | static __init u32 build_jimm(u32 arg) | |
240 | { | |
241 | if (arg & ~((JIMM_MASK) << 2)) | |
242 | printk(KERN_WARNING "TLB synthesizer field overflow\n"); | |
243 | ||
244 | return (arg >> 2) & JIMM_MASK; | |
245 | } | |
246 | ||
247 | static __init u32 build_func(u32 arg) | |
248 | { | |
249 | if (arg & ~FUNC_MASK) | |
250 | printk(KERN_WARNING "TLB synthesizer field overflow\n"); | |
251 | ||
252 | return arg & FUNC_MASK; | |
253 | } | |
254 | ||
41c594ab RB |
255 | static __init u32 build_set(u32 arg) |
256 | { | |
257 | if (arg & ~SET_MASK) | |
258 | printk(KERN_WARNING "TLB synthesizer field overflow\n"); | |
259 | ||
260 | return arg & SET_MASK; | |
261 | } | |
262 | ||
1da177e4 LT |
263 | /* |
264 | * The order of opcode arguments is implicitly left to right, | |
265 | * starting with RS and ending with FUNC or IMM. | |
266 | */ | |
267 | static void __init build_insn(u32 **buf, enum opcode opc, ...) | |
268 | { | |
269 | struct insn *ip = NULL; | |
270 | unsigned int i; | |
271 | va_list ap; | |
272 | u32 op; | |
273 | ||
274 | for (i = 0; insn_table[i].opcode != insn_invalid; i++) | |
275 | if (insn_table[i].opcode == opc) { | |
276 | ip = &insn_table[i]; | |
277 | break; | |
278 | } | |
279 | ||
280 | if (!ip) | |
281 | panic("Unsupported TLB synthesizer instruction %d", opc); | |
282 | ||
283 | op = ip->match; | |
284 | va_start(ap, opc); | |
285 | if (ip->fields & RS) op |= build_rs(va_arg(ap, u32)); | |
286 | if (ip->fields & RT) op |= build_rt(va_arg(ap, u32)); | |
287 | if (ip->fields & RD) op |= build_rd(va_arg(ap, u32)); | |
288 | if (ip->fields & RE) op |= build_re(va_arg(ap, u32)); | |
289 | if (ip->fields & SIMM) op |= build_simm(va_arg(ap, s32)); | |
290 | if (ip->fields & UIMM) op |= build_uimm(va_arg(ap, u32)); | |
291 | if (ip->fields & BIMM) op |= build_bimm(va_arg(ap, s32)); | |
292 | if (ip->fields & JIMM) op |= build_jimm(va_arg(ap, u32)); | |
293 | if (ip->fields & FUNC) op |= build_func(va_arg(ap, u32)); | |
41c594ab | 294 | if (ip->fields & SET) op |= build_set(va_arg(ap, u32)); |
1da177e4 LT |
295 | va_end(ap); |
296 | ||
297 | **buf = op; | |
298 | (*buf)++; | |
299 | } | |
300 | ||
301 | #define I_u1u2u3(op) \ | |
1443e483 | 302 | static inline void __init i##op(u32 **buf, unsigned int a, \ |
1da177e4 LT |
303 | unsigned int b, unsigned int c) \ |
304 | { \ | |
305 | build_insn(buf, insn##op, a, b, c); \ | |
306 | } | |
307 | ||
308 | #define I_u2u1u3(op) \ | |
1443e483 | 309 | static inline void __init i##op(u32 **buf, unsigned int a, \ |
1da177e4 LT |
310 | unsigned int b, unsigned int c) \ |
311 | { \ | |
312 | build_insn(buf, insn##op, b, a, c); \ | |
313 | } | |
314 | ||
315 | #define I_u3u1u2(op) \ | |
1443e483 | 316 | static inline void __init i##op(u32 **buf, unsigned int a, \ |
1da177e4 LT |
317 | unsigned int b, unsigned int c) \ |
318 | { \ | |
319 | build_insn(buf, insn##op, b, c, a); \ | |
320 | } | |
321 | ||
322 | #define I_u1u2s3(op) \ | |
1443e483 | 323 | static inline void __init i##op(u32 **buf, unsigned int a, \ |
1da177e4 LT |
324 | unsigned int b, signed int c) \ |
325 | { \ | |
326 | build_insn(buf, insn##op, a, b, c); \ | |
327 | } | |
328 | ||
329 | #define I_u2s3u1(op) \ | |
1443e483 | 330 | static inline void __init i##op(u32 **buf, unsigned int a, \ |
1da177e4 LT |
331 | signed int b, unsigned int c) \ |
332 | { \ | |
333 | build_insn(buf, insn##op, c, a, b); \ | |
334 | } | |
335 | ||
336 | #define I_u2u1s3(op) \ | |
1443e483 | 337 | static inline void __init i##op(u32 **buf, unsigned int a, \ |
1da177e4 LT |
338 | unsigned int b, signed int c) \ |
339 | { \ | |
340 | build_insn(buf, insn##op, b, a, c); \ | |
341 | } | |
342 | ||
343 | #define I_u1u2(op) \ | |
1443e483 | 344 | static inline void __init i##op(u32 **buf, unsigned int a, \ |
1da177e4 LT |
345 | unsigned int b) \ |
346 | { \ | |
347 | build_insn(buf, insn##op, a, b); \ | |
348 | } | |
349 | ||
350 | #define I_u1s2(op) \ | |
1443e483 | 351 | static inline void __init i##op(u32 **buf, unsigned int a, \ |
1da177e4 LT |
352 | signed int b) \ |
353 | { \ | |
354 | build_insn(buf, insn##op, a, b); \ | |
355 | } | |
356 | ||
357 | #define I_u1(op) \ | |
1443e483 | 358 | static inline void __init i##op(u32 **buf, unsigned int a) \ |
1da177e4 LT |
359 | { \ |
360 | build_insn(buf, insn##op, a); \ | |
361 | } | |
362 | ||
363 | #define I_0(op) \ | |
1443e483 | 364 | static inline void __init i##op(u32 **buf) \ |
1da177e4 LT |
365 | { \ |
366 | build_insn(buf, insn##op); \ | |
367 | } | |
368 | ||
369 | I_u2u1s3(_addiu); | |
370 | I_u3u1u2(_addu); | |
371 | I_u2u1u3(_andi); | |
372 | I_u3u1u2(_and); | |
373 | I_u1u2s3(_beq); | |
374 | I_u1u2s3(_beql); | |
375 | I_u1s2(_bgez); | |
376 | I_u1s2(_bgezl); | |
377 | I_u1s2(_bltz); | |
378 | I_u1s2(_bltzl); | |
379 | I_u1u2s3(_bne); | |
41c594ab RB |
380 | I_u1u2u3(_dmfc0); |
381 | I_u1u2u3(_dmtc0); | |
1da177e4 LT |
382 | I_u2u1s3(_daddiu); |
383 | I_u3u1u2(_daddu); | |
384 | I_u2u1u3(_dsll); | |
385 | I_u2u1u3(_dsll32); | |
386 | I_u2u1u3(_dsra); | |
387 | I_u2u1u3(_dsrl); | |
1da177e4 LT |
388 | I_u3u1u2(_dsubu); |
389 | I_0(_eret); | |
390 | I_u1(_j); | |
391 | I_u1(_jal); | |
392 | I_u1(_jr); | |
393 | I_u2s3u1(_ld); | |
394 | I_u2s3u1(_ll); | |
395 | I_u2s3u1(_lld); | |
396 | I_u1s2(_lui); | |
397 | I_u2s3u1(_lw); | |
41c594ab RB |
398 | I_u1u2u3(_mfc0); |
399 | I_u1u2u3(_mtc0); | |
1da177e4 LT |
400 | I_u2u1u3(_ori); |
401 | I_0(_rfe); | |
402 | I_u2s3u1(_sc); | |
403 | I_u2s3u1(_scd); | |
404 | I_u2s3u1(_sd); | |
405 | I_u2u1u3(_sll); | |
406 | I_u2u1u3(_sra); | |
407 | I_u2u1u3(_srl); | |
408 | I_u3u1u2(_subu); | |
409 | I_u2s3u1(_sw); | |
410 | I_0(_tlbp); | |
411 | I_0(_tlbwi); | |
412 | I_0(_tlbwr); | |
413 | I_u3u1u2(_xor) | |
414 | I_u2u1u3(_xori); | |
415 | ||
416 | /* | |
417 | * handling labels | |
418 | */ | |
419 | ||
420 | enum label_id { | |
421 | label_invalid, | |
422 | label_second_part, | |
423 | label_leave, | |
424 | label_vmalloc, | |
425 | label_vmalloc_done, | |
426 | label_tlbw_hazard, | |
427 | label_split, | |
428 | label_nopage_tlbl, | |
429 | label_nopage_tlbs, | |
430 | label_nopage_tlbm, | |
431 | label_smp_pgtable_change, | |
432 | label_r3000_write_probe_fail, | |
1da177e4 LT |
433 | }; |
434 | ||
435 | struct label { | |
436 | u32 *addr; | |
437 | enum label_id lab; | |
438 | }; | |
439 | ||
440 | static __init void build_label(struct label **lab, u32 *addr, | |
441 | enum label_id l) | |
442 | { | |
443 | (*lab)->addr = addr; | |
444 | (*lab)->lab = l; | |
445 | (*lab)++; | |
446 | } | |
447 | ||
448 | #define L_LA(lb) \ | |
449 | static inline void l##lb(struct label **lab, u32 *addr) \ | |
450 | { \ | |
451 | build_label(lab, addr, label##lb); \ | |
452 | } | |
453 | ||
454 | L_LA(_second_part) | |
455 | L_LA(_leave) | |
456 | L_LA(_vmalloc) | |
457 | L_LA(_vmalloc_done) | |
458 | L_LA(_tlbw_hazard) | |
459 | L_LA(_split) | |
460 | L_LA(_nopage_tlbl) | |
461 | L_LA(_nopage_tlbs) | |
462 | L_LA(_nopage_tlbm) | |
463 | L_LA(_smp_pgtable_change) | |
464 | L_LA(_r3000_write_probe_fail) | |
1da177e4 LT |
465 | |
466 | /* convenience macros for instructions */ | |
875d43e7 | 467 | #ifdef CONFIG_64BIT |
1da177e4 LT |
468 | # define i_LW(buf, rs, rt, off) i_ld(buf, rs, rt, off) |
469 | # define i_SW(buf, rs, rt, off) i_sd(buf, rs, rt, off) | |
470 | # define i_SLL(buf, rs, rt, sh) i_dsll(buf, rs, rt, sh) | |
471 | # define i_SRA(buf, rs, rt, sh) i_dsra(buf, rs, rt, sh) | |
472 | # define i_SRL(buf, rs, rt, sh) i_dsrl(buf, rs, rt, sh) | |
41c594ab RB |
473 | # define i_MFC0(buf, rt, rd...) i_dmfc0(buf, rt, rd) |
474 | # define i_MTC0(buf, rt, rd...) i_dmtc0(buf, rt, rd) | |
1da177e4 LT |
475 | # define i_ADDIU(buf, rs, rt, val) i_daddiu(buf, rs, rt, val) |
476 | # define i_ADDU(buf, rs, rt, rd) i_daddu(buf, rs, rt, rd) | |
477 | # define i_SUBU(buf, rs, rt, rd) i_dsubu(buf, rs, rt, rd) | |
478 | # define i_LL(buf, rs, rt, off) i_lld(buf, rs, rt, off) | |
479 | # define i_SC(buf, rs, rt, off) i_scd(buf, rs, rt, off) | |
480 | #else | |
481 | # define i_LW(buf, rs, rt, off) i_lw(buf, rs, rt, off) | |
482 | # define i_SW(buf, rs, rt, off) i_sw(buf, rs, rt, off) | |
483 | # define i_SLL(buf, rs, rt, sh) i_sll(buf, rs, rt, sh) | |
484 | # define i_SRA(buf, rs, rt, sh) i_sra(buf, rs, rt, sh) | |
485 | # define i_SRL(buf, rs, rt, sh) i_srl(buf, rs, rt, sh) | |
41c594ab RB |
486 | # define i_MFC0(buf, rt, rd...) i_mfc0(buf, rt, rd) |
487 | # define i_MTC0(buf, rt, rd...) i_mtc0(buf, rt, rd) | |
1da177e4 LT |
488 | # define i_ADDIU(buf, rs, rt, val) i_addiu(buf, rs, rt, val) |
489 | # define i_ADDU(buf, rs, rt, rd) i_addu(buf, rs, rt, rd) | |
490 | # define i_SUBU(buf, rs, rt, rd) i_subu(buf, rs, rt, rd) | |
491 | # define i_LL(buf, rs, rt, off) i_ll(buf, rs, rt, off) | |
492 | # define i_SC(buf, rs, rt, off) i_sc(buf, rs, rt, off) | |
493 | #endif | |
494 | ||
495 | #define i_b(buf, off) i_beq(buf, 0, 0, off) | |
496 | #define i_beqz(buf, rs, off) i_beq(buf, rs, 0, off) | |
497 | #define i_beqzl(buf, rs, off) i_beql(buf, rs, 0, off) | |
498 | #define i_bnez(buf, rs, off) i_bne(buf, rs, 0, off) | |
499 | #define i_bnezl(buf, rs, off) i_bnel(buf, rs, 0, off) | |
500 | #define i_move(buf, a, b) i_ADDU(buf, a, 0, b) | |
501 | #define i_nop(buf) i_sll(buf, 0, 0, 0) | |
502 | #define i_ssnop(buf) i_sll(buf, 0, 0, 1) | |
503 | #define i_ehb(buf) i_sll(buf, 0, 0, 3) | |
504 | ||
875d43e7 | 505 | #ifdef CONFIG_64BIT |
1da177e4 LT |
506 | static __init int __attribute__((unused)) in_compat_space_p(long addr) |
507 | { | |
508 | /* Is this address in 32bit compat space? */ | |
3ef33e68 | 509 | return (((addr) & 0xffffffff00000000L) == 0xffffffff00000000L); |
1da177e4 LT |
510 | } |
511 | ||
512 | static __init int __attribute__((unused)) rel_highest(long val) | |
513 | { | |
514 | return ((((val + 0x800080008000L) >> 48) & 0xffff) ^ 0x8000) - 0x8000; | |
515 | } | |
516 | ||
517 | static __init int __attribute__((unused)) rel_higher(long val) | |
518 | { | |
519 | return ((((val + 0x80008000L) >> 32) & 0xffff) ^ 0x8000) - 0x8000; | |
520 | } | |
521 | #endif | |
522 | ||
523 | static __init int rel_hi(long val) | |
524 | { | |
525 | return ((((val + 0x8000L) >> 16) & 0xffff) ^ 0x8000) - 0x8000; | |
526 | } | |
527 | ||
528 | static __init int rel_lo(long val) | |
529 | { | |
530 | return ((val & 0xffff) ^ 0x8000) - 0x8000; | |
531 | } | |
532 | ||
533 | static __init void i_LA_mostly(u32 **buf, unsigned int rs, long addr) | |
534 | { | |
766160c2 | 535 | #ifdef CONFIG_64BIT |
1da177e4 LT |
536 | if (!in_compat_space_p(addr)) { |
537 | i_lui(buf, rs, rel_highest(addr)); | |
538 | if (rel_higher(addr)) | |
539 | i_daddiu(buf, rs, rs, rel_higher(addr)); | |
540 | if (rel_hi(addr)) { | |
541 | i_dsll(buf, rs, rs, 16); | |
542 | i_daddiu(buf, rs, rs, rel_hi(addr)); | |
543 | i_dsll(buf, rs, rs, 16); | |
544 | } else | |
545 | i_dsll32(buf, rs, rs, 0); | |
546 | } else | |
547 | #endif | |
548 | i_lui(buf, rs, rel_hi(addr)); | |
549 | } | |
550 | ||
551 | static __init void __attribute__((unused)) i_LA(u32 **buf, unsigned int rs, | |
552 | long addr) | |
553 | { | |
554 | i_LA_mostly(buf, rs, addr); | |
555 | if (rel_lo(addr)) | |
556 | i_ADDIU(buf, rs, rs, rel_lo(addr)); | |
557 | } | |
558 | ||
559 | /* | |
560 | * handle relocations | |
561 | */ | |
562 | ||
563 | struct reloc { | |
564 | u32 *addr; | |
565 | unsigned int type; | |
566 | enum label_id lab; | |
567 | }; | |
568 | ||
569 | static __init void r_mips_pc16(struct reloc **rel, u32 *addr, | |
570 | enum label_id l) | |
571 | { | |
572 | (*rel)->addr = addr; | |
573 | (*rel)->type = R_MIPS_PC16; | |
574 | (*rel)->lab = l; | |
575 | (*rel)++; | |
576 | } | |
577 | ||
578 | static inline void __resolve_relocs(struct reloc *rel, struct label *lab) | |
579 | { | |
580 | long laddr = (long)lab->addr; | |
581 | long raddr = (long)rel->addr; | |
582 | ||
583 | switch (rel->type) { | |
584 | case R_MIPS_PC16: | |
585 | *rel->addr |= build_bimm(laddr - (raddr + 4)); | |
586 | break; | |
587 | ||
588 | default: | |
589 | panic("Unsupported TLB synthesizer relocation %d", | |
590 | rel->type); | |
591 | } | |
592 | } | |
593 | ||
594 | static __init void resolve_relocs(struct reloc *rel, struct label *lab) | |
595 | { | |
596 | struct label *l; | |
597 | ||
598 | for (; rel->lab != label_invalid; rel++) | |
599 | for (l = lab; l->lab != label_invalid; l++) | |
600 | if (rel->lab == l->lab) | |
601 | __resolve_relocs(rel, l); | |
602 | } | |
603 | ||
604 | static __init void move_relocs(struct reloc *rel, u32 *first, u32 *end, | |
605 | long off) | |
606 | { | |
607 | for (; rel->lab != label_invalid; rel++) | |
608 | if (rel->addr >= first && rel->addr < end) | |
609 | rel->addr += off; | |
610 | } | |
611 | ||
612 | static __init void move_labels(struct label *lab, u32 *first, u32 *end, | |
613 | long off) | |
614 | { | |
615 | for (; lab->lab != label_invalid; lab++) | |
616 | if (lab->addr >= first && lab->addr < end) | |
617 | lab->addr += off; | |
618 | } | |
619 | ||
620 | static __init void copy_handler(struct reloc *rel, struct label *lab, | |
621 | u32 *first, u32 *end, u32 *target) | |
622 | { | |
623 | long off = (long)(target - first); | |
624 | ||
625 | memcpy(target, first, (end - first) * sizeof(u32)); | |
626 | ||
627 | move_relocs(rel, first, end, off); | |
628 | move_labels(lab, first, end, off); | |
629 | } | |
630 | ||
631 | static __init int __attribute__((unused)) insn_has_bdelay(struct reloc *rel, | |
632 | u32 *addr) | |
633 | { | |
634 | for (; rel->lab != label_invalid; rel++) { | |
635 | if (rel->addr == addr | |
636 | && (rel->type == R_MIPS_PC16 | |
637 | || rel->type == R_MIPS_26)) | |
638 | return 1; | |
639 | } | |
640 | ||
641 | return 0; | |
642 | } | |
643 | ||
644 | /* convenience functions for labeled branches */ | |
1443e483 RB |
645 | static void __init __attribute__((unused)) |
646 | il_bltz(u32 **p, struct reloc **r, unsigned int reg, enum label_id l) | |
1da177e4 LT |
647 | { |
648 | r_mips_pc16(r, *p, l); | |
649 | i_bltz(p, reg, 0); | |
650 | } | |
651 | ||
1443e483 | 652 | static void __init __attribute__((unused)) il_b(u32 **p, struct reloc **r, |
1da177e4 LT |
653 | enum label_id l) |
654 | { | |
655 | r_mips_pc16(r, *p, l); | |
656 | i_b(p, 0); | |
657 | } | |
658 | ||
1443e483 | 659 | static void __init il_beqz(u32 **p, struct reloc **r, unsigned int reg, |
1da177e4 LT |
660 | enum label_id l) |
661 | { | |
662 | r_mips_pc16(r, *p, l); | |
663 | i_beqz(p, reg, 0); | |
664 | } | |
665 | ||
1443e483 | 666 | static void __init __attribute__((unused)) |
1da177e4 LT |
667 | il_beqzl(u32 **p, struct reloc **r, unsigned int reg, enum label_id l) |
668 | { | |
669 | r_mips_pc16(r, *p, l); | |
670 | i_beqzl(p, reg, 0); | |
671 | } | |
672 | ||
1443e483 | 673 | static void __init il_bnez(u32 **p, struct reloc **r, unsigned int reg, |
1da177e4 LT |
674 | enum label_id l) |
675 | { | |
676 | r_mips_pc16(r, *p, l); | |
677 | i_bnez(p, reg, 0); | |
678 | } | |
679 | ||
1443e483 | 680 | static void __init il_bgezl(u32 **p, struct reloc **r, unsigned int reg, |
1da177e4 LT |
681 | enum label_id l) |
682 | { | |
683 | r_mips_pc16(r, *p, l); | |
684 | i_bgezl(p, reg, 0); | |
685 | } | |
686 | ||
687 | /* The only general purpose registers allowed in TLB handlers. */ | |
688 | #define K0 26 | |
689 | #define K1 27 | |
690 | ||
691 | /* Some CP0 registers */ | |
41c594ab RB |
692 | #define C0_INDEX 0, 0 |
693 | #define C0_ENTRYLO0 2, 0 | |
694 | #define C0_TCBIND 2, 2 | |
695 | #define C0_ENTRYLO1 3, 0 | |
696 | #define C0_CONTEXT 4, 0 | |
697 | #define C0_BADVADDR 8, 0 | |
698 | #define C0_ENTRYHI 10, 0 | |
699 | #define C0_EPC 14, 0 | |
700 | #define C0_XCONTEXT 20, 0 | |
1da177e4 | 701 | |
875d43e7 | 702 | #ifdef CONFIG_64BIT |
1da177e4 LT |
703 | # define GET_CONTEXT(buf, reg) i_MFC0(buf, reg, C0_XCONTEXT) |
704 | #else | |
705 | # define GET_CONTEXT(buf, reg) i_MFC0(buf, reg, C0_CONTEXT) | |
706 | #endif | |
707 | ||
708 | /* The worst case length of the handler is around 18 instructions for | |
709 | * R3000-style TLBs and up to 63 instructions for R4000-style TLBs. | |
710 | * Maximum space available is 32 instructions for R3000 and 64 | |
711 | * instructions for R4000. | |
712 | * | |
713 | * We deliberately chose a buffer size of 128, so we won't scribble | |
714 | * over anything important on overflow before we panic. | |
715 | */ | |
716 | static __initdata u32 tlb_handler[128]; | |
717 | ||
718 | /* simply assume worst case size for labels and relocs */ | |
719 | static __initdata struct label labels[128]; | |
720 | static __initdata struct reloc relocs[128]; | |
721 | ||
722 | /* | |
723 | * The R3000 TLB handler is simple. | |
724 | */ | |
725 | static void __init build_r3000_tlb_refill_handler(void) | |
726 | { | |
727 | long pgdc = (long)pgd_current; | |
728 | u32 *p; | |
115f2a44 | 729 | int i; |
1da177e4 LT |
730 | |
731 | memset(tlb_handler, 0, sizeof(tlb_handler)); | |
732 | p = tlb_handler; | |
733 | ||
734 | i_mfc0(&p, K0, C0_BADVADDR); | |
735 | i_lui(&p, K1, rel_hi(pgdc)); /* cp0 delay */ | |
736 | i_lw(&p, K1, rel_lo(pgdc), K1); | |
737 | i_srl(&p, K0, K0, 22); /* load delay */ | |
738 | i_sll(&p, K0, K0, 2); | |
739 | i_addu(&p, K1, K1, K0); | |
740 | i_mfc0(&p, K0, C0_CONTEXT); | |
741 | i_lw(&p, K1, 0, K1); /* cp0 delay */ | |
742 | i_andi(&p, K0, K0, 0xffc); /* load delay */ | |
743 | i_addu(&p, K1, K1, K0); | |
744 | i_lw(&p, K0, 0, K1); | |
745 | i_nop(&p); /* load delay */ | |
746 | i_mtc0(&p, K0, C0_ENTRYLO0); | |
747 | i_mfc0(&p, K1, C0_EPC); /* cp0 delay */ | |
748 | i_tlbwr(&p); /* cp0 delay */ | |
749 | i_jr(&p, K1); | |
750 | i_rfe(&p); /* branch delay */ | |
751 | ||
752 | if (p > tlb_handler + 32) | |
753 | panic("TLB refill handler space exceeded"); | |
754 | ||
115f2a44 TS |
755 | pr_info("Synthesized TLB refill handler (%u instructions).\n", |
756 | (unsigned int)(p - tlb_handler)); | |
1da177e4 | 757 | |
115f2a44 TS |
758 | pr_debug("\t.set push\n"); |
759 | pr_debug("\t.set noreorder\n"); | |
760 | for (i = 0; i < (p - tlb_handler); i++) | |
761 | pr_debug("\t.word 0x%08x\n", tlb_handler[i]); | |
762 | pr_debug("\t.set pop\n"); | |
1da177e4 | 763 | |
91b05e67 | 764 | memcpy((void *)ebase, tlb_handler, 0x80); |
1da177e4 LT |
765 | } |
766 | ||
767 | /* | |
768 | * The R4000 TLB handler is much more complicated. We have two | |
769 | * consecutive handler areas with 32 instructions space each. | |
770 | * Since they aren't used at the same time, we can overflow in the | |
771 | * other one.To keep things simple, we first assume linear space, | |
772 | * then we relocate it to the final handler layout as needed. | |
773 | */ | |
774 | static __initdata u32 final_handler[64]; | |
775 | ||
776 | /* | |
777 | * Hazards | |
778 | * | |
779 | * From the IDT errata for the QED RM5230 (Nevada), processor revision 1.0: | |
780 | * 2. A timing hazard exists for the TLBP instruction. | |
781 | * | |
782 | * stalling_instruction | |
783 | * TLBP | |
784 | * | |
785 | * The JTLB is being read for the TLBP throughout the stall generated by the | |
786 | * previous instruction. This is not really correct as the stalling instruction | |
787 | * can modify the address used to access the JTLB. The failure symptom is that | |
788 | * the TLBP instruction will use an address created for the stalling instruction | |
789 | * and not the address held in C0_ENHI and thus report the wrong results. | |
790 | * | |
791 | * The software work-around is to not allow the instruction preceding the TLBP | |
792 | * to stall - make it an NOP or some other instruction guaranteed not to stall. | |
793 | * | |
794 | * Errata 2 will not be fixed. This errata is also on the R5000. | |
795 | * | |
796 | * As if we MIPS hackers wouldn't know how to nop pipelines happy ... | |
797 | */ | |
798 | static __init void __attribute__((unused)) build_tlb_probe_entry(u32 **p) | |
799 | { | |
800 | switch (current_cpu_data.cputype) { | |
f5b4d956 TS |
801 | /* Found by experiment: R4600 v2.0 needs this, too. */ |
802 | case CPU_R4600: | |
1da177e4 LT |
803 | case CPU_R5000: |
804 | case CPU_R5000A: | |
805 | case CPU_NEVADA: | |
806 | i_nop(p); | |
807 | i_tlbp(p); | |
808 | break; | |
809 | ||
810 | default: | |
811 | i_tlbp(p); | |
812 | break; | |
813 | } | |
814 | } | |
815 | ||
816 | /* | |
817 | * Write random or indexed TLB entry, and care about the hazards from | |
818 | * the preceeding mtc0 and for the following eret. | |
819 | */ | |
820 | enum tlb_write_entry { tlb_random, tlb_indexed }; | |
821 | ||
822 | static __init void build_tlb_write_entry(u32 **p, struct label **l, | |
823 | struct reloc **r, | |
824 | enum tlb_write_entry wmode) | |
825 | { | |
826 | void(*tlbw)(u32 **) = NULL; | |
827 | ||
828 | switch (wmode) { | |
829 | case tlb_random: tlbw = i_tlbwr; break; | |
830 | case tlb_indexed: tlbw = i_tlbwi; break; | |
831 | } | |
832 | ||
833 | switch (current_cpu_data.cputype) { | |
834 | case CPU_R4000PC: | |
835 | case CPU_R4000SC: | |
836 | case CPU_R4000MC: | |
837 | case CPU_R4400PC: | |
838 | case CPU_R4400SC: | |
839 | case CPU_R4400MC: | |
840 | /* | |
841 | * This branch uses up a mtc0 hazard nop slot and saves | |
842 | * two nops after the tlbw instruction. | |
843 | */ | |
844 | il_bgezl(p, r, 0, label_tlbw_hazard); | |
845 | tlbw(p); | |
846 | l_tlbw_hazard(l, *p); | |
847 | i_nop(p); | |
848 | break; | |
849 | ||
850 | case CPU_R4600: | |
851 | case CPU_R4700: | |
852 | case CPU_R5000: | |
853 | case CPU_R5000A: | |
2c93e12c MR |
854 | i_nop(p); |
855 | tlbw(p); | |
856 | i_nop(p); | |
857 | break; | |
858 | ||
859 | case CPU_R4300: | |
1da177e4 LT |
860 | case CPU_5KC: |
861 | case CPU_TX49XX: | |
862 | case CPU_AU1000: | |
863 | case CPU_AU1100: | |
864 | case CPU_AU1500: | |
865 | case CPU_AU1550: | |
e3ad1c23 | 866 | case CPU_AU1200: |
bdf21b18 | 867 | case CPU_PR4450: |
1da177e4 LT |
868 | i_nop(p); |
869 | tlbw(p); | |
870 | break; | |
871 | ||
872 | case CPU_R10000: | |
873 | case CPU_R12000: | |
44d921b2 | 874 | case CPU_R14000: |
1da177e4 LT |
875 | case CPU_4KC: |
876 | case CPU_SB1: | |
93ce2f52 | 877 | case CPU_SB1A: |
1da177e4 LT |
878 | case CPU_4KSC: |
879 | case CPU_20KC: | |
880 | case CPU_25KF: | |
881 | tlbw(p); | |
882 | break; | |
883 | ||
884 | case CPU_NEVADA: | |
885 | i_nop(p); /* QED specifies 2 nops hazard */ | |
886 | /* | |
887 | * This branch uses up a mtc0 hazard nop slot and saves | |
888 | * a nop after the tlbw instruction. | |
889 | */ | |
890 | il_bgezl(p, r, 0, label_tlbw_hazard); | |
891 | tlbw(p); | |
892 | l_tlbw_hazard(l, *p); | |
893 | break; | |
894 | ||
895 | case CPU_RM7000: | |
896 | i_nop(p); | |
897 | i_nop(p); | |
898 | i_nop(p); | |
899 | i_nop(p); | |
900 | tlbw(p); | |
901 | break; | |
902 | ||
903 | case CPU_4KEC: | |
904 | case CPU_24K: | |
bbc7f22f | 905 | case CPU_34K: |
c620953c | 906 | case CPU_74K: |
1da177e4 LT |
907 | i_ehb(p); |
908 | tlbw(p); | |
909 | break; | |
910 | ||
911 | case CPU_RM9000: | |
912 | /* | |
913 | * When the JTLB is updated by tlbwi or tlbwr, a subsequent | |
914 | * use of the JTLB for instructions should not occur for 4 | |
915 | * cpu cycles and use for data translations should not occur | |
916 | * for 3 cpu cycles. | |
917 | */ | |
918 | i_ssnop(p); | |
919 | i_ssnop(p); | |
920 | i_ssnop(p); | |
921 | i_ssnop(p); | |
922 | tlbw(p); | |
923 | i_ssnop(p); | |
924 | i_ssnop(p); | |
925 | i_ssnop(p); | |
926 | i_ssnop(p); | |
927 | break; | |
928 | ||
929 | case CPU_VR4111: | |
930 | case CPU_VR4121: | |
931 | case CPU_VR4122: | |
932 | case CPU_VR4181: | |
933 | case CPU_VR4181A: | |
934 | i_nop(p); | |
935 | i_nop(p); | |
936 | tlbw(p); | |
937 | i_nop(p); | |
938 | i_nop(p); | |
939 | break; | |
940 | ||
941 | case CPU_VR4131: | |
942 | case CPU_VR4133: | |
7623debf | 943 | case CPU_R5432: |
1da177e4 LT |
944 | i_nop(p); |
945 | i_nop(p); | |
946 | tlbw(p); | |
947 | break; | |
948 | ||
949 | default: | |
950 | panic("No TLB refill handler yet (CPU type: %d)", | |
951 | current_cpu_data.cputype); | |
952 | break; | |
953 | } | |
954 | } | |
955 | ||
875d43e7 | 956 | #ifdef CONFIG_64BIT |
1da177e4 LT |
957 | /* |
958 | * TMP and PTR are scratch. | |
959 | * TMP will be clobbered, PTR will hold the pmd entry. | |
960 | */ | |
961 | static __init void | |
962 | build_get_pmde64(u32 **p, struct label **l, struct reloc **r, | |
963 | unsigned int tmp, unsigned int ptr) | |
964 | { | |
965 | long pgdc = (long)pgd_current; | |
966 | ||
967 | /* | |
968 | * The vmalloc handling is not in the hotpath. | |
969 | */ | |
970 | i_dmfc0(p, tmp, C0_BADVADDR); | |
971 | il_bltz(p, r, tmp, label_vmalloc); | |
972 | /* No i_nop needed here, since the next insn doesn't touch TMP. */ | |
973 | ||
974 | #ifdef CONFIG_SMP | |
41c594ab RB |
975 | # ifdef CONFIG_MIPS_MT_SMTC |
976 | /* | |
977 | * SMTC uses TCBind value as "CPU" index | |
978 | */ | |
979 | i_mfc0(p, ptr, C0_TCBIND); | |
980 | i_dsrl(p, ptr, ptr, 19); | |
981 | # else | |
1da177e4 | 982 | /* |
1b3a6e97 | 983 | * 64 bit SMP running in XKPHYS has smp_processor_id() << 3 |
1da177e4 LT |
984 | * stored in CONTEXT. |
985 | */ | |
1b3a6e97 TS |
986 | i_dmfc0(p, ptr, C0_CONTEXT); |
987 | i_dsrl(p, ptr, ptr, 23); | |
41c594ab | 988 | #endif |
1b3a6e97 TS |
989 | i_LA_mostly(p, tmp, pgdc); |
990 | i_daddu(p, ptr, ptr, tmp); | |
991 | i_dmfc0(p, tmp, C0_BADVADDR); | |
992 | i_ld(p, ptr, rel_lo(pgdc), ptr); | |
1da177e4 LT |
993 | #else |
994 | i_LA_mostly(p, ptr, pgdc); | |
995 | i_ld(p, ptr, rel_lo(pgdc), ptr); | |
996 | #endif | |
997 | ||
998 | l_vmalloc_done(l, *p); | |
999 | i_dsrl(p, tmp, tmp, PGDIR_SHIFT-3); /* get pgd offset in bytes */ | |
1000 | i_andi(p, tmp, tmp, (PTRS_PER_PGD - 1)<<3); | |
1001 | i_daddu(p, ptr, ptr, tmp); /* add in pgd offset */ | |
1002 | i_dmfc0(p, tmp, C0_BADVADDR); /* get faulting address */ | |
1003 | i_ld(p, ptr, 0, ptr); /* get pmd pointer */ | |
1004 | i_dsrl(p, tmp, tmp, PMD_SHIFT-3); /* get pmd offset in bytes */ | |
1005 | i_andi(p, tmp, tmp, (PTRS_PER_PMD - 1)<<3); | |
1006 | i_daddu(p, ptr, ptr, tmp); /* add in pmd offset */ | |
1007 | } | |
1008 | ||
1009 | /* | |
1010 | * BVADDR is the faulting address, PTR is scratch. | |
1011 | * PTR will hold the pgd for vmalloc. | |
1012 | */ | |
1013 | static __init void | |
1014 | build_get_pgd_vmalloc64(u32 **p, struct label **l, struct reloc **r, | |
1015 | unsigned int bvaddr, unsigned int ptr) | |
1016 | { | |
1017 | long swpd = (long)swapper_pg_dir; | |
1018 | ||
1019 | l_vmalloc(l, *p); | |
1020 | i_LA(p, ptr, VMALLOC_START); | |
1021 | i_dsubu(p, bvaddr, bvaddr, ptr); | |
1022 | ||
1023 | if (in_compat_space_p(swpd) && !rel_lo(swpd)) { | |
1024 | il_b(p, r, label_vmalloc_done); | |
1025 | i_lui(p, ptr, rel_hi(swpd)); | |
1026 | } else { | |
1027 | i_LA_mostly(p, ptr, swpd); | |
1028 | il_b(p, r, label_vmalloc_done); | |
1029 | i_daddiu(p, ptr, ptr, rel_lo(swpd)); | |
1030 | } | |
1031 | } | |
1032 | ||
875d43e7 | 1033 | #else /* !CONFIG_64BIT */ |
1da177e4 LT |
1034 | |
1035 | /* | |
1036 | * TMP and PTR are scratch. | |
1037 | * TMP will be clobbered, PTR will hold the pgd entry. | |
1038 | */ | |
1039 | static __init void __attribute__((unused)) | |
1040 | build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr) | |
1041 | { | |
1042 | long pgdc = (long)pgd_current; | |
1043 | ||
1044 | /* 32 bit SMP has smp_processor_id() stored in CONTEXT. */ | |
1045 | #ifdef CONFIG_SMP | |
41c594ab RB |
1046 | #ifdef CONFIG_MIPS_MT_SMTC |
1047 | /* | |
1048 | * SMTC uses TCBind value as "CPU" index | |
1049 | */ | |
1050 | i_mfc0(p, ptr, C0_TCBIND); | |
1051 | i_LA_mostly(p, tmp, pgdc); | |
1052 | i_srl(p, ptr, ptr, 19); | |
1053 | #else | |
1054 | /* | |
1055 | * smp_processor_id() << 3 is stored in CONTEXT. | |
1056 | */ | |
1da177e4 LT |
1057 | i_mfc0(p, ptr, C0_CONTEXT); |
1058 | i_LA_mostly(p, tmp, pgdc); | |
1059 | i_srl(p, ptr, ptr, 23); | |
41c594ab | 1060 | #endif |
1da177e4 LT |
1061 | i_addu(p, ptr, tmp, ptr); |
1062 | #else | |
1063 | i_LA_mostly(p, ptr, pgdc); | |
1064 | #endif | |
1065 | i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */ | |
1066 | i_lw(p, ptr, rel_lo(pgdc), ptr); | |
1067 | i_srl(p, tmp, tmp, PGDIR_SHIFT); /* get pgd only bits */ | |
1068 | i_sll(p, tmp, tmp, PGD_T_LOG2); | |
1069 | i_addu(p, ptr, ptr, tmp); /* add in pgd offset */ | |
1070 | } | |
1071 | ||
875d43e7 | 1072 | #endif /* !CONFIG_64BIT */ |
1da177e4 LT |
1073 | |
1074 | static __init void build_adjust_context(u32 **p, unsigned int ctx) | |
1075 | { | |
1076 | unsigned int shift = 4 - (PTE_T_LOG2 + 1); | |
1077 | unsigned int mask = (PTRS_PER_PTE / 2 - 1) << (PTE_T_LOG2 + 1); | |
1078 | ||
1079 | switch (current_cpu_data.cputype) { | |
1080 | case CPU_VR41XX: | |
1081 | case CPU_VR4111: | |
1082 | case CPU_VR4121: | |
1083 | case CPU_VR4122: | |
1084 | case CPU_VR4131: | |
1085 | case CPU_VR4181: | |
1086 | case CPU_VR4181A: | |
1087 | case CPU_VR4133: | |
1088 | shift += 2; | |
1089 | break; | |
1090 | ||
1091 | default: | |
1092 | break; | |
1093 | } | |
1094 | ||
1095 | if (shift) | |
1096 | i_SRL(p, ctx, ctx, shift); | |
1097 | i_andi(p, ctx, ctx, mask); | |
1098 | } | |
1099 | ||
1100 | static __init void build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr) | |
1101 | { | |
1102 | /* | |
1103 | * Bug workaround for the Nevada. It seems as if under certain | |
1104 | * circumstances the move from cp0_context might produce a | |
1105 | * bogus result when the mfc0 instruction and its consumer are | |
1106 | * in a different cacheline or a load instruction, probably any | |
1107 | * memory reference, is between them. | |
1108 | */ | |
1109 | switch (current_cpu_data.cputype) { | |
1110 | case CPU_NEVADA: | |
1111 | i_LW(p, ptr, 0, ptr); | |
1112 | GET_CONTEXT(p, tmp); /* get context reg */ | |
1113 | break; | |
1114 | ||
1115 | default: | |
1116 | GET_CONTEXT(p, tmp); /* get context reg */ | |
1117 | i_LW(p, ptr, 0, ptr); | |
1118 | break; | |
1119 | } | |
1120 | ||
1121 | build_adjust_context(p, tmp); | |
1122 | i_ADDU(p, ptr, ptr, tmp); /* add in offset */ | |
1123 | } | |
1124 | ||
1125 | static __init void build_update_entries(u32 **p, unsigned int tmp, | |
1126 | unsigned int ptep) | |
1127 | { | |
1128 | /* | |
1129 | * 64bit address support (36bit on a 32bit CPU) in a 32bit | |
1130 | * Kernel is a special case. Only a few CPUs use it. | |
1131 | */ | |
1132 | #ifdef CONFIG_64BIT_PHYS_ADDR | |
1133 | if (cpu_has_64bits) { | |
1134 | i_ld(p, tmp, 0, ptep); /* get even pte */ | |
1135 | i_ld(p, ptep, sizeof(pte_t), ptep); /* get odd pte */ | |
1136 | i_dsrl(p, tmp, tmp, 6); /* convert to entrylo0 */ | |
1137 | i_mtc0(p, tmp, C0_ENTRYLO0); /* load it */ | |
1138 | i_dsrl(p, ptep, ptep, 6); /* convert to entrylo1 */ | |
1139 | i_mtc0(p, ptep, C0_ENTRYLO1); /* load it */ | |
1140 | } else { | |
1141 | int pte_off_even = sizeof(pte_t) / 2; | |
1142 | int pte_off_odd = pte_off_even + sizeof(pte_t); | |
1143 | ||
1144 | /* The pte entries are pre-shifted */ | |
1145 | i_lw(p, tmp, pte_off_even, ptep); /* get even pte */ | |
1146 | i_mtc0(p, tmp, C0_ENTRYLO0); /* load it */ | |
1147 | i_lw(p, ptep, pte_off_odd, ptep); /* get odd pte */ | |
1148 | i_mtc0(p, ptep, C0_ENTRYLO1); /* load it */ | |
1149 | } | |
1150 | #else | |
1151 | i_LW(p, tmp, 0, ptep); /* get even pte */ | |
1152 | i_LW(p, ptep, sizeof(pte_t), ptep); /* get odd pte */ | |
1153 | if (r45k_bvahwbug()) | |
1154 | build_tlb_probe_entry(p); | |
1155 | i_SRL(p, tmp, tmp, 6); /* convert to entrylo0 */ | |
1156 | if (r4k_250MHZhwbug()) | |
1157 | i_mtc0(p, 0, C0_ENTRYLO0); | |
1158 | i_mtc0(p, tmp, C0_ENTRYLO0); /* load it */ | |
1159 | i_SRL(p, ptep, ptep, 6); /* convert to entrylo1 */ | |
1160 | if (r45k_bvahwbug()) | |
1161 | i_mfc0(p, tmp, C0_INDEX); | |
1162 | if (r4k_250MHZhwbug()) | |
1163 | i_mtc0(p, 0, C0_ENTRYLO1); | |
1164 | i_mtc0(p, ptep, C0_ENTRYLO1); /* load it */ | |
1165 | #endif | |
1166 | } | |
1167 | ||
1168 | static void __init build_r4000_tlb_refill_handler(void) | |
1169 | { | |
1170 | u32 *p = tlb_handler; | |
1171 | struct label *l = labels; | |
1172 | struct reloc *r = relocs; | |
1173 | u32 *f; | |
1174 | unsigned int final_len; | |
115f2a44 | 1175 | int i; |
1da177e4 LT |
1176 | |
1177 | memset(tlb_handler, 0, sizeof(tlb_handler)); | |
1178 | memset(labels, 0, sizeof(labels)); | |
1179 | memset(relocs, 0, sizeof(relocs)); | |
1180 | memset(final_handler, 0, sizeof(final_handler)); | |
1181 | ||
1182 | /* | |
1183 | * create the plain linear handler | |
1184 | */ | |
1185 | if (bcm1250_m3_war()) { | |
1186 | i_MFC0(&p, K0, C0_BADVADDR); | |
1187 | i_MFC0(&p, K1, C0_ENTRYHI); | |
1188 | i_xor(&p, K0, K0, K1); | |
1189 | i_SRL(&p, K0, K0, PAGE_SHIFT + 1); | |
1190 | il_bnez(&p, &r, K0, label_leave); | |
1191 | /* No need for i_nop */ | |
1192 | } | |
1193 | ||
875d43e7 | 1194 | #ifdef CONFIG_64BIT |
1da177e4 LT |
1195 | build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */ |
1196 | #else | |
1197 | build_get_pgde32(&p, K0, K1); /* get pgd in K1 */ | |
1198 | #endif | |
1199 | ||
1200 | build_get_ptep(&p, K0, K1); | |
1201 | build_update_entries(&p, K0, K1); | |
1202 | build_tlb_write_entry(&p, &l, &r, tlb_random); | |
1203 | l_leave(&l, p); | |
1204 | i_eret(&p); /* return from trap */ | |
1205 | ||
875d43e7 | 1206 | #ifdef CONFIG_64BIT |
1da177e4 LT |
1207 | build_get_pgd_vmalloc64(&p, &l, &r, K0, K1); |
1208 | #endif | |
1209 | ||
1210 | /* | |
1211 | * Overflow check: For the 64bit handler, we need at least one | |
1212 | * free instruction slot for the wrap-around branch. In worst | |
1213 | * case, if the intended insertion point is a delay slot, we | |
1214 | * need three, with the the second nop'ed and the third being | |
1215 | * unused. | |
1216 | */ | |
875d43e7 | 1217 | #ifdef CONFIG_32BIT |
1da177e4 LT |
1218 | if ((p - tlb_handler) > 64) |
1219 | panic("TLB refill handler space exceeded"); | |
1220 | #else | |
1221 | if (((p - tlb_handler) > 63) | |
1222 | || (((p - tlb_handler) > 61) | |
1223 | && insn_has_bdelay(relocs, tlb_handler + 29))) | |
1224 | panic("TLB refill handler space exceeded"); | |
1225 | #endif | |
1226 | ||
1227 | /* | |
1228 | * Now fold the handler in the TLB refill handler space. | |
1229 | */ | |
875d43e7 | 1230 | #ifdef CONFIG_32BIT |
1da177e4 LT |
1231 | f = final_handler; |
1232 | /* Simplest case, just copy the handler. */ | |
1233 | copy_handler(relocs, labels, tlb_handler, p, f); | |
1234 | final_len = p - tlb_handler; | |
875d43e7 | 1235 | #else /* CONFIG_64BIT */ |
1da177e4 LT |
1236 | f = final_handler + 32; |
1237 | if ((p - tlb_handler) <= 32) { | |
1238 | /* Just copy the handler. */ | |
1239 | copy_handler(relocs, labels, tlb_handler, p, f); | |
1240 | final_len = p - tlb_handler; | |
1241 | } else { | |
1242 | u32 *split = tlb_handler + 30; | |
1243 | ||
1244 | /* | |
1245 | * Find the split point. | |
1246 | */ | |
1247 | if (insn_has_bdelay(relocs, split - 1)) | |
1248 | split--; | |
1249 | ||
1250 | /* Copy first part of the handler. */ | |
1251 | copy_handler(relocs, labels, tlb_handler, split, f); | |
1252 | f += split - tlb_handler; | |
1253 | ||
1254 | /* Insert branch. */ | |
1255 | l_split(&l, final_handler); | |
1256 | il_b(&f, &r, label_split); | |
1257 | if (insn_has_bdelay(relocs, split)) | |
1258 | i_nop(&f); | |
1259 | else { | |
1260 | copy_handler(relocs, labels, split, split + 1, f); | |
1261 | move_labels(labels, f, f + 1, -1); | |
1262 | f++; | |
1263 | split++; | |
1264 | } | |
1265 | ||
1266 | /* Copy the rest of the handler. */ | |
1267 | copy_handler(relocs, labels, split, p, final_handler); | |
1268 | final_len = (f - (final_handler + 32)) + (p - split); | |
1269 | } | |
875d43e7 | 1270 | #endif /* CONFIG_64BIT */ |
1da177e4 LT |
1271 | |
1272 | resolve_relocs(relocs, labels); | |
115f2a44 TS |
1273 | pr_info("Synthesized TLB refill handler (%u instructions).\n", |
1274 | final_len); | |
1da177e4 | 1275 | |
115f2a44 | 1276 | f = final_handler; |
4c0a2d42 | 1277 | #ifdef CONFIG_64BIT |
115f2a44 TS |
1278 | if (final_len > 32) |
1279 | final_len = 64; | |
1280 | else | |
1281 | f = final_handler + 32; | |
4c0a2d42 | 1282 | #endif /* CONFIG_64BIT */ |
115f2a44 TS |
1283 | pr_debug("\t.set push\n"); |
1284 | pr_debug("\t.set noreorder\n"); | |
1285 | for (i = 0; i < final_len; i++) | |
1286 | pr_debug("\t.word 0x%08x\n", f[i]); | |
1287 | pr_debug("\t.set pop\n"); | |
1da177e4 | 1288 | |
91b05e67 | 1289 | memcpy((void *)ebase, final_handler, 0x100); |
1da177e4 LT |
1290 | } |
1291 | ||
1292 | /* | |
1293 | * TLB load/store/modify handlers. | |
1294 | * | |
1295 | * Only the fastpath gets synthesized at runtime, the slowpath for | |
1296 | * do_page_fault remains normal asm. | |
1297 | */ | |
1298 | extern void tlb_do_page_fault_0(void); | |
1299 | extern void tlb_do_page_fault_1(void); | |
1300 | ||
1301 | #define __tlb_handler_align \ | |
1302 | __attribute__((__aligned__(1 << CONFIG_MIPS_L1_CACHE_SHIFT))) | |
1303 | ||
1304 | /* | |
1305 | * 128 instructions for the fastpath handler is generous and should | |
1306 | * never be exceeded. | |
1307 | */ | |
1308 | #define FASTPATH_SIZE 128 | |
1309 | ||
1310 | u32 __tlb_handler_align handle_tlbl[FASTPATH_SIZE]; | |
1311 | u32 __tlb_handler_align handle_tlbs[FASTPATH_SIZE]; | |
1312 | u32 __tlb_handler_align handle_tlbm[FASTPATH_SIZE]; | |
1313 | ||
1314 | static void __init | |
63b2d2f4 | 1315 | iPTE_LW(u32 **p, struct label **l, unsigned int pte, unsigned int ptr) |
1da177e4 LT |
1316 | { |
1317 | #ifdef CONFIG_SMP | |
1318 | # ifdef CONFIG_64BIT_PHYS_ADDR | |
1319 | if (cpu_has_64bits) | |
63b2d2f4 | 1320 | i_lld(p, pte, 0, ptr); |
1da177e4 LT |
1321 | else |
1322 | # endif | |
63b2d2f4 | 1323 | i_LL(p, pte, 0, ptr); |
1da177e4 LT |
1324 | #else |
1325 | # ifdef CONFIG_64BIT_PHYS_ADDR | |
1326 | if (cpu_has_64bits) | |
63b2d2f4 | 1327 | i_ld(p, pte, 0, ptr); |
1da177e4 LT |
1328 | else |
1329 | # endif | |
63b2d2f4 | 1330 | i_LW(p, pte, 0, ptr); |
1da177e4 LT |
1331 | #endif |
1332 | } | |
1333 | ||
1334 | static void __init | |
63b2d2f4 TS |
1335 | iPTE_SW(u32 **p, struct reloc **r, unsigned int pte, unsigned int ptr, |
1336 | unsigned int mode) | |
1da177e4 | 1337 | { |
63b2d2f4 TS |
1338 | #ifdef CONFIG_64BIT_PHYS_ADDR |
1339 | unsigned int hwmode = mode & (_PAGE_VALID | _PAGE_DIRTY); | |
1340 | #endif | |
1341 | ||
1342 | i_ori(p, pte, pte, mode); | |
1da177e4 LT |
1343 | #ifdef CONFIG_SMP |
1344 | # ifdef CONFIG_64BIT_PHYS_ADDR | |
1345 | if (cpu_has_64bits) | |
63b2d2f4 | 1346 | i_scd(p, pte, 0, ptr); |
1da177e4 LT |
1347 | else |
1348 | # endif | |
63b2d2f4 | 1349 | i_SC(p, pte, 0, ptr); |
1da177e4 LT |
1350 | |
1351 | if (r10000_llsc_war()) | |
1352 | il_beqzl(p, r, pte, label_smp_pgtable_change); | |
1353 | else | |
1354 | il_beqz(p, r, pte, label_smp_pgtable_change); | |
1355 | ||
1356 | # ifdef CONFIG_64BIT_PHYS_ADDR | |
1357 | if (!cpu_has_64bits) { | |
1358 | /* no i_nop needed */ | |
1359 | i_ll(p, pte, sizeof(pte_t) / 2, ptr); | |
63b2d2f4 | 1360 | i_ori(p, pte, pte, hwmode); |
1da177e4 LT |
1361 | i_sc(p, pte, sizeof(pte_t) / 2, ptr); |
1362 | il_beqz(p, r, pte, label_smp_pgtable_change); | |
1363 | /* no i_nop needed */ | |
1364 | i_lw(p, pte, 0, ptr); | |
1365 | } else | |
1366 | i_nop(p); | |
1367 | # else | |
1368 | i_nop(p); | |
1369 | # endif | |
1370 | #else | |
1371 | # ifdef CONFIG_64BIT_PHYS_ADDR | |
1372 | if (cpu_has_64bits) | |
63b2d2f4 | 1373 | i_sd(p, pte, 0, ptr); |
1da177e4 LT |
1374 | else |
1375 | # endif | |
63b2d2f4 | 1376 | i_SW(p, pte, 0, ptr); |
1da177e4 LT |
1377 | |
1378 | # ifdef CONFIG_64BIT_PHYS_ADDR | |
1379 | if (!cpu_has_64bits) { | |
1380 | i_lw(p, pte, sizeof(pte_t) / 2, ptr); | |
63b2d2f4 | 1381 | i_ori(p, pte, pte, hwmode); |
1da177e4 LT |
1382 | i_sw(p, pte, sizeof(pte_t) / 2, ptr); |
1383 | i_lw(p, pte, 0, ptr); | |
1384 | } | |
1385 | # endif | |
1386 | #endif | |
1387 | } | |
1388 | ||
1389 | /* | |
1390 | * Check if PTE is present, if not then jump to LABEL. PTR points to | |
1391 | * the page table where this PTE is located, PTE will be re-loaded | |
1392 | * with it's original value. | |
1393 | */ | |
1394 | static void __init | |
1395 | build_pte_present(u32 **p, struct label **l, struct reloc **r, | |
1396 | unsigned int pte, unsigned int ptr, enum label_id lid) | |
1397 | { | |
1398 | i_andi(p, pte, pte, _PAGE_PRESENT | _PAGE_READ); | |
1399 | i_xori(p, pte, pte, _PAGE_PRESENT | _PAGE_READ); | |
1400 | il_bnez(p, r, pte, lid); | |
63b2d2f4 | 1401 | iPTE_LW(p, l, pte, ptr); |
1da177e4 LT |
1402 | } |
1403 | ||
1404 | /* Make PTE valid, store result in PTR. */ | |
1405 | static void __init | |
1406 | build_make_valid(u32 **p, struct reloc **r, unsigned int pte, | |
1407 | unsigned int ptr) | |
1408 | { | |
63b2d2f4 TS |
1409 | unsigned int mode = _PAGE_VALID | _PAGE_ACCESSED; |
1410 | ||
1411 | iPTE_SW(p, r, pte, ptr, mode); | |
1da177e4 LT |
1412 | } |
1413 | ||
1414 | /* | |
1415 | * Check if PTE can be written to, if not branch to LABEL. Regardless | |
1416 | * restore PTE with value from PTR when done. | |
1417 | */ | |
1418 | static void __init | |
1419 | build_pte_writable(u32 **p, struct label **l, struct reloc **r, | |
1420 | unsigned int pte, unsigned int ptr, enum label_id lid) | |
1421 | { | |
1422 | i_andi(p, pte, pte, _PAGE_PRESENT | _PAGE_WRITE); | |
1423 | i_xori(p, pte, pte, _PAGE_PRESENT | _PAGE_WRITE); | |
1424 | il_bnez(p, r, pte, lid); | |
63b2d2f4 | 1425 | iPTE_LW(p, l, pte, ptr); |
1da177e4 LT |
1426 | } |
1427 | ||
1428 | /* Make PTE writable, update software status bits as well, then store | |
1429 | * at PTR. | |
1430 | */ | |
1431 | static void __init | |
1432 | build_make_write(u32 **p, struct reloc **r, unsigned int pte, | |
1433 | unsigned int ptr) | |
1434 | { | |
63b2d2f4 TS |
1435 | unsigned int mode = (_PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID |
1436 | | _PAGE_DIRTY); | |
1437 | ||
1438 | iPTE_SW(p, r, pte, ptr, mode); | |
1da177e4 LT |
1439 | } |
1440 | ||
1441 | /* | |
1442 | * Check if PTE can be modified, if not branch to LABEL. Regardless | |
1443 | * restore PTE with value from PTR when done. | |
1444 | */ | |
1445 | static void __init | |
1446 | build_pte_modifiable(u32 **p, struct label **l, struct reloc **r, | |
1447 | unsigned int pte, unsigned int ptr, enum label_id lid) | |
1448 | { | |
1449 | i_andi(p, pte, pte, _PAGE_WRITE); | |
1450 | il_beqz(p, r, pte, lid); | |
63b2d2f4 | 1451 | iPTE_LW(p, l, pte, ptr); |
1da177e4 LT |
1452 | } |
1453 | ||
1454 | /* | |
1455 | * R3000 style TLB load/store/modify handlers. | |
1456 | */ | |
1457 | ||
fded2e50 MR |
1458 | /* |
1459 | * This places the pte into ENTRYLO0 and writes it with tlbwi. | |
1460 | * Then it returns. | |
1461 | */ | |
1da177e4 | 1462 | static void __init |
fded2e50 | 1463 | build_r3000_pte_reload_tlbwi(u32 **p, unsigned int pte, unsigned int tmp) |
1da177e4 | 1464 | { |
fded2e50 MR |
1465 | i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */ |
1466 | i_mfc0(p, tmp, C0_EPC); /* cp0 delay */ | |
1467 | i_tlbwi(p); | |
1468 | i_jr(p, tmp); | |
1469 | i_rfe(p); /* branch delay */ | |
1da177e4 LT |
1470 | } |
1471 | ||
1472 | /* | |
fded2e50 MR |
1473 | * This places the pte into ENTRYLO0 and writes it with tlbwi |
1474 | * or tlbwr as appropriate. This is because the index register | |
1475 | * may have the probe fail bit set as a result of a trap on a | |
1476 | * kseg2 access, i.e. without refill. Then it returns. | |
1da177e4 LT |
1477 | */ |
1478 | static void __init | |
fded2e50 MR |
1479 | build_r3000_tlb_reload_write(u32 **p, struct label **l, struct reloc **r, |
1480 | unsigned int pte, unsigned int tmp) | |
1da177e4 LT |
1481 | { |
1482 | i_mfc0(p, tmp, C0_INDEX); | |
fded2e50 MR |
1483 | i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */ |
1484 | il_bltz(p, r, tmp, label_r3000_write_probe_fail); /* cp0 delay */ | |
1485 | i_mfc0(p, tmp, C0_EPC); /* branch delay */ | |
1486 | i_tlbwi(p); /* cp0 delay */ | |
1487 | i_jr(p, tmp); | |
1488 | i_rfe(p); /* branch delay */ | |
1da177e4 | 1489 | l_r3000_write_probe_fail(l, *p); |
fded2e50 MR |
1490 | i_tlbwr(p); /* cp0 delay */ |
1491 | i_jr(p, tmp); | |
1492 | i_rfe(p); /* branch delay */ | |
1da177e4 LT |
1493 | } |
1494 | ||
1495 | static void __init | |
1496 | build_r3000_tlbchange_handler_head(u32 **p, unsigned int pte, | |
1497 | unsigned int ptr) | |
1498 | { | |
1499 | long pgdc = (long)pgd_current; | |
1500 | ||
1501 | i_mfc0(p, pte, C0_BADVADDR); | |
1502 | i_lui(p, ptr, rel_hi(pgdc)); /* cp0 delay */ | |
1503 | i_lw(p, ptr, rel_lo(pgdc), ptr); | |
1504 | i_srl(p, pte, pte, 22); /* load delay */ | |
1505 | i_sll(p, pte, pte, 2); | |
1506 | i_addu(p, ptr, ptr, pte); | |
1507 | i_mfc0(p, pte, C0_CONTEXT); | |
1508 | i_lw(p, ptr, 0, ptr); /* cp0 delay */ | |
1509 | i_andi(p, pte, pte, 0xffc); /* load delay */ | |
1510 | i_addu(p, ptr, ptr, pte); | |
1511 | i_lw(p, pte, 0, ptr); | |
fded2e50 | 1512 | i_tlbp(p); /* load delay */ |
1da177e4 LT |
1513 | } |
1514 | ||
1515 | static void __init build_r3000_tlb_load_handler(void) | |
1516 | { | |
1517 | u32 *p = handle_tlbl; | |
1518 | struct label *l = labels; | |
1519 | struct reloc *r = relocs; | |
115f2a44 | 1520 | int i; |
1da177e4 LT |
1521 | |
1522 | memset(handle_tlbl, 0, sizeof(handle_tlbl)); | |
1523 | memset(labels, 0, sizeof(labels)); | |
1524 | memset(relocs, 0, sizeof(relocs)); | |
1525 | ||
1526 | build_r3000_tlbchange_handler_head(&p, K0, K1); | |
1527 | build_pte_present(&p, &l, &r, K0, K1, label_nopage_tlbl); | |
d925c262 | 1528 | i_nop(&p); /* load delay */ |
1da177e4 | 1529 | build_make_valid(&p, &r, K0, K1); |
fded2e50 | 1530 | build_r3000_tlb_reload_write(&p, &l, &r, K0, K1); |
1da177e4 LT |
1531 | |
1532 | l_nopage_tlbl(&l, p); | |
1533 | i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff); | |
1534 | i_nop(&p); | |
1535 | ||
1536 | if ((p - handle_tlbl) > FASTPATH_SIZE) | |
1537 | panic("TLB load handler fastpath space exceeded"); | |
1538 | ||
1539 | resolve_relocs(relocs, labels); | |
115f2a44 TS |
1540 | pr_info("Synthesized TLB load handler fastpath (%u instructions).\n", |
1541 | (unsigned int)(p - handle_tlbl)); | |
1da177e4 | 1542 | |
115f2a44 TS |
1543 | pr_debug("\t.set push\n"); |
1544 | pr_debug("\t.set noreorder\n"); | |
1545 | for (i = 0; i < (p - handle_tlbl); i++) | |
1546 | pr_debug("\t.word 0x%08x\n", handle_tlbl[i]); | |
1547 | pr_debug("\t.set pop\n"); | |
1da177e4 LT |
1548 | } |
1549 | ||
1550 | static void __init build_r3000_tlb_store_handler(void) | |
1551 | { | |
1552 | u32 *p = handle_tlbs; | |
1553 | struct label *l = labels; | |
1554 | struct reloc *r = relocs; | |
115f2a44 | 1555 | int i; |
1da177e4 LT |
1556 | |
1557 | memset(handle_tlbs, 0, sizeof(handle_tlbs)); | |
1558 | memset(labels, 0, sizeof(labels)); | |
1559 | memset(relocs, 0, sizeof(relocs)); | |
1560 | ||
1561 | build_r3000_tlbchange_handler_head(&p, K0, K1); | |
1562 | build_pte_writable(&p, &l, &r, K0, K1, label_nopage_tlbs); | |
d925c262 | 1563 | i_nop(&p); /* load delay */ |
1da177e4 | 1564 | build_make_write(&p, &r, K0, K1); |
fded2e50 | 1565 | build_r3000_tlb_reload_write(&p, &l, &r, K0, K1); |
1da177e4 LT |
1566 | |
1567 | l_nopage_tlbs(&l, p); | |
1568 | i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); | |
1569 | i_nop(&p); | |
1570 | ||
1571 | if ((p - handle_tlbs) > FASTPATH_SIZE) | |
1572 | panic("TLB store handler fastpath space exceeded"); | |
1573 | ||
1574 | resolve_relocs(relocs, labels); | |
115f2a44 TS |
1575 | pr_info("Synthesized TLB store handler fastpath (%u instructions).\n", |
1576 | (unsigned int)(p - handle_tlbs)); | |
1da177e4 | 1577 | |
115f2a44 TS |
1578 | pr_debug("\t.set push\n"); |
1579 | pr_debug("\t.set noreorder\n"); | |
1580 | for (i = 0; i < (p - handle_tlbs); i++) | |
1581 | pr_debug("\t.word 0x%08x\n", handle_tlbs[i]); | |
1582 | pr_debug("\t.set pop\n"); | |
1da177e4 LT |
1583 | } |
1584 | ||
1585 | static void __init build_r3000_tlb_modify_handler(void) | |
1586 | { | |
1587 | u32 *p = handle_tlbm; | |
1588 | struct label *l = labels; | |
1589 | struct reloc *r = relocs; | |
115f2a44 | 1590 | int i; |
1da177e4 LT |
1591 | |
1592 | memset(handle_tlbm, 0, sizeof(handle_tlbm)); | |
1593 | memset(labels, 0, sizeof(labels)); | |
1594 | memset(relocs, 0, sizeof(relocs)); | |
1595 | ||
1596 | build_r3000_tlbchange_handler_head(&p, K0, K1); | |
1597 | build_pte_modifiable(&p, &l, &r, K0, K1, label_nopage_tlbm); | |
d925c262 | 1598 | i_nop(&p); /* load delay */ |
1da177e4 | 1599 | build_make_write(&p, &r, K0, K1); |
fded2e50 | 1600 | build_r3000_pte_reload_tlbwi(&p, K0, K1); |
1da177e4 LT |
1601 | |
1602 | l_nopage_tlbm(&l, p); | |
1603 | i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); | |
1604 | i_nop(&p); | |
1605 | ||
1606 | if ((p - handle_tlbm) > FASTPATH_SIZE) | |
1607 | panic("TLB modify handler fastpath space exceeded"); | |
1608 | ||
1609 | resolve_relocs(relocs, labels); | |
115f2a44 TS |
1610 | pr_info("Synthesized TLB modify handler fastpath (%u instructions).\n", |
1611 | (unsigned int)(p - handle_tlbm)); | |
1da177e4 | 1612 | |
115f2a44 TS |
1613 | pr_debug("\t.set push\n"); |
1614 | pr_debug("\t.set noreorder\n"); | |
1615 | for (i = 0; i < (p - handle_tlbm); i++) | |
1616 | pr_debug("\t.word 0x%08x\n", handle_tlbm[i]); | |
1617 | pr_debug("\t.set pop\n"); | |
1da177e4 LT |
1618 | } |
1619 | ||
1620 | /* | |
1621 | * R4000 style TLB load/store/modify handlers. | |
1622 | */ | |
1623 | static void __init | |
1624 | build_r4000_tlbchange_handler_head(u32 **p, struct label **l, | |
1625 | struct reloc **r, unsigned int pte, | |
1626 | unsigned int ptr) | |
1627 | { | |
875d43e7 | 1628 | #ifdef CONFIG_64BIT |
1da177e4 LT |
1629 | build_get_pmde64(p, l, r, pte, ptr); /* get pmd in ptr */ |
1630 | #else | |
1631 | build_get_pgde32(p, pte, ptr); /* get pgd in ptr */ | |
1632 | #endif | |
1633 | ||
1634 | i_MFC0(p, pte, C0_BADVADDR); | |
1635 | i_LW(p, ptr, 0, ptr); | |
1636 | i_SRL(p, pte, pte, PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2); | |
1637 | i_andi(p, pte, pte, (PTRS_PER_PTE - 1) << PTE_T_LOG2); | |
1638 | i_ADDU(p, ptr, ptr, pte); | |
1639 | ||
1640 | #ifdef CONFIG_SMP | |
1641 | l_smp_pgtable_change(l, *p); | |
1642 | # endif | |
63b2d2f4 | 1643 | iPTE_LW(p, l, pte, ptr); /* get even pte */ |
1da177e4 LT |
1644 | build_tlb_probe_entry(p); |
1645 | } | |
1646 | ||
1647 | static void __init | |
1648 | build_r4000_tlbchange_handler_tail(u32 **p, struct label **l, | |
1649 | struct reloc **r, unsigned int tmp, | |
1650 | unsigned int ptr) | |
1651 | { | |
1652 | i_ori(p, ptr, ptr, sizeof(pte_t)); | |
1653 | i_xori(p, ptr, ptr, sizeof(pte_t)); | |
1654 | build_update_entries(p, tmp, ptr); | |
1655 | build_tlb_write_entry(p, l, r, tlb_indexed); | |
1656 | l_leave(l, *p); | |
1657 | i_eret(p); /* return from trap */ | |
1658 | ||
875d43e7 | 1659 | #ifdef CONFIG_64BIT |
1da177e4 LT |
1660 | build_get_pgd_vmalloc64(p, l, r, tmp, ptr); |
1661 | #endif | |
1662 | } | |
1663 | ||
1664 | static void __init build_r4000_tlb_load_handler(void) | |
1665 | { | |
1666 | u32 *p = handle_tlbl; | |
1667 | struct label *l = labels; | |
1668 | struct reloc *r = relocs; | |
115f2a44 | 1669 | int i; |
1da177e4 LT |
1670 | |
1671 | memset(handle_tlbl, 0, sizeof(handle_tlbl)); | |
1672 | memset(labels, 0, sizeof(labels)); | |
1673 | memset(relocs, 0, sizeof(relocs)); | |
1674 | ||
1675 | if (bcm1250_m3_war()) { | |
1676 | i_MFC0(&p, K0, C0_BADVADDR); | |
1677 | i_MFC0(&p, K1, C0_ENTRYHI); | |
1678 | i_xor(&p, K0, K0, K1); | |
1679 | i_SRL(&p, K0, K0, PAGE_SHIFT + 1); | |
1680 | il_bnez(&p, &r, K0, label_leave); | |
1681 | /* No need for i_nop */ | |
1682 | } | |
1683 | ||
1684 | build_r4000_tlbchange_handler_head(&p, &l, &r, K0, K1); | |
1685 | build_pte_present(&p, &l, &r, K0, K1, label_nopage_tlbl); | |
1686 | build_make_valid(&p, &r, K0, K1); | |
1687 | build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1); | |
1688 | ||
1689 | l_nopage_tlbl(&l, p); | |
1690 | i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff); | |
1691 | i_nop(&p); | |
1692 | ||
1693 | if ((p - handle_tlbl) > FASTPATH_SIZE) | |
1694 | panic("TLB load handler fastpath space exceeded"); | |
1695 | ||
1696 | resolve_relocs(relocs, labels); | |
115f2a44 TS |
1697 | pr_info("Synthesized TLB load handler fastpath (%u instructions).\n", |
1698 | (unsigned int)(p - handle_tlbl)); | |
1da177e4 | 1699 | |
115f2a44 TS |
1700 | pr_debug("\t.set push\n"); |
1701 | pr_debug("\t.set noreorder\n"); | |
1702 | for (i = 0; i < (p - handle_tlbl); i++) | |
1703 | pr_debug("\t.word 0x%08x\n", handle_tlbl[i]); | |
1704 | pr_debug("\t.set pop\n"); | |
1da177e4 LT |
1705 | } |
1706 | ||
1707 | static void __init build_r4000_tlb_store_handler(void) | |
1708 | { | |
1709 | u32 *p = handle_tlbs; | |
1710 | struct label *l = labels; | |
1711 | struct reloc *r = relocs; | |
115f2a44 | 1712 | int i; |
1da177e4 LT |
1713 | |
1714 | memset(handle_tlbs, 0, sizeof(handle_tlbs)); | |
1715 | memset(labels, 0, sizeof(labels)); | |
1716 | memset(relocs, 0, sizeof(relocs)); | |
1717 | ||
1718 | build_r4000_tlbchange_handler_head(&p, &l, &r, K0, K1); | |
1719 | build_pte_writable(&p, &l, &r, K0, K1, label_nopage_tlbs); | |
1720 | build_make_write(&p, &r, K0, K1); | |
1721 | build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1); | |
1722 | ||
1723 | l_nopage_tlbs(&l, p); | |
1724 | i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); | |
1725 | i_nop(&p); | |
1726 | ||
1727 | if ((p - handle_tlbs) > FASTPATH_SIZE) | |
1728 | panic("TLB store handler fastpath space exceeded"); | |
1729 | ||
1730 | resolve_relocs(relocs, labels); | |
115f2a44 TS |
1731 | pr_info("Synthesized TLB store handler fastpath (%u instructions).\n", |
1732 | (unsigned int)(p - handle_tlbs)); | |
1da177e4 | 1733 | |
115f2a44 TS |
1734 | pr_debug("\t.set push\n"); |
1735 | pr_debug("\t.set noreorder\n"); | |
1736 | for (i = 0; i < (p - handle_tlbs); i++) | |
1737 | pr_debug("\t.word 0x%08x\n", handle_tlbs[i]); | |
1738 | pr_debug("\t.set pop\n"); | |
1da177e4 LT |
1739 | } |
1740 | ||
1741 | static void __init build_r4000_tlb_modify_handler(void) | |
1742 | { | |
1743 | u32 *p = handle_tlbm; | |
1744 | struct label *l = labels; | |
1745 | struct reloc *r = relocs; | |
115f2a44 | 1746 | int i; |
1da177e4 LT |
1747 | |
1748 | memset(handle_tlbm, 0, sizeof(handle_tlbm)); | |
1749 | memset(labels, 0, sizeof(labels)); | |
1750 | memset(relocs, 0, sizeof(relocs)); | |
1751 | ||
1752 | build_r4000_tlbchange_handler_head(&p, &l, &r, K0, K1); | |
1753 | build_pte_modifiable(&p, &l, &r, K0, K1, label_nopage_tlbm); | |
1754 | /* Present and writable bits set, set accessed and dirty bits. */ | |
1755 | build_make_write(&p, &r, K0, K1); | |
1756 | build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1); | |
1757 | ||
1758 | l_nopage_tlbm(&l, p); | |
1759 | i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); | |
1760 | i_nop(&p); | |
1761 | ||
1762 | if ((p - handle_tlbm) > FASTPATH_SIZE) | |
1763 | panic("TLB modify handler fastpath space exceeded"); | |
1764 | ||
1765 | resolve_relocs(relocs, labels); | |
115f2a44 TS |
1766 | pr_info("Synthesized TLB modify handler fastpath (%u instructions).\n", |
1767 | (unsigned int)(p - handle_tlbm)); | |
1768 | ||
1769 | pr_debug("\t.set push\n"); | |
1770 | pr_debug("\t.set noreorder\n"); | |
1771 | for (i = 0; i < (p - handle_tlbm); i++) | |
1772 | pr_debug("\t.word 0x%08x\n", handle_tlbm[i]); | |
1773 | pr_debug("\t.set pop\n"); | |
1da177e4 LT |
1774 | } |
1775 | ||
1776 | void __init build_tlb_refill_handler(void) | |
1777 | { | |
1778 | /* | |
1779 | * The refill handler is generated per-CPU, multi-node systems | |
1780 | * may have local storage for it. The other handlers are only | |
1781 | * needed once. | |
1782 | */ | |
1783 | static int run_once = 0; | |
1784 | ||
1785 | switch (current_cpu_data.cputype) { | |
1786 | case CPU_R2000: | |
1787 | case CPU_R3000: | |
1788 | case CPU_R3000A: | |
1789 | case CPU_R3081E: | |
1790 | case CPU_TX3912: | |
1791 | case CPU_TX3922: | |
1792 | case CPU_TX3927: | |
1793 | build_r3000_tlb_refill_handler(); | |
1794 | if (!run_once) { | |
1795 | build_r3000_tlb_load_handler(); | |
1796 | build_r3000_tlb_store_handler(); | |
1797 | build_r3000_tlb_modify_handler(); | |
1798 | run_once++; | |
1799 | } | |
1800 | break; | |
1801 | ||
1802 | case CPU_R6000: | |
1803 | case CPU_R6000A: | |
1804 | panic("No R6000 TLB refill handler yet"); | |
1805 | break; | |
1806 | ||
1807 | case CPU_R8000: | |
1808 | panic("No R8000 TLB refill handler yet"); | |
1809 | break; | |
1810 | ||
1811 | default: | |
1812 | build_r4000_tlb_refill_handler(); | |
1813 | if (!run_once) { | |
1814 | build_r4000_tlb_load_handler(); | |
1815 | build_r4000_tlb_store_handler(); | |
1816 | build_r4000_tlb_modify_handler(); | |
1817 | run_once++; | |
1818 | } | |
1819 | } | |
1820 | } | |
1d40cfcd RB |
1821 | |
1822 | void __init flush_tlb_handlers(void) | |
1823 | { | |
1824 | flush_icache_range((unsigned long)handle_tlbl, | |
1825 | (unsigned long)handle_tlbl + sizeof(handle_tlbl)); | |
1826 | flush_icache_range((unsigned long)handle_tlbs, | |
1827 | (unsigned long)handle_tlbs + sizeof(handle_tlbs)); | |
1828 | flush_icache_range((unsigned long)handle_tlbm, | |
1829 | (unsigned long)handle_tlbm + sizeof(handle_tlbm)); | |
1830 | } |