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Merge branch 'lazytime' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs
[deliverable/linux.git] / arch / mips / mm / uasm-mips.c
CommitLineData
abc597fe
SH		 1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * A small micro-assembler. It is intentionally kept simple, does only
7 * support a subset of instructions, and does not try to hide pipeline
8 * effects like branch delay slots.
9 *
10 * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer
11 * Copyright (C) 2005, 2007 Maciej W. Rozycki
12 * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
13 * Copyright (C) 2012, 2013 MIPS Technologies, Inc. All rights reserved.
14 */
15
16#include <linux/kernel.h>
17#include <linux/types.h>
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SH		 18
19#include <asm/inst.h>
20#include <asm/elf.h>
21#include <asm/bugs.h>
cf6d9058 22#define UASM_ISA _UASM_ISA_CLASSIC
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SH		 23#include <asm/uasm.h>
24
25#define RS_MASK 0x1f
26#define RS_SH 21
27#define RT_MASK 0x1f
28#define RT_SH 16
29#define SCIMM_MASK 0xfffff
30#define SCIMM_SH 6
31
32/* This macro sets the non-variable bits of an instruction. */
33#define M(a, b, c, d, e, f) \
34 ((a) << OP_SH \
35 | (b) << RS_SH \
36 | (c) << RT_SH \
37 | (d) << RD_SH \
38 | (e) << RE_SH \
39 | (f) << FUNC_SH)
40
cf6d9058
SH		 41/* Define these when we are not the ISA the kernel is being compiled with. */
42#ifdef CONFIG_CPU_MICROMIPS
43#define CL_uasm_i_b(buf, off) ISAOPC(_beq)(buf, 0, 0, off)
44#define CL_uasm_i_beqz(buf, rs, off) ISAOPC(_beq)(buf, rs, 0, off)
45#define CL_uasm_i_beqzl(buf, rs, off) ISAOPC(_beql)(buf, rs, 0, off)
46#define CL_uasm_i_bnez(buf, rs, off) ISAOPC(_bne)(buf, rs, 0, off)
47#endif
48
abc597fe
SH		 49#include "uasm.c"
50
078a55fc 51static struct insn insn_table[] = {
abc597fe
SH		 52 { insn_addiu, M(addiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
53 { insn_addu, M(spec_op, 0, 0, 0, 0, addu_op), RS | RT | RD },
54 { insn_andi, M(andi_op, 0, 0, 0, 0, 0), RS | RT | UIMM },
55 { insn_and, M(spec_op, 0, 0, 0, 0, and_op), RS | RT | RD },
56 { insn_bbit0, M(lwc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
57 { insn_bbit1, M(swc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
58 { insn_beql, M(beql_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
59 { insn_beq, M(beq_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
60 { insn_bgezl, M(bcond_op, 0, bgezl_op, 0, 0, 0), RS | BIMM },
61 { insn_bgez, M(bcond_op, 0, bgez_op, 0, 0, 0), RS | BIMM },
62 { insn_bltzl, M(bcond_op, 0, bltzl_op, 0, 0, 0), RS | BIMM },
63 { insn_bltz, M(bcond_op, 0, bltz_op, 0, 0, 0), RS | BIMM },
64 { insn_bne, M(bne_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
65 { insn_cache, M(cache_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
66 { insn_daddiu, M(daddiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
67 { insn_daddu, M(spec_op, 0, 0, 0, 0, daddu_op), RS | RT | RD },
68 { insn_dinsm, M(spec3_op, 0, 0, 0, 0, dinsm_op), RS | RT | RD | RE },
69 { insn_dins, M(spec3_op, 0, 0, 0, 0, dins_op), RS | RT | RD | RE },
4c12a854 70 { insn_divu, M(spec_op, 0, 0, 0, 0, divu_op), RS | RT },
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SH		 71 { insn_dmfc0, M(cop0_op, dmfc_op, 0, 0, 0, 0), RT | RD | SET},
72 { insn_dmtc0, M(cop0_op, dmtc_op, 0, 0, 0, 0), RT | RD | SET},
73 { insn_drotr32, M(spec_op, 1, 0, 0, 0, dsrl32_op), RT | RD | RE },
74 { insn_drotr, M(spec_op, 1, 0, 0, 0, dsrl_op), RT | RD | RE },
75 { insn_dsll32, M(spec_op, 0, 0, 0, 0, dsll32_op), RT | RD | RE },
76 { insn_dsll, M(spec_op, 0, 0, 0, 0, dsll_op), RT | RD | RE },
77 { insn_dsra, M(spec_op, 0, 0, 0, 0, dsra_op), RT | RD | RE },
78 { insn_dsrl32, M(spec_op, 0, 0, 0, 0, dsrl32_op), RT | RD | RE },
79 { insn_dsrl, M(spec_op, 0, 0, 0, 0, dsrl_op), RT | RD | RE },
80 { insn_dsubu, M(spec_op, 0, 0, 0, 0, dsubu_op), RS | RT | RD },
81 { insn_eret, M(cop0_op, cop_op, 0, 0, 0, eret_op), 0 },
82 { insn_ext, M(spec3_op, 0, 0, 0, 0, ext_op), RS | RT | RD | RE },
83 { insn_ins, M(spec3_op, 0, 0, 0, 0, ins_op), RS | RT | RD | RE },
84 { insn_j, M(j_op, 0, 0, 0, 0, 0), JIMM },
85 { insn_jal, M(jal_op, 0, 0, 0, 0, 0), JIMM },
49e9529b 86 { insn_jalr, M(spec_op, 0, 0, 0, 0, jalr_op), RS | RD },
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SH		 87 { insn_j, M(j_op, 0, 0, 0, 0, 0), JIMM },
88 { insn_jr, M(spec_op, 0, 0, 0, 0, jr_op), RS },
82488818 89 { insn_lb, M(lb_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
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SH		 90 { insn_ld, M(ld_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
91 { insn_ldx, M(spec3_op, 0, 0, 0, ldx_op, lx_op), RS | RT | RD },
84c68cbc 92 { insn_lh, M(lh_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
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SH		 93 { insn_lld, M(lld_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
94 { insn_ll, M(ll_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
95 { insn_lui, M(lui_op, 0, 0, 0, 0, 0), RT | SIMM },
96 { insn_lw, M(lw_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
97 { insn_lwx, M(spec3_op, 0, 0, 0, lwx_op, lx_op), RS | RT | RD },
98 { insn_mfc0, M(cop0_op, mfc_op, 0, 0, 0, 0), RT | RD | SET},
e2965cd0 99 { insn_mfhc0, M(cop0_op, mfhc0_op, 0, 0, 0, 0), RT | RD | SET},
f3ec7a23 100 { insn_mfhi, M(spec_op, 0, 0, 0, 0, mfhi_op), RD },
16d21a81 101 { insn_mflo, M(spec_op, 0, 0, 0, 0, mflo_op), RD },
abc597fe 102 { insn_mtc0, M(cop0_op, mtc_op, 0, 0, 0, 0), RT | RD | SET},
e2965cd0 103 { insn_mthc0, M(cop0_op, mthc0_op, 0, 0, 0, 0), RT | RD | SET},
a8e897ad 104 { insn_mul, M(spec2_op, 0, 0, 0, 0, mul_op), RS | RT | RD},
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SH		 105 { insn_ori, M(ori_op, 0, 0, 0, 0, 0), RS | RT | UIMM },
106 { insn_or, M(spec_op, 0, 0, 0, 0, or_op), RS | RT | RD },
107 { insn_pref, M(pref_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
108 { insn_rfe, M(cop0_op, cop_op, 0, 0, 0, rfe_op), 0 },
109 { insn_rotr, M(spec_op, 1, 0, 0, 0, srl_op), RT | RD | RE },
110 { insn_scd, M(scd_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
111 { insn_sc, M(sc_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
112 { insn_sd, M(sd_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
113 { insn_sll, M(spec_op, 0, 0, 0, 0, sll_op), RT | RD | RE },
bef581ba 114 { insn_sllv, M(spec_op, 0, 0, 0, 0, sllv_op), RS | RT | RD },
7682f9e8 115 { insn_slt, M(spec_op, 0, 0, 0, 0, slt_op), RS | RT | RD },
390363ed 116 { insn_sltiu, M(sltiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
e8ef868b 117 { insn_sltu, M(spec_op, 0, 0, 0, 0, sltu_op), RS | RT | RD },
abc597fe
SH		 118 { insn_sra, M(spec_op, 0, 0, 0, 0, sra_op), RT | RD | RE },
119 { insn_srl, M(spec_op, 0, 0, 0, 0, srl_op), RT | RD | RE },
f31318fd 120 { insn_srlv, M(spec_op, 0, 0, 0, 0, srlv_op), RS | RT | RD },
abc597fe
SH		 121 { insn_subu, M(spec_op, 0, 0, 0, 0, subu_op), RS | RT | RD },
122 { insn_sw, M(sw_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
729ff561 123 { insn_sync, M(spec_op, 0, 0, 0, 0, sync_op), RE },
abc597fe
SH		 124 { insn_syscall, M(spec_op, 0, 0, 0, 0, syscall_op), SCIMM},
125 { insn_tlbp, M(cop0_op, cop_op, 0, 0, 0, tlbp_op), 0 },
126 { insn_tlbr, M(cop0_op, cop_op, 0, 0, 0, tlbr_op), 0 },
127 { insn_tlbwi, M(cop0_op, cop_op, 0, 0, 0, tlbwi_op), 0 },
128 { insn_tlbwr, M(cop0_op, cop_op, 0, 0, 0, tlbwr_op), 0 },
53ed1389 129 { insn_wait, M(cop0_op, cop_op, 0, 0, 0, wait_op), SCIMM },
ab9e4fa0 130 { insn_wsbh, M(spec3_op, 0, 0, 0, wsbh_op, bshfl_op), RT | RD },
abc597fe
SH		 131 { insn_xori, M(xori_op, 0, 0, 0, 0, 0), RS | RT | UIMM },
132 { insn_xor, M(spec_op, 0, 0, 0, 0, xor_op), RS | RT | RD },
d674dd14 133 { insn_yield, M(spec3_op, 0, 0, 0, 0, yield_op), RS | RD },
abc597fe
SH		 134 { insn_invalid, 0, 0 }
135};
136
137#undef M
138
078a55fc 139static inline u32 build_bimm(s32 arg)
abc597fe
SH		 140{
141 WARN(arg > 0x1ffff || arg < -0x20000,
142 KERN_WARNING "Micro-assembler field overflow\n");
143
144 WARN(arg & 0x3, KERN_WARNING "Invalid micro-assembler branch target\n");
145
146 return ((arg < 0) ? (1 << 15) : 0) | ((arg >> 2) & 0x7fff);
147}
148
078a55fc 149static inline u32 build_jimm(u32 arg)
abc597fe
SH		 150{
151 WARN(arg & ~(JIMM_MASK << 2),
152 KERN_WARNING "Micro-assembler field overflow\n");
153
154 return (arg >> 2) & JIMM_MASK;
155}
156
157/*
158 * The order of opcode arguments is implicitly left to right,
159 * starting with RS and ending with FUNC or IMM.
160 */
078a55fc 161static void build_insn(u32 **buf, enum opcode opc, ...)
abc597fe
SH		 162{
163 struct insn *ip = NULL;
164 unsigned int i;
165 va_list ap;
166 u32 op;
167
168 for (i = 0; insn_table[i].opcode != insn_invalid; i++)
169 if (insn_table[i].opcode == opc) {
170 ip = &insn_table[i];
171 break;
172 }
173
174 if (!ip || (opc == insn_daddiu && r4k_daddiu_bug()))
175 panic("Unsupported Micro-assembler instruction %d", opc);
176
177 op = ip->match;
178 va_start(ap, opc);
179 if (ip->fields & RS)
180 op |= build_rs(va_arg(ap, u32));
181 if (ip->fields & RT)
182 op |= build_rt(va_arg(ap, u32));
183 if (ip->fields & RD)
184 op |= build_rd(va_arg(ap, u32));
185 if (ip->fields & RE)
186 op |= build_re(va_arg(ap, u32));
187 if (ip->fields & SIMM)
188 op |= build_simm(va_arg(ap, s32));
189 if (ip->fields & UIMM)
190 op |= build_uimm(va_arg(ap, u32));
191 if (ip->fields & BIMM)
192 op |= build_bimm(va_arg(ap, s32));
193 if (ip->fields & JIMM)
194 op |= build_jimm(va_arg(ap, u32));
195 if (ip->fields & FUNC)
196 op |= build_func(va_arg(ap, u32));
197 if (ip->fields & SET)
198 op |= build_set(va_arg(ap, u32));
199 if (ip->fields & SCIMM)
200 op |= build_scimm(va_arg(ap, u32));
201 va_end(ap);
202
203 **buf = op;
204 (*buf)++;
205}
206
078a55fc 207static inline void
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SH		 208__resolve_relocs(struct uasm_reloc *rel, struct uasm_label *lab)
209{
210 long laddr = (long)lab->addr;
211 long raddr = (long)rel->addr;
212
213 switch (rel->type) {
214 case R_MIPS_PC16:
215 *rel->addr |= build_bimm(laddr - (raddr + 4));
216 break;
217
218 default:
219 panic("Unsupported Micro-assembler relocation %d",
220 rel->type);
221 }
222}
Linux kernel - Deliverables
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