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e30ec452 TS |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * A small micro-assembler. It is intentionally kept simple, does only | |
7 | * support a subset of instructions, and does not try to hide pipeline | |
8 | * effects like branch delay slots. | |
9 | * | |
70342287 | 10 | * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer |
e30ec452 TS |
11 | * Copyright (C) 2005, 2007 Maciej W. Rozycki |
12 | * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org) | |
abc597fe | 13 | * Copyright (C) 2012, 2013 MIPS Technologies, Inc. All rights reserved. |
e30ec452 TS |
14 | */ |
15 | ||
e30ec452 TS |
16 | enum fields { |
17 | RS = 0x001, | |
18 | RT = 0x002, | |
19 | RD = 0x004, | |
20 | RE = 0x008, | |
21 | SIMM = 0x010, | |
22 | UIMM = 0x020, | |
23 | BIMM = 0x040, | |
24 | JIMM = 0x080, | |
25 | FUNC = 0x100, | |
58b9e223 | 26 | SET = 0x200, |
51eec48e LY |
27 | SCIMM = 0x400, |
28 | SIMM9 = 0x800, | |
e30ec452 TS |
29 | }; |
30 | ||
31 | #define OP_MASK 0x3f | |
32 | #define OP_SH 26 | |
e30ec452 TS |
33 | #define RD_MASK 0x1f |
34 | #define RD_SH 11 | |
35 | #define RE_MASK 0x1f | |
36 | #define RE_SH 6 | |
37 | #define IMM_MASK 0xffff | |
38 | #define IMM_SH 0 | |
39 | #define JIMM_MASK 0x3ffffff | |
40 | #define JIMM_SH 0 | |
41 | #define FUNC_MASK 0x3f | |
42 | #define FUNC_SH 0 | |
43 | #define SET_MASK 0x7 | |
44 | #define SET_SH 0 | |
51eec48e LY |
45 | #define SIMM9_SH 7 |
46 | #define SIMM9_MASK 0x1ff | |
e30ec452 TS |
47 | |
48 | enum opcode { | |
49 | insn_invalid, | |
71a1c776 SH |
50 | insn_addiu, insn_addu, insn_and, insn_andi, insn_bbit0, insn_bbit1, |
51 | insn_beq, insn_beql, insn_bgez, insn_bgezl, insn_bltz, insn_bltzl, | |
52 | insn_bne, insn_cache, insn_daddiu, insn_daddu, insn_dins, insn_dinsm, | |
4c12a854 | 53 | insn_divu, insn_dmfc0, insn_dmtc0, insn_drotr, insn_drotr32, insn_dsll, |
71a1c776 | 54 | insn_dsll32, insn_dsra, insn_dsrl, insn_dsrl32, insn_dsubu, insn_eret, |
82488818 MC |
55 | insn_ext, insn_ins, insn_j, insn_jal, insn_jalr, insn_jr, insn_lb, |
56 | insn_ld, insn_ldx, insn_lh, insn_ll, insn_lld, insn_lui, insn_lw, | |
e2965cd0 SH |
57 | insn_lwx, insn_mfc0, insn_mfhc0, insn_mfhi, insn_mflo, insn_mtc0, |
58 | insn_mthc0, insn_mul, insn_or, insn_ori, insn_pref, insn_rfe, | |
59 | insn_rotr, insn_sc, insn_scd, insn_sd, insn_sll, insn_sllv, insn_slt, | |
60 | insn_sltiu, insn_sltu, insn_sra, insn_srl, insn_srlv, insn_subu, | |
61 | insn_sw, insn_sync, insn_syscall, insn_tlbp, insn_tlbr, insn_tlbwi, | |
62 | insn_tlbwr, insn_wait, insn_wsbh, insn_xor, insn_xori, insn_yield, | |
e30ec452 TS |
63 | }; |
64 | ||
65 | struct insn { | |
66 | enum opcode opcode; | |
67 | u32 match; | |
68 | enum fields fields; | |
69 | }; | |
70 | ||
078a55fc | 71 | static inline u32 build_rs(u32 arg) |
e30ec452 | 72 | { |
8d662c8d | 73 | WARN(arg & ~RS_MASK, KERN_WARNING "Micro-assembler field overflow\n"); |
e30ec452 TS |
74 | |
75 | return (arg & RS_MASK) << RS_SH; | |
76 | } | |
77 | ||
078a55fc | 78 | static inline u32 build_rt(u32 arg) |
e30ec452 | 79 | { |
8d662c8d | 80 | WARN(arg & ~RT_MASK, KERN_WARNING "Micro-assembler field overflow\n"); |
e30ec452 TS |
81 | |
82 | return (arg & RT_MASK) << RT_SH; | |
83 | } | |
84 | ||
078a55fc | 85 | static inline u32 build_rd(u32 arg) |
e30ec452 | 86 | { |
8d662c8d | 87 | WARN(arg & ~RD_MASK, KERN_WARNING "Micro-assembler field overflow\n"); |
e30ec452 TS |
88 | |
89 | return (arg & RD_MASK) << RD_SH; | |
90 | } | |
91 | ||
078a55fc | 92 | static inline u32 build_re(u32 arg) |
e30ec452 | 93 | { |
8d662c8d | 94 | WARN(arg & ~RE_MASK, KERN_WARNING "Micro-assembler field overflow\n"); |
e30ec452 TS |
95 | |
96 | return (arg & RE_MASK) << RE_SH; | |
97 | } | |
98 | ||
078a55fc | 99 | static inline u32 build_simm(s32 arg) |
e30ec452 | 100 | { |
8d662c8d DD |
101 | WARN(arg > 0x7fff || arg < -0x8000, |
102 | KERN_WARNING "Micro-assembler field overflow\n"); | |
e30ec452 TS |
103 | |
104 | return arg & 0xffff; | |
105 | } | |
106 | ||
078a55fc | 107 | static inline u32 build_uimm(u32 arg) |
e30ec452 | 108 | { |
8d662c8d | 109 | WARN(arg & ~IMM_MASK, KERN_WARNING "Micro-assembler field overflow\n"); |
e30ec452 TS |
110 | |
111 | return arg & IMM_MASK; | |
112 | } | |
113 | ||
078a55fc | 114 | static inline u32 build_scimm(u32 arg) |
58b9e223 | 115 | { |
8d662c8d DD |
116 | WARN(arg & ~SCIMM_MASK, |
117 | KERN_WARNING "Micro-assembler field overflow\n"); | |
58b9e223 DD |
118 | |
119 | return (arg & SCIMM_MASK) << SCIMM_SH; | |
120 | } | |
121 | ||
51eec48e LY |
122 | static inline u32 build_scimm9(s32 arg) |
123 | { | |
124 | WARN((arg > 0xff || arg < -0x100), | |
125 | KERN_WARNING "Micro-assembler field overflow\n"); | |
126 | ||
127 | return (arg & SIMM9_MASK) << SIMM9_SH; | |
128 | } | |
129 | ||
078a55fc | 130 | static inline u32 build_func(u32 arg) |
e30ec452 | 131 | { |
8d662c8d | 132 | WARN(arg & ~FUNC_MASK, KERN_WARNING "Micro-assembler field overflow\n"); |
e30ec452 TS |
133 | |
134 | return arg & FUNC_MASK; | |
135 | } | |
136 | ||
078a55fc | 137 | static inline u32 build_set(u32 arg) |
e30ec452 | 138 | { |
8d662c8d | 139 | WARN(arg & ~SET_MASK, KERN_WARNING "Micro-assembler field overflow\n"); |
e30ec452 TS |
140 | |
141 | return arg & SET_MASK; | |
142 | } | |
143 | ||
078a55fc | 144 | static void build_insn(u32 **buf, enum opcode opc, ...); |
e30ec452 TS |
145 | |
146 | #define I_u1u2u3(op) \ | |
147 | Ip_u1u2u3(op) \ | |
148 | { \ | |
149 | build_insn(buf, insn##op, a, b, c); \ | |
22b0763a DD |
150 | } \ |
151 | UASM_EXPORT_SYMBOL(uasm_i##op); | |
e30ec452 | 152 | |
9d987369 MC |
153 | #define I_s3s1s2(op) \ |
154 | Ip_s3s1s2(op) \ | |
155 | { \ | |
156 | build_insn(buf, insn##op, b, c, a); \ | |
157 | } \ | |
158 | UASM_EXPORT_SYMBOL(uasm_i##op); | |
159 | ||
e30ec452 TS |
160 | #define I_u2u1u3(op) \ |
161 | Ip_u2u1u3(op) \ | |
162 | { \ | |
163 | build_insn(buf, insn##op, b, a, c); \ | |
22b0763a DD |
164 | } \ |
165 | UASM_EXPORT_SYMBOL(uasm_i##op); | |
e30ec452 | 166 | |
beef8e02 MC |
167 | #define I_u3u2u1(op) \ |
168 | Ip_u3u2u1(op) \ | |
169 | { \ | |
170 | build_insn(buf, insn##op, c, b, a); \ | |
171 | } \ | |
172 | UASM_EXPORT_SYMBOL(uasm_i##op); | |
173 | ||
e30ec452 TS |
174 | #define I_u3u1u2(op) \ |
175 | Ip_u3u1u2(op) \ | |
176 | { \ | |
177 | build_insn(buf, insn##op, b, c, a); \ | |
22b0763a DD |
178 | } \ |
179 | UASM_EXPORT_SYMBOL(uasm_i##op); | |
e30ec452 TS |
180 | |
181 | #define I_u1u2s3(op) \ | |
182 | Ip_u1u2s3(op) \ | |
183 | { \ | |
184 | build_insn(buf, insn##op, a, b, c); \ | |
22b0763a DD |
185 | } \ |
186 | UASM_EXPORT_SYMBOL(uasm_i##op); | |
e30ec452 TS |
187 | |
188 | #define I_u2s3u1(op) \ | |
189 | Ip_u2s3u1(op) \ | |
190 | { \ | |
191 | build_insn(buf, insn##op, c, a, b); \ | |
22b0763a DD |
192 | } \ |
193 | UASM_EXPORT_SYMBOL(uasm_i##op); | |
e30ec452 TS |
194 | |
195 | #define I_u2u1s3(op) \ | |
196 | Ip_u2u1s3(op) \ | |
197 | { \ | |
198 | build_insn(buf, insn##op, b, a, c); \ | |
22b0763a DD |
199 | } \ |
200 | UASM_EXPORT_SYMBOL(uasm_i##op); | |
e30ec452 | 201 | |
92078e06 DD |
202 | #define I_u2u1msbu3(op) \ |
203 | Ip_u2u1msbu3(op) \ | |
204 | { \ | |
205 | build_insn(buf, insn##op, b, a, c+d-1, c); \ | |
22b0763a DD |
206 | } \ |
207 | UASM_EXPORT_SYMBOL(uasm_i##op); | |
92078e06 | 208 | |
c42aef09 DD |
209 | #define I_u2u1msb32u3(op) \ |
210 | Ip_u2u1msbu3(op) \ | |
211 | { \ | |
212 | build_insn(buf, insn##op, b, a, c+d-33, c); \ | |
213 | } \ | |
214 | UASM_EXPORT_SYMBOL(uasm_i##op); | |
215 | ||
70342287 | 216 | #define I_u2u1msbdu3(op) \ |
e6de1a09 SH |
217 | Ip_u2u1msbu3(op) \ |
218 | { \ | |
219 | build_insn(buf, insn##op, b, a, d-1, c); \ | |
220 | } \ | |
221 | UASM_EXPORT_SYMBOL(uasm_i##op); | |
222 | ||
e30ec452 TS |
223 | #define I_u1u2(op) \ |
224 | Ip_u1u2(op) \ | |
225 | { \ | |
226 | build_insn(buf, insn##op, a, b); \ | |
22b0763a DD |
227 | } \ |
228 | UASM_EXPORT_SYMBOL(uasm_i##op); | |
e30ec452 | 229 | |
d674dd14 PB |
230 | #define I_u2u1(op) \ |
231 | Ip_u1u2(op) \ | |
232 | { \ | |
233 | build_insn(buf, insn##op, b, a); \ | |
234 | } \ | |
235 | UASM_EXPORT_SYMBOL(uasm_i##op); | |
236 | ||
e30ec452 TS |
237 | #define I_u1s2(op) \ |
238 | Ip_u1s2(op) \ | |
239 | { \ | |
240 | build_insn(buf, insn##op, a, b); \ | |
22b0763a DD |
241 | } \ |
242 | UASM_EXPORT_SYMBOL(uasm_i##op); | |
e30ec452 TS |
243 | |
244 | #define I_u1(op) \ | |
245 | Ip_u1(op) \ | |
246 | { \ | |
247 | build_insn(buf, insn##op, a); \ | |
22b0763a DD |
248 | } \ |
249 | UASM_EXPORT_SYMBOL(uasm_i##op); | |
e30ec452 TS |
250 | |
251 | #define I_0(op) \ | |
252 | Ip_0(op) \ | |
253 | { \ | |
254 | build_insn(buf, insn##op); \ | |
22b0763a DD |
255 | } \ |
256 | UASM_EXPORT_SYMBOL(uasm_i##op); | |
e30ec452 TS |
257 | |
258 | I_u2u1s3(_addiu) | |
259 | I_u3u1u2(_addu) | |
260 | I_u2u1u3(_andi) | |
261 | I_u3u1u2(_and) | |
262 | I_u1u2s3(_beq) | |
263 | I_u1u2s3(_beql) | |
264 | I_u1s2(_bgez) | |
265 | I_u1s2(_bgezl) | |
266 | I_u1s2(_bltz) | |
267 | I_u1s2(_bltzl) | |
268 | I_u1u2s3(_bne) | |
fb2a27e7 | 269 | I_u2s3u1(_cache) |
e30ec452 TS |
270 | I_u1u2u3(_dmfc0) |
271 | I_u1u2u3(_dmtc0) | |
272 | I_u2u1s3(_daddiu) | |
273 | I_u3u1u2(_daddu) | |
4c12a854 | 274 | I_u1u2(_divu) |
e30ec452 TS |
275 | I_u2u1u3(_dsll) |
276 | I_u2u1u3(_dsll32) | |
277 | I_u2u1u3(_dsra) | |
278 | I_u2u1u3(_dsrl) | |
279 | I_u2u1u3(_dsrl32) | |
92078e06 | 280 | I_u2u1u3(_drotr) |
de6d5b55 | 281 | I_u2u1u3(_drotr32) |
e30ec452 TS |
282 | I_u3u1u2(_dsubu) |
283 | I_0(_eret) | |
e6de1a09 SH |
284 | I_u2u1msbdu3(_ext) |
285 | I_u2u1msbu3(_ins) | |
e30ec452 TS |
286 | I_u1(_j) |
287 | I_u1(_jal) | |
49e9529b | 288 | I_u2u1(_jalr) |
e30ec452 | 289 | I_u1(_jr) |
82488818 | 290 | I_u2s3u1(_lb) |
e30ec452 | 291 | I_u2s3u1(_ld) |
d6b3314b | 292 | I_u2s3u1(_lh) |
e30ec452 TS |
293 | I_u2s3u1(_ll) |
294 | I_u2s3u1(_lld) | |
295 | I_u1s2(_lui) | |
296 | I_u2s3u1(_lw) | |
297 | I_u1u2u3(_mfc0) | |
e2965cd0 | 298 | I_u1u2u3(_mfhc0) |
f3ec7a23 | 299 | I_u1(_mfhi) |
16d21a81 | 300 | I_u1(_mflo) |
e30ec452 | 301 | I_u1u2u3(_mtc0) |
e2965cd0 | 302 | I_u1u2u3(_mthc0) |
a8e897ad | 303 | I_u3u1u2(_mul) |
e30ec452 | 304 | I_u2u1u3(_ori) |
5808184f | 305 | I_u3u1u2(_or) |
e30ec452 TS |
306 | I_0(_rfe) |
307 | I_u2s3u1(_sc) | |
308 | I_u2s3u1(_scd) | |
309 | I_u2s3u1(_sd) | |
310 | I_u2u1u3(_sll) | |
bef581ba | 311 | I_u3u2u1(_sllv) |
7682f9e8 | 312 | I_s3s1s2(_slt) |
390363ed | 313 | I_u2u1s3(_sltiu) |
e8ef868b | 314 | I_u3u1u2(_sltu) |
e30ec452 TS |
315 | I_u2u1u3(_sra) |
316 | I_u2u1u3(_srl) | |
f31318fd | 317 | I_u3u2u1(_srlv) |
32546f38 | 318 | I_u2u1u3(_rotr) |
e30ec452 TS |
319 | I_u3u1u2(_subu) |
320 | I_u2s3u1(_sw) | |
729ff561 | 321 | I_u1(_sync) |
e30ec452 | 322 | I_0(_tlbp) |
32546f38 | 323 | I_0(_tlbr) |
e30ec452 TS |
324 | I_0(_tlbwi) |
325 | I_0(_tlbwr) | |
53ed1389 | 326 | I_u1(_wait); |
ab9e4fa0 | 327 | I_u2u1(_wsbh) |
e30ec452 TS |
328 | I_u3u1u2(_xor) |
329 | I_u2u1u3(_xori) | |
d674dd14 | 330 | I_u2u1(_yield) |
92078e06 | 331 | I_u2u1msbu3(_dins); |
c42aef09 | 332 | I_u2u1msb32u3(_dinsm); |
58b9e223 | 333 | I_u1(_syscall); |
5b97c3f7 DD |
334 | I_u1u2s3(_bbit0); |
335 | I_u1u2s3(_bbit1); | |
bb3d68c3 DD |
336 | I_u3u1u2(_lwx) |
337 | I_u3u1u2(_ldx) | |
e30ec452 | 338 | |
c9941158 DD |
339 | #ifdef CONFIG_CPU_CAVIUM_OCTEON |
340 | #include <asm/octeon/octeon.h> | |
078a55fc | 341 | void ISAFUNC(uasm_i_pref)(u32 **buf, unsigned int a, signed int b, |
c9941158 DD |
342 | unsigned int c) |
343 | { | |
344 | if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X) && a <= 24 && a != 5) | |
345 | /* | |
346 | * As per erratum Core-14449, replace prefetches 0-4, | |
347 | * 6-24 with 'pref 28'. | |
348 | */ | |
349 | build_insn(buf, insn_pref, c, 28, b); | |
350 | else | |
351 | build_insn(buf, insn_pref, c, a, b); | |
352 | } | |
abc597fe | 353 | UASM_EXPORT_SYMBOL(ISAFUNC(uasm_i_pref)); |
c9941158 DD |
354 | #else |
355 | I_u2s3u1(_pref) | |
356 | #endif | |
357 | ||
e30ec452 | 358 | /* Handle labels. */ |
078a55fc | 359 | void ISAFUNC(uasm_build_label)(struct uasm_label **lab, u32 *addr, int lid) |
e30ec452 TS |
360 | { |
361 | (*lab)->addr = addr; | |
362 | (*lab)->lab = lid; | |
363 | (*lab)++; | |
364 | } | |
abc597fe | 365 | UASM_EXPORT_SYMBOL(ISAFUNC(uasm_build_label)); |
e30ec452 | 366 | |
078a55fc | 367 | int ISAFUNC(uasm_in_compat_space_p)(long addr) |
e30ec452 TS |
368 | { |
369 | /* Is this address in 32bit compat space? */ | |
370 | #ifdef CONFIG_64BIT | |
371 | return (((addr) & 0xffffffff00000000L) == 0xffffffff00000000L); | |
372 | #else | |
373 | return 1; | |
374 | #endif | |
375 | } | |
abc597fe | 376 | UASM_EXPORT_SYMBOL(ISAFUNC(uasm_in_compat_space_p)); |
e30ec452 | 377 | |
078a55fc | 378 | static int uasm_rel_highest(long val) |
e30ec452 TS |
379 | { |
380 | #ifdef CONFIG_64BIT | |
381 | return ((((val + 0x800080008000L) >> 48) & 0xffff) ^ 0x8000) - 0x8000; | |
382 | #else | |
383 | return 0; | |
384 | #endif | |
385 | } | |
386 | ||
078a55fc | 387 | static int uasm_rel_higher(long val) |
e30ec452 TS |
388 | { |
389 | #ifdef CONFIG_64BIT | |
390 | return ((((val + 0x80008000L) >> 32) & 0xffff) ^ 0x8000) - 0x8000; | |
391 | #else | |
392 | return 0; | |
393 | #endif | |
394 | } | |
395 | ||
078a55fc | 396 | int ISAFUNC(uasm_rel_hi)(long val) |
e30ec452 TS |
397 | { |
398 | return ((((val + 0x8000L) >> 16) & 0xffff) ^ 0x8000) - 0x8000; | |
399 | } | |
abc597fe | 400 | UASM_EXPORT_SYMBOL(ISAFUNC(uasm_rel_hi)); |
e30ec452 | 401 | |
078a55fc | 402 | int ISAFUNC(uasm_rel_lo)(long val) |
e30ec452 TS |
403 | { |
404 | return ((val & 0xffff) ^ 0x8000) - 0x8000; | |
405 | } | |
abc597fe | 406 | UASM_EXPORT_SYMBOL(ISAFUNC(uasm_rel_lo)); |
e30ec452 | 407 | |
078a55fc | 408 | void ISAFUNC(UASM_i_LA_mostly)(u32 **buf, unsigned int rs, long addr) |
e30ec452 | 409 | { |
abc597fe SH |
410 | if (!ISAFUNC(uasm_in_compat_space_p)(addr)) { |
411 | ISAFUNC(uasm_i_lui)(buf, rs, uasm_rel_highest(addr)); | |
e30ec452 | 412 | if (uasm_rel_higher(addr)) |
abc597fe SH |
413 | ISAFUNC(uasm_i_daddiu)(buf, rs, rs, uasm_rel_higher(addr)); |
414 | if (ISAFUNC(uasm_rel_hi(addr))) { | |
415 | ISAFUNC(uasm_i_dsll)(buf, rs, rs, 16); | |
416 | ISAFUNC(uasm_i_daddiu)(buf, rs, rs, | |
417 | ISAFUNC(uasm_rel_hi)(addr)); | |
418 | ISAFUNC(uasm_i_dsll)(buf, rs, rs, 16); | |
e30ec452 | 419 | } else |
abc597fe | 420 | ISAFUNC(uasm_i_dsll32)(buf, rs, rs, 0); |
e30ec452 | 421 | } else |
abc597fe | 422 | ISAFUNC(uasm_i_lui)(buf, rs, ISAFUNC(uasm_rel_hi(addr))); |
e30ec452 | 423 | } |
abc597fe | 424 | UASM_EXPORT_SYMBOL(ISAFUNC(UASM_i_LA_mostly)); |
e30ec452 | 425 | |
078a55fc | 426 | void ISAFUNC(UASM_i_LA)(u32 **buf, unsigned int rs, long addr) |
e30ec452 | 427 | { |
abc597fe SH |
428 | ISAFUNC(UASM_i_LA_mostly)(buf, rs, addr); |
429 | if (ISAFUNC(uasm_rel_lo(addr))) { | |
430 | if (!ISAFUNC(uasm_in_compat_space_p)(addr)) | |
431 | ISAFUNC(uasm_i_daddiu)(buf, rs, rs, | |
432 | ISAFUNC(uasm_rel_lo(addr))); | |
e30ec452 | 433 | else |
abc597fe SH |
434 | ISAFUNC(uasm_i_addiu)(buf, rs, rs, |
435 | ISAFUNC(uasm_rel_lo(addr))); | |
e30ec452 TS |
436 | } |
437 | } | |
abc597fe | 438 | UASM_EXPORT_SYMBOL(ISAFUNC(UASM_i_LA)); |
e30ec452 TS |
439 | |
440 | /* Handle relocations. */ | |
078a55fc | 441 | void ISAFUNC(uasm_r_mips_pc16)(struct uasm_reloc **rel, u32 *addr, int lid) |
e30ec452 TS |
442 | { |
443 | (*rel)->addr = addr; | |
444 | (*rel)->type = R_MIPS_PC16; | |
445 | (*rel)->lab = lid; | |
446 | (*rel)++; | |
447 | } | |
abc597fe | 448 | UASM_EXPORT_SYMBOL(ISAFUNC(uasm_r_mips_pc16)); |
e30ec452 | 449 | |
078a55fc PG |
450 | static inline void __resolve_relocs(struct uasm_reloc *rel, |
451 | struct uasm_label *lab); | |
e30ec452 | 452 | |
078a55fc PG |
453 | void ISAFUNC(uasm_resolve_relocs)(struct uasm_reloc *rel, |
454 | struct uasm_label *lab) | |
e30ec452 TS |
455 | { |
456 | struct uasm_label *l; | |
457 | ||
458 | for (; rel->lab != UASM_LABEL_INVALID; rel++) | |
459 | for (l = lab; l->lab != UASM_LABEL_INVALID; l++) | |
460 | if (rel->lab == l->lab) | |
461 | __resolve_relocs(rel, l); | |
462 | } | |
abc597fe | 463 | UASM_EXPORT_SYMBOL(ISAFUNC(uasm_resolve_relocs)); |
e30ec452 | 464 | |
078a55fc PG |
465 | void ISAFUNC(uasm_move_relocs)(struct uasm_reloc *rel, u32 *first, u32 *end, |
466 | long off) | |
e30ec452 TS |
467 | { |
468 | for (; rel->lab != UASM_LABEL_INVALID; rel++) | |
469 | if (rel->addr >= first && rel->addr < end) | |
470 | rel->addr += off; | |
471 | } | |
abc597fe | 472 | UASM_EXPORT_SYMBOL(ISAFUNC(uasm_move_relocs)); |
e30ec452 | 473 | |
078a55fc PG |
474 | void ISAFUNC(uasm_move_labels)(struct uasm_label *lab, u32 *first, u32 *end, |
475 | long off) | |
e30ec452 TS |
476 | { |
477 | for (; lab->lab != UASM_LABEL_INVALID; lab++) | |
478 | if (lab->addr >= first && lab->addr < end) | |
479 | lab->addr += off; | |
480 | } | |
abc597fe | 481 | UASM_EXPORT_SYMBOL(ISAFUNC(uasm_move_labels)); |
e30ec452 | 482 | |
078a55fc PG |
483 | void ISAFUNC(uasm_copy_handler)(struct uasm_reloc *rel, struct uasm_label *lab, |
484 | u32 *first, u32 *end, u32 *target) | |
e30ec452 TS |
485 | { |
486 | long off = (long)(target - first); | |
487 | ||
488 | memcpy(target, first, (end - first) * sizeof(u32)); | |
489 | ||
abc597fe SH |
490 | ISAFUNC(uasm_move_relocs(rel, first, end, off)); |
491 | ISAFUNC(uasm_move_labels(lab, first, end, off)); | |
e30ec452 | 492 | } |
abc597fe | 493 | UASM_EXPORT_SYMBOL(ISAFUNC(uasm_copy_handler)); |
e30ec452 | 494 | |
078a55fc | 495 | int ISAFUNC(uasm_insn_has_bdelay)(struct uasm_reloc *rel, u32 *addr) |
e30ec452 TS |
496 | { |
497 | for (; rel->lab != UASM_LABEL_INVALID; rel++) { | |
498 | if (rel->addr == addr | |
499 | && (rel->type == R_MIPS_PC16 | |
500 | || rel->type == R_MIPS_26)) | |
501 | return 1; | |
502 | } | |
503 | ||
504 | return 0; | |
505 | } | |
abc597fe | 506 | UASM_EXPORT_SYMBOL(ISAFUNC(uasm_insn_has_bdelay)); |
e30ec452 TS |
507 | |
508 | /* Convenience functions for labeled branches. */ | |
078a55fc PG |
509 | void ISAFUNC(uasm_il_bltz)(u32 **p, struct uasm_reloc **r, unsigned int reg, |
510 | int lid) | |
e30ec452 TS |
511 | { |
512 | uasm_r_mips_pc16(r, *p, lid); | |
abc597fe | 513 | ISAFUNC(uasm_i_bltz)(p, reg, 0); |
e30ec452 | 514 | } |
abc597fe | 515 | UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bltz)); |
e30ec452 | 516 | |
078a55fc | 517 | void ISAFUNC(uasm_il_b)(u32 **p, struct uasm_reloc **r, int lid) |
e30ec452 TS |
518 | { |
519 | uasm_r_mips_pc16(r, *p, lid); | |
abc597fe | 520 | ISAFUNC(uasm_i_b)(p, 0); |
e30ec452 | 521 | } |
abc597fe | 522 | UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_b)); |
e30ec452 | 523 | |
8dee5901 PB |
524 | void ISAFUNC(uasm_il_beq)(u32 **p, struct uasm_reloc **r, unsigned int r1, |
525 | unsigned int r2, int lid) | |
526 | { | |
527 | uasm_r_mips_pc16(r, *p, lid); | |
528 | ISAFUNC(uasm_i_beq)(p, r1, r2, 0); | |
529 | } | |
530 | UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_beq)); | |
531 | ||
078a55fc PG |
532 | void ISAFUNC(uasm_il_beqz)(u32 **p, struct uasm_reloc **r, unsigned int reg, |
533 | int lid) | |
e30ec452 TS |
534 | { |
535 | uasm_r_mips_pc16(r, *p, lid); | |
abc597fe | 536 | ISAFUNC(uasm_i_beqz)(p, reg, 0); |
e30ec452 | 537 | } |
abc597fe | 538 | UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_beqz)); |
e30ec452 | 539 | |
078a55fc PG |
540 | void ISAFUNC(uasm_il_beqzl)(u32 **p, struct uasm_reloc **r, unsigned int reg, |
541 | int lid) | |
e30ec452 TS |
542 | { |
543 | uasm_r_mips_pc16(r, *p, lid); | |
abc597fe | 544 | ISAFUNC(uasm_i_beqzl)(p, reg, 0); |
e30ec452 | 545 | } |
abc597fe | 546 | UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_beqzl)); |
e30ec452 | 547 | |
078a55fc PG |
548 | void ISAFUNC(uasm_il_bne)(u32 **p, struct uasm_reloc **r, unsigned int reg1, |
549 | unsigned int reg2, int lid) | |
fb2a27e7 TS |
550 | { |
551 | uasm_r_mips_pc16(r, *p, lid); | |
abc597fe | 552 | ISAFUNC(uasm_i_bne)(p, reg1, reg2, 0); |
fb2a27e7 | 553 | } |
abc597fe | 554 | UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bne)); |
fb2a27e7 | 555 | |
078a55fc PG |
556 | void ISAFUNC(uasm_il_bnez)(u32 **p, struct uasm_reloc **r, unsigned int reg, |
557 | int lid) | |
e30ec452 TS |
558 | { |
559 | uasm_r_mips_pc16(r, *p, lid); | |
abc597fe | 560 | ISAFUNC(uasm_i_bnez)(p, reg, 0); |
e30ec452 | 561 | } |
abc597fe | 562 | UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bnez)); |
e30ec452 | 563 | |
078a55fc PG |
564 | void ISAFUNC(uasm_il_bgezl)(u32 **p, struct uasm_reloc **r, unsigned int reg, |
565 | int lid) | |
e30ec452 TS |
566 | { |
567 | uasm_r_mips_pc16(r, *p, lid); | |
abc597fe | 568 | ISAFUNC(uasm_i_bgezl)(p, reg, 0); |
e30ec452 | 569 | } |
abc597fe | 570 | UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bgezl)); |
e30ec452 | 571 | |
078a55fc PG |
572 | void ISAFUNC(uasm_il_bgez)(u32 **p, struct uasm_reloc **r, unsigned int reg, |
573 | int lid) | |
e30ec452 TS |
574 | { |
575 | uasm_r_mips_pc16(r, *p, lid); | |
abc597fe | 576 | ISAFUNC(uasm_i_bgez)(p, reg, 0); |
e30ec452 | 577 | } |
abc597fe | 578 | UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bgez)); |
5b97c3f7 | 579 | |
078a55fc PG |
580 | void ISAFUNC(uasm_il_bbit0)(u32 **p, struct uasm_reloc **r, unsigned int reg, |
581 | unsigned int bit, int lid) | |
5b97c3f7 DD |
582 | { |
583 | uasm_r_mips_pc16(r, *p, lid); | |
abc597fe | 584 | ISAFUNC(uasm_i_bbit0)(p, reg, bit, 0); |
5b97c3f7 | 585 | } |
abc597fe | 586 | UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bbit0)); |
5b97c3f7 | 587 | |
078a55fc PG |
588 | void ISAFUNC(uasm_il_bbit1)(u32 **p, struct uasm_reloc **r, unsigned int reg, |
589 | unsigned int bit, int lid) | |
5b97c3f7 DD |
590 | { |
591 | uasm_r_mips_pc16(r, *p, lid); | |
abc597fe | 592 | ISAFUNC(uasm_i_bbit1)(p, reg, bit, 0); |
5b97c3f7 | 593 | } |
abc597fe | 594 | UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bbit1)); |