[deliverable/linux.git] / arch / mips / mti-malta / malta-setup.c

/*
 * Carsten Langgaard, carstenl@mips.com
 * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
 * Copyright (C) 2008 Dmitri Vorobiev
 *
 *  This program is free software; you can distribute it and/or modify it
 *  under the terms of the GNU General Public License (Version 2) as
 *  published by the Free Software Foundation.
 *
 *  This program is distributed in the hope it will be useful, but WITHOUT
 *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 *  for more details.
 *
 *  You should have received a copy of the GNU General Public License along
 *  with this program; if not, write to the Free Software Foundation, Inc.,
 *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
 */
#include <linux/cpu.h>
#include <linux/init.h>
#include <linux/sched.h>
#include <linux/ioport.h>
#include <linux/irq.h>
#include <linux/pci.h>
#include <linux/screen_info.h>
#include <linux/time.h>

#include <asm/fw/fw.h>
#include <asm/mips-boards/generic.h>
#include <asm/mips-boards/malta.h>
#include <asm/mips-boards/maltaint.h>
#include <asm/dma.h>
#include <asm/traps.h>
#include <asm/gcmpregs.h>
#ifdef CONFIG_VT
#include <linux/console.h>
#endif

extern void malta_be_init(void);
extern int malta_be_handler(struct pt_regs *regs, int is_fixup);

static struct resource standard_io_resources[] = {
	{
		.name = "dma1",
		.start = 0x00,
		.end = 0x1f,
		.flags = IORESOURCE_BUSY
	},
	{
		.name = "timer",
		.start = 0x40,
		.end = 0x5f,
		.flags = IORESOURCE_BUSY
	},
	{
		.name = "keyboard",
		.start = 0x60,
		.end = 0x6f,
		.flags = IORESOURCE_BUSY
	},
	{
		.name = "dma page reg",
		.start = 0x80,
		.end = 0x8f,
		.flags = IORESOURCE_BUSY
	},
	{
		.name = "dma2",
		.start = 0xc0,
		.end = 0xdf,
		.flags = IORESOURCE_BUSY
	},
};

const char *get_system_type(void)
{
	return "MIPS Malta";
}

#if defined(CONFIG_MIPS_MT_SMTC)
const char display_string[] = "	      SMTC LINUX ON MALTA	";
#else
const char display_string[] = "	       LINUX ON MALTA	    ";
#endif /* CONFIG_MIPS_MT_SMTC */

#ifdef CONFIG_BLK_DEV_FD
static void __init fd_activate(void)
{
	/*
	 * Activate Floppy Controller in the SMSC FDC37M817 Super I/O
	 * Controller.
	 * Done by YAMON 2.00 onwards
	 */
	/* Entering config state. */
	SMSC_WRITE(SMSC_CONFIG_ENTER, SMSC_CONFIG_REG);

	/* Activate floppy controller. */
	SMSC_WRITE(SMSC_CONFIG_DEVNUM, SMSC_CONFIG_REG);
	SMSC_WRITE(SMSC_CONFIG_DEVNUM_FLOPPY, SMSC_DATA_REG);
	SMSC_WRITE(SMSC_CONFIG_ACTIVATE, SMSC_CONFIG_REG);
	SMSC_WRITE(SMSC_CONFIG_ACTIVATE_ENABLE, SMSC_DATA_REG);

	/* Exit config state. */
	SMSC_WRITE(SMSC_CONFIG_EXIT, SMSC_CONFIG_REG);
}
#endif

static int __init plat_enable_iocoherency(void)
{
	int supported = 0;
	if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO) {
		if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) {
			BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_CPUCOH_EN;
			pr_info("Enabled Bonito CPU coherency\n");
			supported = 1;
		}
		if (strstr(fw_getcmdline(), "iobcuncached")) {
			BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN;
			BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG &
				~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
				  BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
			pr_info("Disabled Bonito IOBC coherency\n");
		} else {
			BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_IOBCCOH_EN;
			BONITO_PCIMEMBASECFG |=
				(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
				 BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
			pr_info("Enabled Bonito IOBC coherency\n");
		}
	} else if (gcmp_niocu() != 0) {
		/* Nothing special needs to be done to enable coherency */
		pr_info("CMP IOCU detected\n");
		if ((*(unsigned int *)0xbf403000 & 0x81) != 0x81) {
			pr_crit("IOCU OPERATION DISABLED BY SWITCH - DEFAULTING TO SW IO COHERENCY\n");
			return 0;
		}
		supported = 1;
	}
	hw_coherentio = supported;
	return supported;
}

static void __init plat_setup_iocoherency(void)
{
#ifdef CONFIG_DMA_NONCOHERENT
	/*
	 * Kernel has been configured with software coherency
	 * but we might choose to turn it off and use hardware
	 * coherency instead.
	 */
	if (plat_enable_iocoherency()) {
		if (coherentio == 0)
			pr_info("Hardware DMA cache coherency disabled\n");
		else
			pr_info("Hardware DMA cache coherency enabled\n");
	} else {
		if (coherentio == 1)
			pr_info("Hardware DMA cache coherency unsupported, but enabled from command line!\n");
		else
			pr_info("Software DMA cache coherency enabled\n");
	}
#else
	if (!plat_enable_iocoherency())
		panic("Hardware DMA cache coherency not supported!");
#endif
}

#ifdef CONFIG_BLK_DEV_IDE
static void __init pci_clock_check(void)
{
	unsigned int __iomem *jmpr_p =
		(unsigned int *) ioremap(MALTA_JMPRS_REG, sizeof(unsigned int));
	int jmpr = (__raw_readl(jmpr_p) >> 2) & 0x07;
	static const int pciclocks[] __initconst = {
		33, 20, 25, 30, 12, 16, 37, 10
	};
	int pciclock = pciclocks[jmpr];
	char *argptr = fw_getcmdline();

	if (pciclock != 33 && !strstr(argptr, "idebus=")) {
		pr_warn("WARNING: PCI clock is %dMHz, setting idebus\n",
			pciclock);
		argptr += strlen(argptr);
		sprintf(argptr, " idebus=%d", pciclock);
		if (pciclock < 20 || pciclock > 66)
			pr_warn("WARNING: IDE timing calculations will be incorrect\n");
	}
}
#endif

#if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE)
static void __init screen_info_setup(void)
{
	screen_info = (struct screen_info) {
		.orig_x = 0,
		.orig_y = 25,
		.ext_mem_k = 0,
		.orig_video_page = 0,
		.orig_video_mode = 0,
		.orig_video_cols = 80,
		.unused2 = 0,
		.orig_video_ega_bx = 0,
		.unused3 = 0,
		.orig_video_lines = 25,
		.orig_video_isVGA = VIDEO_TYPE_VGAC,
		.orig_video_points = 16
	};
}
#endif

static void __init bonito_quirks_setup(void)
{
	char *argptr;

	argptr = fw_getcmdline();
	if (strstr(argptr, "debug")) {
		BONITO_BONGENCFG |= BONITO_BONGENCFG_DEBUGMODE;
		pr_info("Enabled Bonito debug mode\n");
	} else
		BONITO_BONGENCFG &= ~BONITO_BONGENCFG_DEBUGMODE;

#ifdef CONFIG_DMA_COHERENT
	if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) {
		BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_CPUCOH_EN;
		pr_info("Enabled Bonito CPU coherency\n");

		argptr = fw_getcmdline();
		if (strstr(argptr, "iobcuncached")) {
			BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN;
			BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG &
				~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
					BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
			pr_info("Disabled Bonito IOBC coherency\n");
		} else {
			BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_IOBCCOH_EN;
			BONITO_PCIMEMBASECFG |=
				(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
					BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
			pr_info("Enabled Bonito IOBC coherency\n");
		}
	} else
		panic("Hardware DMA cache coherency not supported");
#endif
}

void __init plat_mem_setup(void)
{
	unsigned int i;

	mips_pcibios_init();

	/* Request I/O space for devices used on the Malta board. */
	for (i = 0; i < ARRAY_SIZE(standard_io_resources); i++)
		request_resource(&ioport_resource, standard_io_resources+i);

	/*
	 * Enable DMA channel 4 (cascade channel) in the PIIX4 south bridge.
	 */
	enable_dma(4);

#ifdef CONFIG_DMA_COHERENT
	if (mips_revision_sconid != MIPS_REVISION_SCON_BONITO)
		panic("Hardware DMA cache coherency not supported");
#endif

	if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO)
		bonito_quirks_setup();

	plat_setup_iocoherency();

#ifdef CONFIG_BLK_DEV_IDE
	pci_clock_check();
#endif

#ifdef CONFIG_BLK_DEV_FD
	fd_activate();
#endif

#if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE)
	screen_info_setup();
#endif

	board_be_init = malta_be_init;
	board_be_handler = malta_be_handler;
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Carsten Langgaard, carstenl@mips.com
	3	* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
52d65cf8	4	* Copyright (C) 2008 Dmitri Vorobiev
1da177e4 LT	5	*
	6	* This program is free software; you can distribute it and/or modify it
	7	* under the terms of the GNU General Public License (Version 2) as
	8	* published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope it will be useful, but WITHOUT
	11	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
	13	* for more details.
	14	*
	15	* You should have received a copy of the GNU General Public License along
	16	* with this program; if not, write to the Free Software Foundation, Inc.,
	17	* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
	18	*/
54bf038e	19	#include <linux/cpu.h>
1da177e4 LT	20	#include <linux/init.h>
	21	#include <linux/sched.h>
	22	#include <linux/ioport.h>
54bf038e	23	#include <linux/irq.h>
1da177e4	24	#include <linux/pci.h>
894673ee	25	#include <linux/screen_info.h>
54bf038e	26	#include <linux/time.h>
1da177e4	27
b431f09d	28	#include <asm/fw/fw.h>
1da177e4	29	#include <asm/mips-boards/generic.h>
1da177e4 LT	30	#include <asm/mips-boards/malta.h>
	31	#include <asm/mips-boards/maltaint.h>
	32	#include <asm/dma.h>
1da177e4	33	#include <asm/traps.h>
b6d92b4a	34	#include <asm/gcmpregs.h>
1da177e4 LT	35	#ifdef CONFIG_VT
	36	#include <linux/console.h>
	37	#endif
	38
39b8d525 RB	39	extern void malta_be_init(void);
	40	extern int malta_be_handler(struct pt_regs *regs, int is_fixup);
	41
52d65cf8	42	static struct resource standard_io_resources[] = {
4ca76513 DV	43	{
	44	.name = "dma1",
	45	.start = 0x00,
	46	.end = 0x1f,
	47	.flags = IORESOURCE_BUSY
	48	},
	49	{
	50	.name = "timer",
	51	.start = 0x40,
	52	.end = 0x5f,
	53	.flags = IORESOURCE_BUSY
	54	},
	55	{
	56	.name = "keyboard",
	57	.start = 0x60,
	58	.end = 0x6f,
	59	.flags = IORESOURCE_BUSY
	60	},
	61	{
	62	.name = "dma page reg",
	63	.start = 0x80,
	64	.end = 0x8f,
	65	.flags = IORESOURCE_BUSY
	66	},
	67	{
	68	.name = "dma2",
	69	.start = 0xc0,
	70	.end = 0xdf,
	71	.flags = IORESOURCE_BUSY
	72	},
1da177e4 LT	73	};
1da177e4 LT	74
1da177e4 LT	75	const char *get_system_type(void)
	76	{
	77	return "MIPS Malta";
	78	}
	79
79894c7b	80	#if defined(CONFIG_MIPS_MT_SMTC)
70342287	81	const char display_string[] = " SMTC LINUX ON MALTA ";
79894c7b	82	#else
70342287	83	const char display_string[] = " LINUX ON MALTA ";
79894c7b RB	84	#endif /* CONFIG_MIPS_MT_SMTC */
79894c7b RB	85
1da177e4	86	#ifdef CONFIG_BLK_DEV_FD
ef7645cf	87	static void __init fd_activate(void)
1da177e4 LT	88	{
	89	/*
	90	* Activate Floppy Controller in the SMSC FDC37M817 Super I/O
	91	* Controller.
	92	* Done by YAMON 2.00 onwards
	93	*/
	94	/* Entering config state. */
	95	SMSC_WRITE(SMSC_CONFIG_ENTER, SMSC_CONFIG_REG);
	96
	97	/* Activate floppy controller. */
	98	SMSC_WRITE(SMSC_CONFIG_DEVNUM, SMSC_CONFIG_REG);
	99	SMSC_WRITE(SMSC_CONFIG_DEVNUM_FLOPPY, SMSC_DATA_REG);
	100	SMSC_WRITE(SMSC_CONFIG_ACTIVATE, SMSC_CONFIG_REG);
	101	SMSC_WRITE(SMSC_CONFIG_ACTIVATE_ENABLE, SMSC_DATA_REG);
	102
	103	/* Exit config state. */
	104	SMSC_WRITE(SMSC_CONFIG_EXIT, SMSC_CONFIG_REG);
	105	}
	106	#endif
	107
b6d92b4a SH	108	static int __init plat_enable_iocoherency(void)
	109	{
	110	int supported = 0;
	111	if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO) {
	112	if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) {
	113	BONITO_PCICACHECTRL \|= BONITO_PCICACHECTRL_CPUCOH_EN;
	114	pr_info("Enabled Bonito CPU coherency\n");
	115	supported = 1;
	116	}
	117	if (strstr(fw_getcmdline(), "iobcuncached")) {
	118	BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN;
	119	BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG &
	120	~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED \|
	121	BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
	122	pr_info("Disabled Bonito IOBC coherency\n");
	123	} else {
	124	BONITO_PCICACHECTRL \|= BONITO_PCICACHECTRL_IOBCCOH_EN;
	125	BONITO_PCIMEMBASECFG \|=
	126	(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED \|
	127	BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
	128	pr_info("Enabled Bonito IOBC coherency\n");
	129	}
	130	} else if (gcmp_niocu() != 0) {
	131	/* Nothing special needs to be done to enable coherency */
	132	pr_info("CMP IOCU detected\n");
	133	if (((unsigned int )0xbf403000 & 0x81) != 0x81) {
	134	pr_crit("IOCU OPERATION DISABLED BY SWITCH - DEFAULTING TO SW IO COHERENCY\n");
	135	return 0;
	136	}
	137	supported = 1;
	138	}
	139	hw_coherentio = supported;
	140	return supported;
	141	}
	142
	143	static void __init plat_setup_iocoherency(void)
	144	{
	145	#ifdef CONFIG_DMA_NONCOHERENT
	146	/*
	147	* Kernel has been configured with software coherency
	148	* but we might choose to turn it off and use hardware
	149	* coherency instead.
	150	*/
	151	if (plat_enable_iocoherency()) {
	152	if (coherentio == 0)
	153	pr_info("Hardware DMA cache coherency disabled\n");
	154	else
	155	pr_info("Hardware DMA cache coherency enabled\n");
	156	} else {
	157	if (coherentio == 1)
	158	pr_info("Hardware DMA cache coherency unsupported, but enabled from command line!\n");
	159	else
	160	pr_info("Software DMA cache coherency enabled\n");
	161	}
	162	#else
	163	if (!plat_enable_iocoherency())
	164	panic("Hardware DMA cache coherency not supported!");
	165	#endif
	166	}
	167
f3a4ce95 DV	168	#ifdef CONFIG_BLK_DEV_IDE
	169	static void __init pci_clock_check(void)
	170	{
	171	unsigned int __iomem *jmpr_p =
	172	(unsigned int *) ioremap(MALTA_JMPRS_REG, sizeof(unsigned int));
	173	int jmpr = (__raw_readl(jmpr_p) >> 2) & 0x07;
4a043d79	174	static const int pciclocks[] __initconst = {
f3a4ce95 DV	175	33, 20, 25, 30, 12, 16, 37, 10
	176	};
	177	int pciclock = pciclocks[jmpr];
b431f09d	178	char *argptr = fw_getcmdline();
f3a4ce95 DV	179
f3a4ce95 DV	180	if (pciclock != 33 && !strstr(argptr, "idebus=")) {
49bffbdc SH	181	pr_warn("WARNING: PCI clock is %dMHz, setting idebus\n",
49bffbdc SH	182	pciclock);
f3a4ce95 DV	183	argptr += strlen(argptr);
	184	sprintf(argptr, " idebus=%d", pciclock);
	185	if (pciclock < 20 \|\| pciclock > 66)
49bffbdc	186	pr_warn("WARNING: IDE timing calculations will be incorrect\n");
f3a4ce95 DV	187	}
	188	}
	189	#endif
	190
a382963e DV	191	#if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE)
	192	static void __init screen_info_setup(void)
	193	{
	194	screen_info = (struct screen_info) {
	195	.orig_x = 0,
	196	.orig_y = 25,
	197	.ext_mem_k = 0,
	198	.orig_video_page = 0,
	199	.orig_video_mode = 0,
	200	.orig_video_cols = 80,
	201	.unused2 = 0,
	202	.orig_video_ega_bx = 0,
	203	.unused3 = 0,
	204	.orig_video_lines = 25,
	205	.orig_video_isVGA = VIDEO_TYPE_VGAC,
	206	.orig_video_points = 16
	207	};
	208	}
	209	#endif
	210
750dc31c DV	211	static void __init bonito_quirks_setup(void)
	212	{
	213	char *argptr;
	214
b431f09d	215	argptr = fw_getcmdline();
750dc31c DV	216	if (strstr(argptr, "debug")) {
750dc31c DV	217	BONITO_BONGENCFG \|= BONITO_BONGENCFG_DEBUGMODE;
49bffbdc	218	pr_info("Enabled Bonito debug mode\n");
750dc31c DV	219	} else
	220	BONITO_BONGENCFG &= ~BONITO_BONGENCFG_DEBUGMODE;
	221
	222	#ifdef CONFIG_DMA_COHERENT
	223	if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) {
	224	BONITO_PCICACHECTRL \|= BONITO_PCICACHECTRL_CPUCOH_EN;
49bffbdc	225	pr_info("Enabled Bonito CPU coherency\n");
750dc31c	226
b431f09d	227	argptr = fw_getcmdline();
750dc31c DV	228	if (strstr(argptr, "iobcuncached")) {
	229	BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN;
	230	BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG &
	231	~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED \|
	232	BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
49bffbdc	233	pr_info("Disabled Bonito IOBC coherency\n");
750dc31c DV	234	} else {
	235	BONITO_PCICACHECTRL \|= BONITO_PCICACHECTRL_IOBCCOH_EN;
	236	BONITO_PCIMEMBASECFG \|=
	237	(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED \|
	238	BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
49bffbdc	239	pr_info("Enabled Bonito IOBC coherency\n");
750dc31c DV	240	}
	241	} else
	242	panic("Hardware DMA cache coherency not supported");
	243	#endif
	244	}
	245
2925aba4	246	void __init plat_mem_setup(void)
1da177e4 LT	247	{
	248	unsigned int i;
	249
c83cfc9c RB	250	mips_pcibios_init();
c83cfc9c RB	251
1da177e4 LT	252	/* Request I/O space for devices used on the Malta board. */
	253	for (i = 0; i < ARRAY_SIZE(standard_io_resources); i++)
	254	request_resource(&ioport_resource, standard_io_resources+i);
	255
	256	/*
	257	* Enable DMA channel 4 (cascade channel) in the PIIX4 south bridge.
	258	*/
	259	enable_dma(4);
	260
1da177e4	261	#ifdef CONFIG_DMA_COHERENT
750dc31c	262	if (mips_revision_sconid != MIPS_REVISION_SCON_BONITO)
1da177e4	263	panic("Hardware DMA cache coherency not supported");
1da177e4 LT	264	#endif
1da177e4 LT	265
750dc31c DV	266	if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO)
	267	bonito_quirks_setup();
	268
b6d92b4a SH	269	plat_setup_iocoherency();
b6d92b4a SH	270
1da177e4	271	#ifdef CONFIG_BLK_DEV_IDE
f3a4ce95	272	pci_clock_check();
1da177e4	273	#endif
750dc31c	274
1da177e4	275	#ifdef CONFIG_BLK_DEV_FD
49a89efb	276	fd_activate();
1da177e4	277	#endif
750dc31c	278
a382963e DV	279	#if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE)
a382963e DV	280	screen_info_setup();
1da177e4	281	#endif
39b8d525 RB	282
	283	board_be_init = malta_be_init;
	284	board_be_handler = malta_be_handler;
1da177e4	285	}