[deliverable/linux.git] / arch / mips / mti-malta / malta-setup.c

/*
 * Carsten Langgaard, carstenl@mips.com
 * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
 * Copyright (C) 2008 Dmitri Vorobiev
 *
 *  This program is free software; you can distribute it and/or modify it
 *  under the terms of the GNU General Public License (Version 2) as
 *  published by the Free Software Foundation.
 *
 *  This program is distributed in the hope it will be useful, but WITHOUT
 *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 *  for more details.
 *
 *  You should have received a copy of the GNU General Public License along
 *  with this program; if not, write to the Free Software Foundation, Inc.,
 *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
 */
#include <linux/cpu.h>
#include <linux/init.h>
#include <linux/sched.h>
#include <linux/ioport.h>
#include <linux/irq.h>
#include <linux/pci.h>
#include <linux/screen_info.h>
#include <linux/time.h>

#include <asm/fw/fw.h>
#include <asm/mips-cm.h>
#include <asm/mips-boards/generic.h>
#include <asm/mips-boards/malta.h>
#include <asm/mips-boards/maltaint.h>
#include <asm/dma.h>
#include <asm/traps.h>
#ifdef CONFIG_VT
#include <linux/console.h>
#endif

extern void malta_be_init(void);
extern int malta_be_handler(struct pt_regs *regs, int is_fixup);

static struct resource standard_io_resources[] = {
	{
		.name = "dma1",
		.start = 0x00,
		.end = 0x1f,
		.flags = IORESOURCE_BUSY
	},
	{
		.name = "timer",
		.start = 0x40,
		.end = 0x5f,
		.flags = IORESOURCE_BUSY
	},
	{
		.name = "keyboard",
		.start = 0x60,
		.end = 0x6f,
		.flags = IORESOURCE_BUSY
	},
	{
		.name = "dma page reg",
		.start = 0x80,
		.end = 0x8f,
		.flags = IORESOURCE_BUSY
	},
	{
		.name = "dma2",
		.start = 0xc0,
		.end = 0xdf,
		.flags = IORESOURCE_BUSY
	},
};

const char *get_system_type(void)
{
	return "MIPS Malta";
}

const char display_string[] = "	       LINUX ON MALTA	    ";

#ifdef CONFIG_BLK_DEV_FD
static void __init fd_activate(void)
{
	/*
	 * Activate Floppy Controller in the SMSC FDC37M817 Super I/O
	 * Controller.
	 * Done by YAMON 2.00 onwards
	 */
	/* Entering config state. */
	SMSC_WRITE(SMSC_CONFIG_ENTER, SMSC_CONFIG_REG);

	/* Activate floppy controller. */
	SMSC_WRITE(SMSC_CONFIG_DEVNUM, SMSC_CONFIG_REG);
	SMSC_WRITE(SMSC_CONFIG_DEVNUM_FLOPPY, SMSC_DATA_REG);
	SMSC_WRITE(SMSC_CONFIG_ACTIVATE, SMSC_CONFIG_REG);
	SMSC_WRITE(SMSC_CONFIG_ACTIVATE_ENABLE, SMSC_DATA_REG);

	/* Exit config state. */
	SMSC_WRITE(SMSC_CONFIG_EXIT, SMSC_CONFIG_REG);
}
#endif

static int __init plat_enable_iocoherency(void)
{
	int supported = 0;
	if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO) {
		if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) {
			BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_CPUCOH_EN;
			pr_info("Enabled Bonito CPU coherency\n");
			supported = 1;
		}
		if (strstr(fw_getcmdline(), "iobcuncached")) {
			BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN;
			BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG &
				~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
				  BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
			pr_info("Disabled Bonito IOBC coherency\n");
		} else {
			BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_IOBCCOH_EN;
			BONITO_PCIMEMBASECFG |=
				(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
				 BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
			pr_info("Enabled Bonito IOBC coherency\n");
		}
	} else if (mips_cm_numiocu() != 0) {
		/* Nothing special needs to be done to enable coherency */
		pr_info("CMP IOCU detected\n");
		if ((*(unsigned int *)0xbf403000 & 0x81) != 0x81) {
			pr_crit("IOCU OPERATION DISABLED BY SWITCH - DEFAULTING TO SW IO COHERENCY\n");
			return 0;
		}
		supported = 1;
	}
	hw_coherentio = supported;
	return supported;
}

static void __init plat_setup_iocoherency(void)
{
#ifdef CONFIG_DMA_NONCOHERENT
	/*
	 * Kernel has been configured with software coherency
	 * but we might choose to turn it off and use hardware
	 * coherency instead.
	 */
	if (plat_enable_iocoherency()) {
		if (coherentio == 0)
			pr_info("Hardware DMA cache coherency disabled\n");
		else
			pr_info("Hardware DMA cache coherency enabled\n");
	} else {
		if (coherentio == 1)
			pr_info("Hardware DMA cache coherency unsupported, but enabled from command line!\n");
		else
			pr_info("Software DMA cache coherency enabled\n");
	}
#else
	if (!plat_enable_iocoherency())
		panic("Hardware DMA cache coherency not supported!");
#endif
}

static void __init pci_clock_check(void)
{
	unsigned int __iomem *jmpr_p =
		(unsigned int *) ioremap(MALTA_JMPRS_REG, sizeof(unsigned int));
	int jmpr = (__raw_readl(jmpr_p) >> 2) & 0x07;
	static const int pciclocks[] __initconst = {
		33, 20, 25, 30, 12, 16, 37, 10
	};
	int pciclock = pciclocks[jmpr];
	char *optptr, *argptr = fw_getcmdline();

	/*
	 * If user passed a pci_clock= option, don't tack on another one
	 */
	optptr = strstr(argptr, "pci_clock=");
	if (optptr && (optptr == argptr || optptr[-1] == ' '))
		return;

	if (pciclock != 33) {
		pr_warn("WARNING: PCI clock is %dMHz, setting pci_clock\n",
			pciclock);
		argptr += strlen(argptr);
		sprintf(argptr, " pci_clock=%d", pciclock);
		if (pciclock < 20 || pciclock > 66)
			pr_warn("WARNING: IDE timing calculations will be "
			        "incorrect\n");
	}
}

#if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE)
static void __init screen_info_setup(void)
{
	screen_info = (struct screen_info) {
		.orig_x = 0,
		.orig_y = 25,
		.ext_mem_k = 0,
		.orig_video_page = 0,
		.orig_video_mode = 0,
		.orig_video_cols = 80,
		.unused2 = 0,
		.orig_video_ega_bx = 0,
		.unused3 = 0,
		.orig_video_lines = 25,
		.orig_video_isVGA = VIDEO_TYPE_VGAC,
		.orig_video_points = 16
	};
}
#endif

static void __init bonito_quirks_setup(void)
{
	char *argptr;

	argptr = fw_getcmdline();
	if (strstr(argptr, "debug")) {
		BONITO_BONGENCFG |= BONITO_BONGENCFG_DEBUGMODE;
		pr_info("Enabled Bonito debug mode\n");
	} else
		BONITO_BONGENCFG &= ~BONITO_BONGENCFG_DEBUGMODE;

#ifdef CONFIG_DMA_COHERENT
	if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) {
		BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_CPUCOH_EN;
		pr_info("Enabled Bonito CPU coherency\n");

		argptr = fw_getcmdline();
		if (strstr(argptr, "iobcuncached")) {
			BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN;
			BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG &
				~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
					BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
			pr_info("Disabled Bonito IOBC coherency\n");
		} else {
			BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_IOBCCOH_EN;
			BONITO_PCIMEMBASECFG |=
				(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
					BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
			pr_info("Enabled Bonito IOBC coherency\n");
		}
	} else
		panic("Hardware DMA cache coherency not supported");
#endif
}

void __init plat_mem_setup(void)
{
	unsigned int i;

	if (config_enabled(CONFIG_EVA))
		/* EVA has already been configured in mach-malta/kernel-init.h */
		pr_info("Enhanced Virtual Addressing (EVA) activated\n");

	mips_pcibios_init();

	/* Request I/O space for devices used on the Malta board. */
	for (i = 0; i < ARRAY_SIZE(standard_io_resources); i++)
		request_resource(&ioport_resource, standard_io_resources+i);

	/*
	 * Enable DMA channel 4 (cascade channel) in the PIIX4 south bridge.
	 */
	enable_dma(4);

#ifdef CONFIG_DMA_COHERENT
	if (mips_revision_sconid != MIPS_REVISION_SCON_BONITO)
		panic("Hardware DMA cache coherency not supported");
#endif

	if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO)
		bonito_quirks_setup();

	plat_setup_iocoherency();

	pci_clock_check();

#ifdef CONFIG_BLK_DEV_FD
	fd_activate();
#endif

#if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE)
	screen_info_setup();
#endif

	board_be_init = malta_be_init;
	board_be_handler = malta_be_handler;
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Carsten Langgaard, carstenl@mips.com
	3	* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
52d65cf8	4	* Copyright (C) 2008 Dmitri Vorobiev
1da177e4 LT	5	*
	6	* This program is free software; you can distribute it and/or modify it
	7	* under the terms of the GNU General Public License (Version 2) as
	8	* published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope it will be useful, but WITHOUT
	11	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
	13	* for more details.
	14	*
	15	* You should have received a copy of the GNU General Public License along
	16	* with this program; if not, write to the Free Software Foundation, Inc.,
	17	* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
	18	*/
54bf038e	19	#include <linux/cpu.h>
1da177e4 LT	20	#include <linux/init.h>
	21	#include <linux/sched.h>
	22	#include <linux/ioport.h>
54bf038e	23	#include <linux/irq.h>
1da177e4	24	#include <linux/pci.h>
894673ee	25	#include <linux/screen_info.h>
54bf038e	26	#include <linux/time.h>
1da177e4	27
b431f09d	28	#include <asm/fw/fw.h>
237036de	29	#include <asm/mips-cm.h>
1da177e4	30	#include <asm/mips-boards/generic.h>
1da177e4 LT	31	#include <asm/mips-boards/malta.h>
	32	#include <asm/mips-boards/maltaint.h>
	33	#include <asm/dma.h>
1da177e4 LT	34	#include <asm/traps.h>
	35	#ifdef CONFIG_VT
	36	#include <linux/console.h>
	37	#endif
	38
39b8d525 RB	39	extern void malta_be_init(void);
	40	extern int malta_be_handler(struct pt_regs *regs, int is_fixup);
	41
52d65cf8	42	static struct resource standard_io_resources[] = {
4ca76513 DV	43	{
	44	.name = "dma1",
	45	.start = 0x00,
	46	.end = 0x1f,
	47	.flags = IORESOURCE_BUSY
	48	},
	49	{
	50	.name = "timer",
	51	.start = 0x40,
	52	.end = 0x5f,
	53	.flags = IORESOURCE_BUSY
	54	},
	55	{
	56	.name = "keyboard",
	57	.start = 0x60,
	58	.end = 0x6f,
	59	.flags = IORESOURCE_BUSY
	60	},
	61	{
	62	.name = "dma page reg",
	63	.start = 0x80,
	64	.end = 0x8f,
	65	.flags = IORESOURCE_BUSY
	66	},
	67	{
	68	.name = "dma2",
	69	.start = 0xc0,
	70	.end = 0xdf,
	71	.flags = IORESOURCE_BUSY
	72	},
1da177e4 LT	73	};
1da177e4 LT	74
1da177e4 LT	75	const char *get_system_type(void)
	76	{
	77	return "MIPS Malta";
	78	}
	79
70342287	80	const char display_string[] = " LINUX ON MALTA ";
79894c7b	81
1da177e4	82	#ifdef CONFIG_BLK_DEV_FD
ef7645cf	83	static void __init fd_activate(void)
1da177e4 LT	84	{
	85	/*
	86	* Activate Floppy Controller in the SMSC FDC37M817 Super I/O
	87	* Controller.
	88	* Done by YAMON 2.00 onwards
	89	*/
	90	/* Entering config state. */
	91	SMSC_WRITE(SMSC_CONFIG_ENTER, SMSC_CONFIG_REG);
	92
	93	/* Activate floppy controller. */
	94	SMSC_WRITE(SMSC_CONFIG_DEVNUM, SMSC_CONFIG_REG);
	95	SMSC_WRITE(SMSC_CONFIG_DEVNUM_FLOPPY, SMSC_DATA_REG);
	96	SMSC_WRITE(SMSC_CONFIG_ACTIVATE, SMSC_CONFIG_REG);
	97	SMSC_WRITE(SMSC_CONFIG_ACTIVATE_ENABLE, SMSC_DATA_REG);
	98
	99	/* Exit config state. */
	100	SMSC_WRITE(SMSC_CONFIG_EXIT, SMSC_CONFIG_REG);
	101	}
	102	#endif
	103
b6d92b4a SH	104	static int __init plat_enable_iocoherency(void)
	105	{
	106	int supported = 0;
	107	if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO) {
	108	if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) {
	109	BONITO_PCICACHECTRL \|= BONITO_PCICACHECTRL_CPUCOH_EN;
	110	pr_info("Enabled Bonito CPU coherency\n");
	111	supported = 1;
	112	}
	113	if (strstr(fw_getcmdline(), "iobcuncached")) {
	114	BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN;
	115	BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG &
	116	~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED \|
	117	BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
	118	pr_info("Disabled Bonito IOBC coherency\n");
	119	} else {
	120	BONITO_PCICACHECTRL \|= BONITO_PCICACHECTRL_IOBCCOH_EN;
	121	BONITO_PCIMEMBASECFG \|=
	122	(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED \|
	123	BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
	124	pr_info("Enabled Bonito IOBC coherency\n");
	125	}
237036de	126	} else if (mips_cm_numiocu() != 0) {
b6d92b4a SH	127	/* Nothing special needs to be done to enable coherency */
	128	pr_info("CMP IOCU detected\n");
	129	if (((unsigned int )0xbf403000 & 0x81) != 0x81) {
	130	pr_crit("IOCU OPERATION DISABLED BY SWITCH - DEFAULTING TO SW IO COHERENCY\n");
	131	return 0;
	132	}
	133	supported = 1;
	134	}
	135	hw_coherentio = supported;
	136	return supported;
	137	}
	138
	139	static void __init plat_setup_iocoherency(void)
	140	{
	141	#ifdef CONFIG_DMA_NONCOHERENT
	142	/*
	143	* Kernel has been configured with software coherency
	144	* but we might choose to turn it off and use hardware
	145	* coherency instead.
	146	*/
	147	if (plat_enable_iocoherency()) {
	148	if (coherentio == 0)
	149	pr_info("Hardware DMA cache coherency disabled\n");
	150	else
	151	pr_info("Hardware DMA cache coherency enabled\n");
	152	} else {
	153	if (coherentio == 1)
	154	pr_info("Hardware DMA cache coherency unsupported, but enabled from command line!\n");
	155	else
	156	pr_info("Software DMA cache coherency enabled\n");
	157	}
	158	#else
	159	if (!plat_enable_iocoherency())
	160	panic("Hardware DMA cache coherency not supported!");
	161	#endif
	162	}
	163
f3a4ce95 DV	164	static void __init pci_clock_check(void)
	165	{
	166	unsigned int __iomem *jmpr_p =
	167	(unsigned int *) ioremap(MALTA_JMPRS_REG, sizeof(unsigned int));
	168	int jmpr = (__raw_readl(jmpr_p) >> 2) & 0x07;
4a043d79	169	static const int pciclocks[] __initconst = {
f3a4ce95 DV	170	33, 20, 25, 30, 12, 16, 37, 10
	171	};
	172	int pciclock = pciclocks[jmpr];
a9dde288	173	char optptr, argptr = fw_getcmdline();
f3a4ce95	174
a9dde288 RB	175	/*
	176	* If user passed a pci_clock= option, don't tack on another one
	177	*/
	178	optptr = strstr(argptr, "pci_clock=");
	179	if (optptr && (optptr == argptr \|\| optptr[-1] == ' '))
	180	return;
	181
	182	if (pciclock != 33) {
	183	pr_warn("WARNING: PCI clock is %dMHz, setting pci_clock\n",
49bffbdc	184	pciclock);
f3a4ce95	185	argptr += strlen(argptr);
a9dde288	186	sprintf(argptr, " pci_clock=%d", pciclock);
f3a4ce95	187	if (pciclock < 20 \|\| pciclock > 66)
a9dde288 RB	188	pr_warn("WARNING: IDE timing calculations will be "
a9dde288 RB	189	"incorrect\n");
f3a4ce95 DV	190	}
f3a4ce95 DV	191	}
f3a4ce95	192
a382963e DV	193	#if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE)
	194	static void __init screen_info_setup(void)
	195	{
	196	screen_info = (struct screen_info) {
	197	.orig_x = 0,
	198	.orig_y = 25,
	199	.ext_mem_k = 0,
	200	.orig_video_page = 0,
	201	.orig_video_mode = 0,
	202	.orig_video_cols = 80,
	203	.unused2 = 0,
	204	.orig_video_ega_bx = 0,
	205	.unused3 = 0,
	206	.orig_video_lines = 25,
	207	.orig_video_isVGA = VIDEO_TYPE_VGAC,
	208	.orig_video_points = 16
	209	};
	210	}
	211	#endif
	212
750dc31c DV	213	static void __init bonito_quirks_setup(void)
	214	{
	215	char *argptr;
	216
b431f09d	217	argptr = fw_getcmdline();
750dc31c DV	218	if (strstr(argptr, "debug")) {
750dc31c DV	219	BONITO_BONGENCFG \|= BONITO_BONGENCFG_DEBUGMODE;
49bffbdc	220	pr_info("Enabled Bonito debug mode\n");
750dc31c DV	221	} else
	222	BONITO_BONGENCFG &= ~BONITO_BONGENCFG_DEBUGMODE;
	223
	224	#ifdef CONFIG_DMA_COHERENT
	225	if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) {
	226	BONITO_PCICACHECTRL \|= BONITO_PCICACHECTRL_CPUCOH_EN;
49bffbdc	227	pr_info("Enabled Bonito CPU coherency\n");
750dc31c	228
b431f09d	229	argptr = fw_getcmdline();
750dc31c DV	230	if (strstr(argptr, "iobcuncached")) {
	231	BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN;
	232	BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG &
	233	~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED \|
	234	BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
49bffbdc	235	pr_info("Disabled Bonito IOBC coherency\n");
750dc31c DV	236	} else {
	237	BONITO_PCICACHECTRL \|= BONITO_PCICACHECTRL_IOBCCOH_EN;
	238	BONITO_PCIMEMBASECFG \|=
	239	(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED \|
	240	BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
49bffbdc	241	pr_info("Enabled Bonito IOBC coherency\n");
750dc31c DV	242	}
	243	} else
	244	panic("Hardware DMA cache coherency not supported");
	245	#endif
	246	}
	247
2925aba4	248	void __init plat_mem_setup(void)
1da177e4 LT	249	{
	250	unsigned int i;
	251
f8b7faf1 MC	252	if (config_enabled(CONFIG_EVA))
	253	/* EVA has already been configured in mach-malta/kernel-init.h */
	254	pr_info("Enhanced Virtual Addressing (EVA) activated\n");
	255
c83cfc9c RB	256	mips_pcibios_init();
c83cfc9c RB	257
1da177e4 LT	258	/* Request I/O space for devices used on the Malta board. */
	259	for (i = 0; i < ARRAY_SIZE(standard_io_resources); i++)
	260	request_resource(&ioport_resource, standard_io_resources+i);
	261
	262	/*
	263	* Enable DMA channel 4 (cascade channel) in the PIIX4 south bridge.
	264	*/
	265	enable_dma(4);
	266
1da177e4	267	#ifdef CONFIG_DMA_COHERENT
750dc31c	268	if (mips_revision_sconid != MIPS_REVISION_SCON_BONITO)
1da177e4	269	panic("Hardware DMA cache coherency not supported");
1da177e4 LT	270	#endif
1da177e4 LT	271
750dc31c DV	272	if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO)
	273	bonito_quirks_setup();
	274
b6d92b4a SH	275	plat_setup_iocoherency();
b6d92b4a SH	276
f3a4ce95	277	pci_clock_check();
750dc31c	278
1da177e4	279	#ifdef CONFIG_BLK_DEV_FD
49a89efb	280	fd_activate();
1da177e4	281	#endif
750dc31c	282
a382963e DV	283	#if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE)
a382963e DV	284	screen_info_setup();
1da177e4	285	#endif
39b8d525 RB	286
	287	board_be_init = malta_be_init;
	288	board_be_handler = malta_be_handler;
1da177e4	289	}