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1da177e4 LT |
1 | /* |
2 | * Carsten Langgaard, carstenl@mips.com | |
3 | * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. | |
4 | * | |
5 | * This program is free software; you can distribute it and/or modify it | |
6 | * under the terms of the GNU General Public License (Version 2) as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 | * for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along | |
15 | * with this program; if not, write to the Free Software Foundation, Inc., | |
16 | * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. | |
17 | * | |
18 | * Setting up the clock on the MIPS boards. | |
19 | */ | |
20 | ||
21 | #include <linux/types.h> | |
1da177e4 LT |
22 | #include <linux/init.h> |
23 | #include <linux/kernel_stat.h> | |
24 | #include <linux/sched.h> | |
25 | #include <linux/spinlock.h> | |
26 | #include <linux/interrupt.h> | |
27 | #include <linux/time.h> | |
28 | #include <linux/timex.h> | |
29 | #include <linux/mc146818rtc.h> | |
30 | ||
31 | #include <asm/mipsregs.h> | |
41c594ab | 32 | #include <asm/mipsmtregs.h> |
e01402b1 | 33 | #include <asm/hardirq.h> |
d865bea4 | 34 | #include <asm/i8253.h> |
e01402b1 | 35 | #include <asm/irq.h> |
1da177e4 LT |
36 | #include <asm/div64.h> |
37 | #include <asm/cpu.h> | |
38 | #include <asm/time.h> | |
39 | #include <asm/mc146818-time.h> | |
e01402b1 | 40 | #include <asm/msc01_ic.h> |
1da177e4 LT |
41 | |
42 | #include <asm/mips-boards/generic.h> | |
43 | #include <asm/mips-boards/prom.h> | |
fc095a90 | 44 | |
e01402b1 | 45 | #include <asm/mips-boards/maltaint.h> |
1da177e4 LT |
46 | |
47 | unsigned long cpu_khz; | |
48 | ||
e01402b1 | 49 | static int mips_cpu_timer_irq; |
39b8d525 | 50 | static int mips_cpu_perf_irq; |
3b1d4ed5 | 51 | extern int cp0_perfcount_irq; |
1da177e4 | 52 | |
937a8015 | 53 | static void mips_timer_dispatch(void) |
1da177e4 | 54 | { |
937a8015 | 55 | do_IRQ(mips_cpu_timer_irq); |
e01402b1 RB |
56 | } |
57 | ||
ffe9ee47 CD |
58 | static void mips_perf_dispatch(void) |
59 | { | |
39b8d525 | 60 | do_IRQ(mips_cpu_perf_irq); |
ffe9ee47 CD |
61 | } |
62 | ||
1da177e4 | 63 | /* |
224dc50e | 64 | * Estimate CPU frequency. Sets mips_hpt_frequency as a side-effect |
1da177e4 LT |
65 | */ |
66 | static unsigned int __init estimate_cpu_frequency(void) | |
67 | { | |
68 | unsigned int prid = read_c0_prid() & 0xffff00; | |
69 | unsigned int count; | |
70 | ||
e79f55a8 | 71 | unsigned long flags; |
70e46f48 | 72 | unsigned int start; |
1da177e4 LT |
73 | |
74 | local_irq_save(flags); | |
75 | ||
76 | /* Start counter exactly on falling edge of update flag */ | |
77 | while (CMOS_READ(RTC_REG_A) & RTC_UIP); | |
78 | while (!(CMOS_READ(RTC_REG_A) & RTC_UIP)); | |
79 | ||
80 | /* Start r4k counter. */ | |
70e46f48 | 81 | start = read_c0_count(); |
1da177e4 LT |
82 | |
83 | /* Read counter exactly on falling edge of update flag */ | |
84 | while (CMOS_READ(RTC_REG_A) & RTC_UIP); | |
85 | while (!(CMOS_READ(RTC_REG_A) & RTC_UIP)); | |
86 | ||
70e46f48 | 87 | count = read_c0_count() - start; |
1da177e4 LT |
88 | |
89 | /* restore interrupts */ | |
90 | local_irq_restore(flags); | |
1da177e4 LT |
91 | |
92 | mips_hpt_frequency = count; | |
93 | if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) && | |
94 | (prid != (PRID_COMP_MIPS | PRID_IMP_25KF))) | |
95 | count *= 2; | |
96 | ||
97 | count += 5000; /* round */ | |
98 | count -= count%10000; | |
99 | ||
100 | return count; | |
101 | } | |
102 | ||
4b550488 | 103 | unsigned long read_persistent_clock(void) |
1da177e4 LT |
104 | { |
105 | return mc146818_get_cmos_time(); | |
106 | } | |
107 | ||
b31dc3c4 | 108 | static void __init plat_perf_setup(void) |
ffe9ee47 | 109 | { |
f75f369f | 110 | #ifdef MSC01E_INT_BASE |
e01402b1 | 111 | if (cpu_has_veic) { |
49a89efb | 112 | set_vi_handler(MSC01E_INT_PERFCTR, mips_perf_dispatch); |
39b8d525 | 113 | mips_cpu_perf_irq = MSC01E_INT_BASE + MSC01E_INT_PERFCTR; |
f75f369f AN |
114 | } else |
115 | #endif | |
3b1d4ed5 RB |
116 | if (cp0_perfcount_irq >= 0) { |
117 | if (cpu_has_vint) | |
118 | set_vi_handler(cp0_perfcount_irq, mips_perf_dispatch); | |
39b8d525 | 119 | mips_cpu_perf_irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq; |
ffe9ee47 | 120 | #ifdef CONFIG_SMP |
39b8d525 | 121 | set_irq_handler(mips_cpu_perf_irq, handle_percpu_irq); |
ffe9ee47 | 122 | #endif |
e01402b1 | 123 | } |
ffe9ee47 | 124 | } |
e01402b1 | 125 | |
234fcd14 | 126 | unsigned int __cpuinit get_c0_compare_int(void) |
ffe9ee47 | 127 | { |
7b4f4ec2 | 128 | #ifdef MSC01E_INT_BASE |
ffe9ee47 | 129 | if (cpu_has_veic) { |
49a89efb | 130 | set_vi_handler(MSC01E_INT_CPUCTR, mips_timer_dispatch); |
ffe9ee47 | 131 | mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR; |
38760d40 | 132 | } else |
7b4f4ec2 CD |
133 | #endif |
134 | { | |
ffe9ee47 | 135 | if (cpu_has_vint) |
3b1d4ed5 RB |
136 | set_vi_handler(cp0_compare_irq, mips_timer_dispatch); |
137 | mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq; | |
ffe9ee47 | 138 | } |
e01402b1 | 139 | |
38760d40 RB |
140 | return mips_cpu_timer_irq; |
141 | } | |
142 | ||
143 | void __init plat_time_init(void) | |
144 | { | |
145 | unsigned int est_freq; | |
146 | ||
147 | /* Set Data mode - binary. */ | |
148 | CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL); | |
149 | ||
150 | est_freq = estimate_cpu_frequency(); | |
151 | ||
152 | printk("CPU frequency %d.%02d MHz\n", est_freq/1000000, | |
153 | (est_freq%1000000)*100/1000000); | |
154 | ||
155 | cpu_khz = est_freq / 1000; | |
156 | ||
157 | mips_scroll_message(); | |
158 | #ifdef CONFIG_I8253 /* Only Malta has a PIT */ | |
159 | setup_pit_timer(); | |
340ee4b9 | 160 | #endif |
ffe9ee47 | 161 | |
91a2fcc8 | 162 | plat_perf_setup(); |
1da177e4 | 163 | } |