Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Carsten Langgaard, carstenl@mips.com | |
3 | * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. | |
4 | * | |
5 | * This program is free software; you can distribute it and/or modify it | |
6 | * under the terms of the GNU General Public License (Version 2) as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 | * for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along | |
15 | * with this program; if not, write to the Free Software Foundation, Inc., | |
16 | * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. | |
17 | * | |
18 | * Setting up the clock on the MIPS boards. | |
19 | */ | |
1da177e4 | 20 | #include <linux/types.h> |
334955ef | 21 | #include <linux/i8253.h> |
1da177e4 LT |
22 | #include <linux/init.h> |
23 | #include <linux/kernel_stat.h> | |
24 | #include <linux/sched.h> | |
25 | #include <linux/spinlock.h> | |
26 | #include <linux/interrupt.h> | |
1da177e4 LT |
27 | #include <linux/timex.h> |
28 | #include <linux/mc146818rtc.h> | |
29 | ||
8ff374b9 | 30 | #include <asm/cpu.h> |
1da177e4 | 31 | #include <asm/mipsregs.h> |
41c594ab | 32 | #include <asm/mipsmtregs.h> |
e01402b1 RB |
33 | #include <asm/hardirq.h> |
34 | #include <asm/irq.h> | |
1da177e4 | 35 | #include <asm/div64.h> |
b81947c6 | 36 | #include <asm/setup.h> |
1da177e4 LT |
37 | #include <asm/time.h> |
38 | #include <asm/mc146818-time.h> | |
e01402b1 | 39 | #include <asm/msc01_ic.h> |
778eeb1b | 40 | #include <asm/gic.h> |
1da177e4 LT |
41 | |
42 | #include <asm/mips-boards/generic.h> | |
e01402b1 | 43 | #include <asm/mips-boards/maltaint.h> |
1da177e4 LT |
44 | |
45 | unsigned long cpu_khz; | |
46 | ||
e01402b1 | 47 | static int mips_cpu_timer_irq; |
39b8d525 | 48 | static int mips_cpu_perf_irq; |
3b1d4ed5 | 49 | extern int cp0_perfcount_irq; |
1da177e4 | 50 | |
937a8015 | 51 | static void mips_timer_dispatch(void) |
1da177e4 | 52 | { |
937a8015 | 53 | do_IRQ(mips_cpu_timer_irq); |
e01402b1 RB |
54 | } |
55 | ||
ffe9ee47 CD |
56 | static void mips_perf_dispatch(void) |
57 | { | |
39b8d525 | 58 | do_IRQ(mips_cpu_perf_irq); |
ffe9ee47 CD |
59 | } |
60 | ||
778eeb1b SH |
61 | static unsigned int freqround(unsigned int freq, unsigned int amount) |
62 | { | |
63 | freq += amount; | |
64 | freq -= freq % (amount*2); | |
65 | return freq; | |
66 | } | |
67 | ||
1da177e4 | 68 | /* |
778eeb1b | 69 | * Estimate CPU and GIC frequencies. |
1da177e4 | 70 | */ |
778eeb1b | 71 | static void __init estimate_frequencies(void) |
1da177e4 | 72 | { |
e79f55a8 | 73 | unsigned long flags; |
778eeb1b | 74 | unsigned int count, start; |
dfa762e1 | 75 | #ifdef CONFIG_IRQ_GIC |
778eeb1b | 76 | unsigned int giccount = 0, gicstart = 0; |
dfa762e1 | 77 | #endif |
1da177e4 | 78 | |
9843b030 | 79 | #if defined (CONFIG_KVM_GUEST) && defined (CONFIG_KVM_HOST_FREQ) |
8ff374b9 | 80 | unsigned int prid = read_c0_prid() & (PRID_COMP_MASK | PRID_IMP_MASK); |
9843b030 SL |
81 | |
82 | /* | |
83 | * XXXKYMA: hardwire the CPU frequency to Host Freq/4 | |
84 | */ | |
85 | count = (CONFIG_KVM_HOST_FREQ * 1000000) >> 3; | |
86 | if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) && | |
87 | (prid != (PRID_COMP_MIPS | PRID_IMP_25KF))) | |
88 | count *= 2; | |
89 | ||
90 | mips_hpt_frequency = count; | |
91 | return; | |
92 | #endif | |
93 | ||
1da177e4 LT |
94 | local_irq_save(flags); |
95 | ||
778eeb1b | 96 | /* Start counter exactly on falling edge of update flag. */ |
1da177e4 LT |
97 | while (CMOS_READ(RTC_REG_A) & RTC_UIP); |
98 | while (!(CMOS_READ(RTC_REG_A) & RTC_UIP)); | |
99 | ||
778eeb1b | 100 | /* Initialize counters. */ |
70e46f48 | 101 | start = read_c0_count(); |
dfa762e1 | 102 | #ifdef CONFIG_IRQ_GIC |
778eeb1b SH |
103 | if (gic_present) |
104 | GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_31_00), gicstart); | |
dfa762e1 | 105 | #endif |
1da177e4 | 106 | |
778eeb1b | 107 | /* Read counter exactly on falling edge of update flag. */ |
1da177e4 LT |
108 | while (CMOS_READ(RTC_REG_A) & RTC_UIP); |
109 | while (!(CMOS_READ(RTC_REG_A) & RTC_UIP)); | |
110 | ||
778eeb1b | 111 | count = read_c0_count(); |
dfa762e1 | 112 | #ifdef CONFIG_IRQ_GIC |
778eeb1b SH |
113 | if (gic_present) |
114 | GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_31_00), giccount); | |
dfa762e1 | 115 | #endif |
1da177e4 | 116 | |
1da177e4 | 117 | local_irq_restore(flags); |
1da177e4 | 118 | |
778eeb1b | 119 | count -= start; |
778eeb1b | 120 | mips_hpt_frequency = count; |
dfa762e1 SH |
121 | |
122 | #ifdef CONFIG_IRQ_GIC | |
123 | if (gic_present) { | |
124 | giccount -= gicstart; | |
778eeb1b | 125 | gic_frequency = giccount; |
dfa762e1 SH |
126 | } |
127 | #endif | |
1da177e4 LT |
128 | } |
129 | ||
d4f587c6 | 130 | void read_persistent_clock(struct timespec *ts) |
1da177e4 | 131 | { |
d4f587c6 MS |
132 | ts->tv_sec = mc146818_get_cmos_time(); |
133 | ts->tv_nsec = 0; | |
1da177e4 LT |
134 | } |
135 | ||
b31dc3c4 | 136 | static void __init plat_perf_setup(void) |
ffe9ee47 | 137 | { |
f75f369f | 138 | #ifdef MSC01E_INT_BASE |
e01402b1 | 139 | if (cpu_has_veic) { |
49a89efb | 140 | set_vi_handler(MSC01E_INT_PERFCTR, mips_perf_dispatch); |
39b8d525 | 141 | mips_cpu_perf_irq = MSC01E_INT_BASE + MSC01E_INT_PERFCTR; |
f75f369f AN |
142 | } else |
143 | #endif | |
3b1d4ed5 RB |
144 | if (cp0_perfcount_irq >= 0) { |
145 | if (cpu_has_vint) | |
146 | set_vi_handler(cp0_perfcount_irq, mips_perf_dispatch); | |
39b8d525 | 147 | mips_cpu_perf_irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq; |
ffe9ee47 | 148 | #ifdef CONFIG_SMP |
e4ec7989 | 149 | irq_set_handler(mips_cpu_perf_irq, handle_percpu_irq); |
ffe9ee47 | 150 | #endif |
e01402b1 | 151 | } |
ffe9ee47 | 152 | } |
e01402b1 | 153 | |
078a55fc | 154 | unsigned int get_c0_compare_int(void) |
ffe9ee47 | 155 | { |
7b4f4ec2 | 156 | #ifdef MSC01E_INT_BASE |
ffe9ee47 | 157 | if (cpu_has_veic) { |
49a89efb | 158 | set_vi_handler(MSC01E_INT_CPUCTR, mips_timer_dispatch); |
ffe9ee47 | 159 | mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR; |
38760d40 | 160 | } else |
7b4f4ec2 CD |
161 | #endif |
162 | { | |
ffe9ee47 | 163 | if (cpu_has_vint) |
3b1d4ed5 RB |
164 | set_vi_handler(cp0_compare_irq, mips_timer_dispatch); |
165 | mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq; | |
ffe9ee47 | 166 | } |
e01402b1 | 167 | |
38760d40 RB |
168 | return mips_cpu_timer_irq; |
169 | } | |
170 | ||
171 | void __init plat_time_init(void) | |
172 | { | |
8ff374b9 | 173 | unsigned int prid = read_c0_prid() & (PRID_COMP_MASK | PRID_IMP_MASK); |
778eeb1b | 174 | unsigned int freq; |
38760d40 | 175 | |
778eeb1b | 176 | estimate_frequencies(); |
38760d40 | 177 | |
778eeb1b SH |
178 | freq = mips_hpt_frequency; |
179 | if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) && | |
180 | (prid != (PRID_COMP_MIPS | PRID_IMP_25KF))) | |
181 | freq *= 2; | |
182 | freq = freqround(freq, 5000); | |
dfa762e1 | 183 | printk("CPU frequency %d.%02d MHz\n", freq/1000000, |
778eeb1b SH |
184 | (freq%1000000)*100/1000000); |
185 | cpu_khz = freq / 1000; | |
186 | ||
dfa762e1 | 187 | mips_scroll_message(); |
38760d40 | 188 | |
778eeb1b SH |
189 | #ifdef CONFIG_I8253 |
190 | /* Only Malta has a PIT. */ | |
38760d40 | 191 | setup_pit_timer(); |
340ee4b9 | 192 | #endif |
ffe9ee47 | 193 | |
dfa762e1 SH |
194 | #ifdef CONFIG_IRQ_GIC |
195 | if (gic_present) { | |
196 | freq = freqround(gic_frequency, 5000); | |
197 | printk("GIC frequency %d.%02d MHz\n", freq/1000000, | |
198 | (freq%1000000)*100/1000000); | |
199 | #ifdef CONFIG_CSRC_GIC | |
200 | gic_clocksource_init(gic_frequency); | |
201 | #endif | |
202 | } | |
203 | #endif | |
778eeb1b | 204 | |
91a2fcc8 | 205 | plat_perf_setup(); |
1da177e4 | 206 | } |