Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Carsten Langgaard, carstenl@mips.com | |
3 | * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. | |
4 | * | |
5 | * This program is free software; you can distribute it and/or modify it | |
6 | * under the terms of the GNU General Public License (Version 2) as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 | * for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along | |
15 | * with this program; if not, write to the Free Software Foundation, Inc., | |
16 | * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. | |
17 | * | |
18 | * Setting up the clock on the MIPS boards. | |
19 | */ | |
1da177e4 | 20 | #include <linux/types.h> |
334955ef | 21 | #include <linux/i8253.h> |
1da177e4 LT |
22 | #include <linux/init.h> |
23 | #include <linux/kernel_stat.h> | |
24 | #include <linux/sched.h> | |
25 | #include <linux/spinlock.h> | |
26 | #include <linux/interrupt.h> | |
4060bbe9 | 27 | #include <linux/irqchip/mips-gic.h> |
1da177e4 LT |
28 | #include <linux/timex.h> |
29 | #include <linux/mc146818rtc.h> | |
30 | ||
8ff374b9 | 31 | #include <asm/cpu.h> |
1da177e4 | 32 | #include <asm/mipsregs.h> |
41c594ab | 33 | #include <asm/mipsmtregs.h> |
e01402b1 RB |
34 | #include <asm/hardirq.h> |
35 | #include <asm/irq.h> | |
1da177e4 | 36 | #include <asm/div64.h> |
b81947c6 | 37 | #include <asm/setup.h> |
1da177e4 LT |
38 | #include <asm/time.h> |
39 | #include <asm/mc146818-time.h> | |
e01402b1 | 40 | #include <asm/msc01_ic.h> |
1da177e4 LT |
41 | |
42 | #include <asm/mips-boards/generic.h> | |
e01402b1 | 43 | #include <asm/mips-boards/maltaint.h> |
1da177e4 | 44 | |
e01402b1 | 45 | static int mips_cpu_timer_irq; |
39b8d525 | 46 | static int mips_cpu_perf_irq; |
3b1d4ed5 | 47 | extern int cp0_perfcount_irq; |
1da177e4 | 48 | |
b0854514 AB |
49 | static unsigned int gic_frequency; |
50 | ||
937a8015 | 51 | static void mips_timer_dispatch(void) |
1da177e4 | 52 | { |
937a8015 | 53 | do_IRQ(mips_cpu_timer_irq); |
e01402b1 RB |
54 | } |
55 | ||
ffe9ee47 CD |
56 | static void mips_perf_dispatch(void) |
57 | { | |
39b8d525 | 58 | do_IRQ(mips_cpu_perf_irq); |
ffe9ee47 CD |
59 | } |
60 | ||
778eeb1b SH |
61 | static unsigned int freqround(unsigned int freq, unsigned int amount) |
62 | { | |
63 | freq += amount; | |
64 | freq -= freq % (amount*2); | |
65 | return freq; | |
66 | } | |
67 | ||
1da177e4 | 68 | /* |
778eeb1b | 69 | * Estimate CPU and GIC frequencies. |
1da177e4 | 70 | */ |
778eeb1b | 71 | static void __init estimate_frequencies(void) |
1da177e4 | 72 | { |
e79f55a8 | 73 | unsigned long flags; |
778eeb1b | 74 | unsigned int count, start; |
7d9ad5d8 | 75 | cycle_t giccount = 0, gicstart = 0; |
1da177e4 | 76 | |
eda3d33c JH |
77 | #if defined(CONFIG_KVM_GUEST) && CONFIG_KVM_GUEST_TIMER_FREQ |
78 | mips_hpt_frequency = CONFIG_KVM_GUEST_TIMER_FREQ * 1000000; | |
9843b030 SL |
79 | return; |
80 | #endif | |
81 | ||
1da177e4 LT |
82 | local_irq_save(flags); |
83 | ||
778eeb1b | 84 | /* Start counter exactly on falling edge of update flag. */ |
1da177e4 LT |
85 | while (CMOS_READ(RTC_REG_A) & RTC_UIP); |
86 | while (!(CMOS_READ(RTC_REG_A) & RTC_UIP)); | |
87 | ||
778eeb1b | 88 | /* Initialize counters. */ |
70e46f48 | 89 | start = read_c0_count(); |
778eeb1b | 90 | if (gic_present) |
7d9ad5d8 | 91 | gicstart = gic_read_count(); |
1da177e4 | 92 | |
778eeb1b | 93 | /* Read counter exactly on falling edge of update flag. */ |
1da177e4 LT |
94 | while (CMOS_READ(RTC_REG_A) & RTC_UIP); |
95 | while (!(CMOS_READ(RTC_REG_A) & RTC_UIP)); | |
96 | ||
778eeb1b SH |
97 | count = read_c0_count(); |
98 | if (gic_present) | |
7d9ad5d8 | 99 | giccount = gic_read_count(); |
1da177e4 | 100 | |
1da177e4 | 101 | local_irq_restore(flags); |
1da177e4 | 102 | |
778eeb1b | 103 | count -= start; |
778eeb1b | 104 | mips_hpt_frequency = count; |
dfa762e1 | 105 | |
dfa762e1 SH |
106 | if (gic_present) { |
107 | giccount -= gicstart; | |
778eeb1b | 108 | gic_frequency = giccount; |
dfa762e1 | 109 | } |
1da177e4 LT |
110 | } |
111 | ||
d4f587c6 | 112 | void read_persistent_clock(struct timespec *ts) |
1da177e4 | 113 | { |
d4f587c6 MS |
114 | ts->tv_sec = mc146818_get_cmos_time(); |
115 | ts->tv_nsec = 0; | |
1da177e4 LT |
116 | } |
117 | ||
a669efc4 | 118 | int get_c0_perfcount_int(void) |
ffe9ee47 | 119 | { |
e01402b1 | 120 | if (cpu_has_veic) { |
49a89efb | 121 | set_vi_handler(MSC01E_INT_PERFCTR, mips_perf_dispatch); |
39b8d525 | 122 | mips_cpu_perf_irq = MSC01E_INT_BASE + MSC01E_INT_PERFCTR; |
e9de688d AB |
123 | } else if (gic_present) { |
124 | mips_cpu_perf_irq = gic_get_c0_perfcount_int(); | |
a669efc4 | 125 | } else if (cp0_perfcount_irq >= 0) { |
39b8d525 | 126 | mips_cpu_perf_irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq; |
a669efc4 AB |
127 | } else { |
128 | mips_cpu_perf_irq = -1; | |
e01402b1 | 129 | } |
a669efc4 AB |
130 | |
131 | return mips_cpu_perf_irq; | |
ffe9ee47 | 132 | } |
e01402b1 | 133 | |
078a55fc | 134 | unsigned int get_c0_compare_int(void) |
ffe9ee47 | 135 | { |
ffe9ee47 | 136 | if (cpu_has_veic) { |
49a89efb | 137 | set_vi_handler(MSC01E_INT_CPUCTR, mips_timer_dispatch); |
ffe9ee47 | 138 | mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR; |
e9de688d AB |
139 | } else if (gic_present) { |
140 | mips_cpu_timer_irq = gic_get_c0_compare_int(); | |
141 | } else { | |
3b1d4ed5 | 142 | mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq; |
ffe9ee47 | 143 | } |
e01402b1 | 144 | |
38760d40 RB |
145 | return mips_cpu_timer_irq; |
146 | } | |
147 | ||
a87ea88d PB |
148 | static void __init init_rtc(void) |
149 | { | |
150 | /* stop the clock whilst setting it up */ | |
151 | CMOS_WRITE(RTC_SET | RTC_24H, RTC_CONTROL); | |
152 | ||
153 | /* 32KHz time base */ | |
154 | CMOS_WRITE(RTC_REF_CLCK_32KHZ, RTC_FREQ_SELECT); | |
155 | ||
156 | /* start the clock */ | |
157 | CMOS_WRITE(RTC_24H, RTC_CONTROL); | |
158 | } | |
159 | ||
38760d40 RB |
160 | void __init plat_time_init(void) |
161 | { | |
8ff374b9 | 162 | unsigned int prid = read_c0_prid() & (PRID_COMP_MASK | PRID_IMP_MASK); |
778eeb1b | 163 | unsigned int freq; |
38760d40 | 164 | |
a87ea88d | 165 | init_rtc(); |
778eeb1b | 166 | estimate_frequencies(); |
38760d40 | 167 | |
778eeb1b SH |
168 | freq = mips_hpt_frequency; |
169 | if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) && | |
170 | (prid != (PRID_COMP_MIPS | PRID_IMP_25KF))) | |
171 | freq *= 2; | |
172 | freq = freqround(freq, 5000); | |
dfa762e1 | 173 | printk("CPU frequency %d.%02d MHz\n", freq/1000000, |
778eeb1b | 174 | (freq%1000000)*100/1000000); |
778eeb1b | 175 | |
dfa762e1 | 176 | mips_scroll_message(); |
38760d40 | 177 | |
778eeb1b SH |
178 | #ifdef CONFIG_I8253 |
179 | /* Only Malta has a PIT. */ | |
38760d40 | 180 | setup_pit_timer(); |
340ee4b9 | 181 | #endif |
ffe9ee47 | 182 | |
8a19b8f1 | 183 | #ifdef CONFIG_MIPS_GIC |
dfa762e1 SH |
184 | if (gic_present) { |
185 | freq = freqround(gic_frequency, 5000); | |
186 | printk("GIC frequency %d.%02d MHz\n", freq/1000000, | |
187 | (freq%1000000)*100/1000000); | |
fa5635a2 | 188 | #ifdef CONFIG_CLKSRC_MIPS_GIC |
dfa762e1 SH |
189 | gic_clocksource_init(gic_frequency); |
190 | #endif | |
191 | } | |
192 | #endif | |
1da177e4 | 193 | } |