Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Carsten Langgaard, carstenl@mips.com | |
3 | * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. | |
4 | * | |
5 | * This program is free software; you can distribute it and/or modify it | |
6 | * under the terms of the GNU General Public License (Version 2) as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 | * for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along | |
15 | * with this program; if not, write to the Free Software Foundation, Inc., | |
16 | * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. | |
17 | * | |
18 | * Setting up the clock on the MIPS boards. | |
19 | */ | |
1da177e4 | 20 | #include <linux/types.h> |
334955ef | 21 | #include <linux/i8253.h> |
1da177e4 LT |
22 | #include <linux/init.h> |
23 | #include <linux/kernel_stat.h> | |
24 | #include <linux/sched.h> | |
25 | #include <linux/spinlock.h> | |
26 | #include <linux/interrupt.h> | |
1da177e4 LT |
27 | #include <linux/timex.h> |
28 | #include <linux/mc146818rtc.h> | |
29 | ||
30 | #include <asm/mipsregs.h> | |
41c594ab | 31 | #include <asm/mipsmtregs.h> |
e01402b1 RB |
32 | #include <asm/hardirq.h> |
33 | #include <asm/irq.h> | |
1da177e4 | 34 | #include <asm/div64.h> |
b81947c6 | 35 | #include <asm/setup.h> |
1da177e4 LT |
36 | #include <asm/time.h> |
37 | #include <asm/mc146818-time.h> | |
e01402b1 | 38 | #include <asm/msc01_ic.h> |
778eeb1b | 39 | #include <asm/gic.h> |
1da177e4 LT |
40 | |
41 | #include <asm/mips-boards/generic.h> | |
42 | #include <asm/mips-boards/prom.h> | |
fc095a90 | 43 | |
e01402b1 | 44 | #include <asm/mips-boards/maltaint.h> |
1da177e4 LT |
45 | |
46 | unsigned long cpu_khz; | |
778eeb1b | 47 | int gic_frequency; |
1da177e4 | 48 | |
e01402b1 | 49 | static int mips_cpu_timer_irq; |
39b8d525 | 50 | static int mips_cpu_perf_irq; |
3b1d4ed5 | 51 | extern int cp0_perfcount_irq; |
1da177e4 | 52 | |
937a8015 | 53 | static void mips_timer_dispatch(void) |
1da177e4 | 54 | { |
937a8015 | 55 | do_IRQ(mips_cpu_timer_irq); |
e01402b1 RB |
56 | } |
57 | ||
ffe9ee47 CD |
58 | static void mips_perf_dispatch(void) |
59 | { | |
39b8d525 | 60 | do_IRQ(mips_cpu_perf_irq); |
ffe9ee47 CD |
61 | } |
62 | ||
778eeb1b SH |
63 | static unsigned int freqround(unsigned int freq, unsigned int amount) |
64 | { | |
65 | freq += amount; | |
66 | freq -= freq % (amount*2); | |
67 | return freq; | |
68 | } | |
69 | ||
1da177e4 | 70 | /* |
778eeb1b | 71 | * Estimate CPU and GIC frequencies. |
1da177e4 | 72 | */ |
778eeb1b | 73 | static void __init estimate_frequencies(void) |
1da177e4 | 74 | { |
e79f55a8 | 75 | unsigned long flags; |
778eeb1b SH |
76 | unsigned int count, start; |
77 | unsigned int giccount = 0, gicstart = 0; | |
1da177e4 LT |
78 | |
79 | local_irq_save(flags); | |
80 | ||
778eeb1b | 81 | /* Start counter exactly on falling edge of update flag. */ |
1da177e4 LT |
82 | while (CMOS_READ(RTC_REG_A) & RTC_UIP); |
83 | while (!(CMOS_READ(RTC_REG_A) & RTC_UIP)); | |
84 | ||
778eeb1b | 85 | /* Initialize counters. */ |
70e46f48 | 86 | start = read_c0_count(); |
778eeb1b SH |
87 | if (gic_present) |
88 | GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_31_00), gicstart); | |
1da177e4 | 89 | |
778eeb1b | 90 | /* Read counter exactly on falling edge of update flag. */ |
1da177e4 LT |
91 | while (CMOS_READ(RTC_REG_A) & RTC_UIP); |
92 | while (!(CMOS_READ(RTC_REG_A) & RTC_UIP)); | |
93 | ||
778eeb1b SH |
94 | count = read_c0_count(); |
95 | if (gic_present) | |
96 | GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_31_00), giccount); | |
1da177e4 | 97 | |
1da177e4 | 98 | local_irq_restore(flags); |
1da177e4 | 99 | |
778eeb1b SH |
100 | count -= start; |
101 | if (gic_present) | |
102 | giccount -= gicstart; | |
1da177e4 | 103 | |
778eeb1b SH |
104 | mips_hpt_frequency = count; |
105 | if (gic_present) | |
106 | gic_frequency = giccount; | |
1da177e4 LT |
107 | } |
108 | ||
d4f587c6 | 109 | void read_persistent_clock(struct timespec *ts) |
1da177e4 | 110 | { |
d4f587c6 MS |
111 | ts->tv_sec = mc146818_get_cmos_time(); |
112 | ts->tv_nsec = 0; | |
1da177e4 LT |
113 | } |
114 | ||
b31dc3c4 | 115 | static void __init plat_perf_setup(void) |
ffe9ee47 | 116 | { |
f75f369f | 117 | #ifdef MSC01E_INT_BASE |
e01402b1 | 118 | if (cpu_has_veic) { |
49a89efb | 119 | set_vi_handler(MSC01E_INT_PERFCTR, mips_perf_dispatch); |
39b8d525 | 120 | mips_cpu_perf_irq = MSC01E_INT_BASE + MSC01E_INT_PERFCTR; |
f75f369f AN |
121 | } else |
122 | #endif | |
3b1d4ed5 RB |
123 | if (cp0_perfcount_irq >= 0) { |
124 | if (cpu_has_vint) | |
125 | set_vi_handler(cp0_perfcount_irq, mips_perf_dispatch); | |
39b8d525 | 126 | mips_cpu_perf_irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq; |
ffe9ee47 | 127 | #ifdef CONFIG_SMP |
e4ec7989 | 128 | irq_set_handler(mips_cpu_perf_irq, handle_percpu_irq); |
ffe9ee47 | 129 | #endif |
e01402b1 | 130 | } |
ffe9ee47 | 131 | } |
e01402b1 | 132 | |
234fcd14 | 133 | unsigned int __cpuinit get_c0_compare_int(void) |
ffe9ee47 | 134 | { |
7b4f4ec2 | 135 | #ifdef MSC01E_INT_BASE |
ffe9ee47 | 136 | if (cpu_has_veic) { |
49a89efb | 137 | set_vi_handler(MSC01E_INT_CPUCTR, mips_timer_dispatch); |
ffe9ee47 | 138 | mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR; |
38760d40 | 139 | } else |
7b4f4ec2 CD |
140 | #endif |
141 | { | |
ffe9ee47 | 142 | if (cpu_has_vint) |
3b1d4ed5 RB |
143 | set_vi_handler(cp0_compare_irq, mips_timer_dispatch); |
144 | mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq; | |
ffe9ee47 | 145 | } |
e01402b1 | 146 | |
38760d40 RB |
147 | return mips_cpu_timer_irq; |
148 | } | |
149 | ||
150 | void __init plat_time_init(void) | |
151 | { | |
778eeb1b SH |
152 | unsigned int prid = read_c0_prid() & 0xffff00; |
153 | unsigned int freq; | |
38760d40 | 154 | |
778eeb1b | 155 | estimate_frequencies(); |
38760d40 | 156 | |
778eeb1b SH |
157 | freq = mips_hpt_frequency; |
158 | if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) && | |
159 | (prid != (PRID_COMP_MIPS | PRID_IMP_25KF))) | |
160 | freq *= 2; | |
161 | freq = freqround(freq, 5000); | |
162 | pr_debug("CPU frequency %d.%02d MHz\n", freq/1000000, | |
163 | (freq%1000000)*100/1000000); | |
164 | cpu_khz = freq / 1000; | |
165 | ||
166 | if (gic_present) { | |
167 | freq = freqround(gic_frequency, 5000); | |
168 | pr_debug("GIC frequency %d.%02d MHz\n", freq/1000000, | |
169 | (freq%1000000)*100/1000000); | |
170 | gic_clocksource_init(gic_frequency); | |
171 | } else | |
172 | init_r4k_clocksource(); | |
38760d40 | 173 | |
778eeb1b SH |
174 | #ifdef CONFIG_I8253 |
175 | /* Only Malta has a PIT. */ | |
38760d40 | 176 | setup_pit_timer(); |
340ee4b9 | 177 | #endif |
ffe9ee47 | 178 | |
778eeb1b SH |
179 | mips_scroll_message(); |
180 | ||
91a2fcc8 | 181 | plat_perf_setup(); |
1da177e4 | 182 | } |