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5c642506 J |
1 | /* |
2 | * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights | |
3 | * reserved. | |
4 | * | |
5 | * This software is available to you under a choice of one of two | |
6 | * licenses. You may choose to be licensed under the terms of the GNU | |
7 | * General Public License (GPL) Version 2, available from the file | |
8 | * COPYING in the main directory of this source tree, or the NetLogic | |
9 | * license below: | |
10 | * | |
11 | * Redistribution and use in source and binary forms, with or without | |
12 | * modification, are permitted provided that the following conditions | |
13 | * are met: | |
14 | * | |
15 | * 1. Redistributions of source code must retain the above copyright | |
16 | * notice, this list of conditions and the following disclaimer. | |
17 | * 2. Redistributions in binary form must reproduce the above copyright | |
18 | * notice, this list of conditions and the following disclaimer in | |
19 | * the documentation and/or other materials provided with the | |
20 | * distribution. | |
21 | * | |
22 | * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR | |
23 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED | |
24 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |
25 | * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE | |
26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | |
27 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | |
28 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR | |
29 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, | |
30 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE | |
31 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN | |
32 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
33 | */ | |
34 | ||
35 | #include <linux/kernel.h> | |
36 | #include <linux/delay.h> | |
37 | #include <linux/init.h> | |
38 | #include <linux/smp.h> | |
39 | #include <linux/irq.h> | |
40 | ||
41 | #include <asm/mmu_context.h> | |
42 | ||
43 | #include <asm/netlogic/interrupt.h> | |
44 | #include <asm/netlogic/mips-extns.h> | |
0c965407 J |
45 | #include <asm/netlogic/haldefs.h> |
46 | #include <asm/netlogic/common.h> | |
5c642506 | 47 | |
65040e22 J |
48 | #if defined(CONFIG_CPU_XLP) |
49 | #include <asm/netlogic/xlp-hal/iomap.h> | |
66d29985 | 50 | #include <asm/netlogic/xlp-hal/xlp.h> |
65040e22 J |
51 | #include <asm/netlogic/xlp-hal/pic.h> |
52 | #elif defined(CONFIG_CPU_XLR) | |
5c642506 J |
53 | #include <asm/netlogic/xlr/iomap.h> |
54 | #include <asm/netlogic/xlr/pic.h> | |
66d29985 | 55 | #include <asm/netlogic/xlr/xlr.h> |
65040e22 J |
56 | #else |
57 | #error "Unknown CPU" | |
58 | #endif | |
5c642506 | 59 | |
0c965407 | 60 | void nlm_send_ipi_single(int logical_cpu, unsigned int action) |
5c642506 | 61 | { |
77ae798f J |
62 | int cpu, node; |
63 | uint64_t picbase; | |
64 | ||
65 | cpu = cpu_logical_map(logical_cpu); | |
66 | node = cpu / NLM_CPUS_PER_NODE; | |
67 | picbase = nlm_get_node(node)->picbase; | |
5c642506 J |
68 | |
69 | if (action & SMP_CALL_FUNCTION) | |
77ae798f | 70 | nlm_pic_send_ipi(picbase, cpu, IRQ_IPI_SMP_FUNCTION, 0); |
0c965407 | 71 | if (action & SMP_RESCHEDULE_YOURSELF) |
77ae798f | 72 | nlm_pic_send_ipi(picbase, cpu, IRQ_IPI_SMP_RESCHEDULE, 0); |
5c642506 J |
73 | } |
74 | ||
75 | void nlm_send_ipi_mask(const struct cpumask *mask, unsigned int action) | |
76 | { | |
77 | int cpu; | |
78 | ||
79 | for_each_cpu(cpu, mask) { | |
0c965407 | 80 | nlm_send_ipi_single(cpu, action); |
5c642506 J |
81 | } |
82 | } | |
83 | ||
84 | /* IRQ_IPI_SMP_FUNCTION Handler */ | |
85 | void nlm_smp_function_ipi_handler(unsigned int irq, struct irq_desc *desc) | |
86 | { | |
220d9122 J |
87 | clear_c0_eimr(irq); |
88 | ack_c0_eirr(irq); | |
65040e22 | 89 | smp_call_function_interrupt(); |
220d9122 | 90 | set_c0_eimr(irq); |
5c642506 J |
91 | } |
92 | ||
93 | /* IRQ_IPI_SMP_RESCHEDULE handler */ | |
94 | void nlm_smp_resched_ipi_handler(unsigned int irq, struct irq_desc *desc) | |
95 | { | |
220d9122 J |
96 | clear_c0_eimr(irq); |
97 | ack_c0_eirr(irq); | |
65040e22 | 98 | scheduler_ipi(); |
220d9122 | 99 | set_c0_eimr(irq); |
5c642506 J |
100 | } |
101 | ||
102 | /* | |
103 | * Called before going into mips code, early cpu init | |
104 | */ | |
0c965407 | 105 | void nlm_early_init_secondary(int cpu) |
5c642506 | 106 | { |
65040e22 | 107 | change_c0_config(CONF_CM_CMASK, 0x3); |
65040e22 | 108 | #ifdef CONFIG_CPU_XLP |
5b6ff35d | 109 | xlp_mmu_init(); |
0c965407 | 110 | #endif |
77ae798f | 111 | write_c0_ebase(nlm_current_node()->ebase); |
5c642506 J |
112 | } |
113 | ||
114 | /* | |
115 | * Code to run on secondary just after probing the CPU | |
116 | */ | |
078a55fc | 117 | static void nlm_init_secondary(void) |
5c642506 | 118 | { |
38541742 J |
119 | int hwtid; |
120 | ||
121 | hwtid = hard_smp_processor_id(); | |
122 | current_cpu_data.core = hwtid / NLM_THREADS_PER_CORE; | |
ed21cfe2 | 123 | nlm_percpu_init(hwtid); |
38541742 | 124 | nlm_smp_irq_init(hwtid); |
5c642506 J |
125 | } |
126 | ||
b3ea5818 HD |
127 | void nlm_prepare_cpus(unsigned int max_cpus) |
128 | { | |
129 | /* declare we are SMT capable */ | |
130 | smp_num_siblings = nlm_threads_per_core; | |
131 | } | |
132 | ||
5c642506 J |
133 | void nlm_smp_finish(void) |
134 | { | |
39263eeb | 135 | local_irq_enable(); |
5c642506 J |
136 | } |
137 | ||
138 | void nlm_cpus_done(void) | |
139 | { | |
140 | } | |
141 | ||
142 | /* | |
143 | * Boot all other cpus in the system, initialize them, and bring them into | |
144 | * the boot function | |
145 | */ | |
5c642506 J |
146 | unsigned long nlm_next_gp; |
147 | unsigned long nlm_next_sp; | |
62b734d2 | 148 | static cpumask_t phys_cpu_present_mask; |
5c642506 J |
149 | |
150 | void nlm_boot_secondary(int logical_cpu, struct task_struct *idle) | |
151 | { | |
77ae798f | 152 | int cpu, node; |
5c642506 | 153 | |
77ae798f J |
154 | cpu = cpu_logical_map(logical_cpu); |
155 | node = cpu / NLM_CPUS_PER_NODE; | |
156 | nlm_next_sp = (unsigned long)__KSTK_TOS(idle); | |
157 | nlm_next_gp = (unsigned long)task_thread_info(idle); | |
5c642506 | 158 | |
77ae798f | 159 | /* barrier for sp/gp store above */ |
5c642506 | 160 | __sync(); |
77ae798f | 161 | nlm_pic_send_ipi(nlm_get_node(node)->picbase, cpu, 1, 1); /* NMI */ |
5c642506 J |
162 | } |
163 | ||
164 | void __init nlm_smp_setup(void) | |
165 | { | |
166 | unsigned int boot_cpu; | |
77ae798f | 167 | int num_cpus, i, ncore; |
919f9abb | 168 | volatile u32 *cpu_ready = nlm_get_boot_data(BOOT_CPU_READY); |
62b734d2 | 169 | char buf[64]; |
5c642506 J |
170 | |
171 | boot_cpu = hard_smp_processor_id(); | |
62b734d2 | 172 | cpumask_clear(&phys_cpu_present_mask); |
5c642506 | 173 | |
62b734d2 | 174 | cpumask_set_cpu(boot_cpu, &phys_cpu_present_mask); |
5c642506 J |
175 | __cpu_number_map[boot_cpu] = 0; |
176 | __cpu_logical_map[0] = boot_cpu; | |
0b5f9c00 | 177 | set_cpu_possible(0, true); |
5c642506 J |
178 | |
179 | num_cpus = 1; | |
180 | for (i = 0; i < NR_CPUS; i++) { | |
b2788965 | 181 | /* |
919f9abb | 182 | * cpu_ready array is not set for the boot_cpu, |
0c965407 | 183 | * it is only set for ASPs (see smpboot.S) |
b2788965 | 184 | */ |
919f9abb | 185 | if (cpu_ready[i]) { |
62b734d2 | 186 | cpumask_set_cpu(i, &phys_cpu_present_mask); |
5c642506 J |
187 | __cpu_number_map[i] = num_cpus; |
188 | __cpu_logical_map[num_cpus] = i; | |
0b5f9c00 | 189 | set_cpu_possible(num_cpus, true); |
5c642506 J |
190 | ++num_cpus; |
191 | } | |
192 | } | |
193 | ||
62b734d2 J |
194 | cpumask_scnprintf(buf, ARRAY_SIZE(buf), &phys_cpu_present_mask); |
195 | pr_info("Physical CPU mask: %s\n", buf); | |
196 | cpumask_scnprintf(buf, ARRAY_SIZE(buf), cpu_possible_mask); | |
197 | pr_info("Possible CPU mask: %s\n", buf); | |
198 | ||
77ae798f J |
199 | /* check with the cores we have worken up */ |
200 | for (ncore = 0, i = 0; i < NLM_NR_NODES; i++) | |
201 | ncore += hweight32(nlm_get_node(i)->coremask); | |
202 | ||
77ae798f J |
203 | pr_info("Detected (%dc%dt) %d Slave CPU(s)\n", ncore, |
204 | nlm_threads_per_core, num_cpus); | |
62b734d2 J |
205 | |
206 | /* switch NMI handler to boot CPUs */ | |
66d29985 | 207 | nlm_set_nmi_handler(nlm_boot_secondary_cpus); |
5c642506 J |
208 | } |
209 | ||
2a37b1ae | 210 | static int nlm_parse_cpumask(cpumask_t *wakeup_mask) |
66d29985 J |
211 | { |
212 | uint32_t core0_thr_mask, core_thr_mask; | |
2a37b1ae | 213 | int threadmode, i, j; |
66d29985 | 214 | |
2a37b1ae | 215 | core0_thr_mask = 0; |
77ae798f | 216 | for (i = 0; i < NLM_THREADS_PER_CORE; i++) |
2a37b1ae J |
217 | if (cpumask_test_cpu(i, wakeup_mask)) |
218 | core0_thr_mask |= (1 << i); | |
66d29985 J |
219 | switch (core0_thr_mask) { |
220 | case 1: | |
221 | nlm_threads_per_core = 1; | |
222 | threadmode = 0; | |
223 | break; | |
224 | case 3: | |
225 | nlm_threads_per_core = 2; | |
226 | threadmode = 2; | |
227 | break; | |
228 | case 0xf: | |
229 | nlm_threads_per_core = 4; | |
230 | threadmode = 3; | |
231 | break; | |
232 | default: | |
233 | goto unsupp; | |
234 | } | |
235 | ||
236 | /* Verify other cores CPU masks */ | |
77ae798f | 237 | for (i = 0; i < NR_CPUS; i += NLM_THREADS_PER_CORE) { |
2a37b1ae | 238 | core_thr_mask = 0; |
77ae798f | 239 | for (j = 0; j < NLM_THREADS_PER_CORE; j++) |
2a37b1ae J |
240 | if (cpumask_test_cpu(i + j, wakeup_mask)) |
241 | core_thr_mask |= (1 << j); | |
242 | if (core_thr_mask != 0 && core_thr_mask != core0_thr_mask) | |
66d29985 | 243 | goto unsupp; |
66d29985 J |
244 | } |
245 | return threadmode; | |
246 | ||
247 | unsupp: | |
f7777dcc | 248 | panic("Unsupported CPU mask %lx", |
2a37b1ae | 249 | (unsigned long)cpumask_bits(wakeup_mask)[0]); |
66d29985 J |
250 | return 0; |
251 | } | |
252 | ||
078a55fc | 253 | int nlm_wakeup_secondary_cpus(void) |
66d29985 | 254 | { |
53c83219 | 255 | u32 *reset_data; |
66d29985 J |
256 | int threadmode; |
257 | ||
66d29985 | 258 | /* verify the mask and setup core config variables */ |
2a37b1ae | 259 | threadmode = nlm_parse_cpumask(&nlm_cpumask); |
66d29985 J |
260 | |
261 | /* Setup CPU init parameters */ | |
53c83219 J |
262 | reset_data = nlm_get_boot_data(BOOT_THREAD_MODE); |
263 | *reset_data = threadmode; | |
66d29985 J |
264 | |
265 | #ifdef CONFIG_CPU_XLP | |
266 | xlp_wakeup_secondary_cpus(); | |
267 | #else | |
268 | xlr_wakeup_secondary_cpus(); | |
269 | #endif | |
270 | return 0; | |
271 | } | |
272 | ||
5c642506 J |
273 | struct plat_smp_ops nlm_smp_ops = { |
274 | .send_ipi_single = nlm_send_ipi_single, | |
275 | .send_ipi_mask = nlm_send_ipi_mask, | |
276 | .init_secondary = nlm_init_secondary, | |
277 | .smp_finish = nlm_smp_finish, | |
278 | .cpus_done = nlm_cpus_done, | |
279 | .boot_secondary = nlm_boot_secondary, | |
280 | .smp_setup = nlm_smp_setup, | |
281 | .prepare_cpus = nlm_prepare_cpus, | |
282 | }; |