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65040e22 J |
1 | /* |
2 | * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights | |
3 | * reserved. | |
4 | * | |
5 | * This software is available to you under a choice of one of two | |
6 | * licenses. You may choose to be licensed under the terms of the GNU | |
7 | * General Public License (GPL) Version 2, available from the file | |
8 | * COPYING in the main directory of this source tree, or the NetLogic | |
9 | * license below: | |
10 | * | |
11 | * Redistribution and use in source and binary forms, with or without | |
12 | * modification, are permitted provided that the following conditions | |
13 | * are met: | |
14 | * | |
15 | * 1. Redistributions of source code must retain the above copyright | |
16 | * notice, this list of conditions and the following disclaimer. | |
17 | * 2. Redistributions in binary form must reproduce the above copyright | |
18 | * notice, this list of conditions and the following disclaimer in | |
19 | * the documentation and/or other materials provided with the | |
20 | * distribution. | |
21 | * | |
22 | * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR | |
23 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED | |
24 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |
25 | * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE | |
26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | |
27 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | |
28 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR | |
29 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, | |
30 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE | |
31 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN | |
32 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
33 | */ | |
34 | ||
35 | #include <linux/init.h> | |
36 | #include <linux/kernel.h> | |
37 | #include <linux/threads.h> | |
38 | ||
39 | #include <asm/asm.h> | |
40 | #include <asm/asm-offsets.h> | |
41 | #include <asm/mipsregs.h> | |
42 | #include <asm/addrspace.h> | |
43 | #include <asm/string.h> | |
44 | ||
45 | #include <asm/netlogic/haldefs.h> | |
46 | #include <asm/netlogic/common.h> | |
47 | #include <asm/netlogic/mips-extns.h> | |
48 | ||
49 | #include <asm/netlogic/xlp-hal/iomap.h> | |
50 | #include <asm/netlogic/xlp-hal/pic.h> | |
51 | #include <asm/netlogic/xlp-hal/xlp.h> | |
52 | #include <asm/netlogic/xlp-hal/sys.h> | |
53 | ||
66d29985 | 54 | static void xlp_enable_secondary_cores(void) |
65040e22 | 55 | { |
66d29985 J |
56 | uint32_t core, value, coremask, syscoremask; |
57 | int count; | |
58 | ||
59 | /* read cores in reset from SYS block */ | |
60 | syscoremask = nlm_read_sys_reg(nlm_sys_base, SYS_CPU_RESET); | |
61 | ||
62 | /* update user specified */ | |
63 | nlm_coremask = nlm_coremask & (syscoremask | 1); | |
65040e22 J |
64 | |
65 | for (core = 1; core < 8; core++) { | |
66 | coremask = 1 << core; | |
66d29985 | 67 | if ((nlm_coremask & coremask) == 0) |
65040e22 J |
68 | continue; |
69 | ||
70 | /* Enable CPU clock */ | |
71 | value = nlm_read_sys_reg(nlm_sys_base, SYS_CORE_DFS_DIS_CTRL); | |
72 | value &= ~coremask; | |
73 | nlm_write_sys_reg(nlm_sys_base, SYS_CORE_DFS_DIS_CTRL, value); | |
74 | ||
75 | /* Remove CPU Reset */ | |
76 | value = nlm_read_sys_reg(nlm_sys_base, SYS_CPU_RESET); | |
77 | value &= ~coremask; | |
78 | nlm_write_sys_reg(nlm_sys_base, SYS_CPU_RESET, value); | |
79 | ||
80 | /* Poll for CPU to mark itself coherent */ | |
66d29985 | 81 | count = 100000; |
65040e22 J |
82 | do { |
83 | value = nlm_read_sys_reg(nlm_sys_base, | |
84 | SYS_CPU_NONCOHERENT_MODE); | |
66d29985 | 85 | } while ((value & coremask) != 0 && count-- > 0); |
65040e22 | 86 | |
66d29985 J |
87 | if (count == 0) |
88 | pr_err("Failed to enable core %d\n", core); | |
65040e22 | 89 | } |
65040e22 J |
90 | } |
91 | ||
66d29985 | 92 | void xlp_wakeup_secondary_cpus(void) |
65040e22 | 93 | { |
66d29985 J |
94 | /* |
95 | * In case of u-boot, the secondaries are in reset | |
96 | * first wakeup core 0 threads | |
97 | */ | |
98 | xlp_boot_core0_siblings(); | |
99 | ||
100 | /* now get other cores out of reset */ | |
101 | xlp_enable_secondary_cores(); | |
65040e22 | 102 | } |