[deliverable/linux.git] / arch / mips / oprofile / op_model_mipsxx.c

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 2004, 05, 06 by Ralf Baechle
 * Copyright (C) 2005 by MIPS Technologies, Inc.
 */
#include <linux/cpumask.h>
#include <linux/oprofile.h>
#include <linux/interrupt.h>
#include <linux/smp.h>
#include <asm/irq_regs.h>

#include "op_impl.h"

#define M_PERFCTL_EXL			(1UL      <<  0)
#define M_PERFCTL_KERNEL		(1UL      <<  1)
#define M_PERFCTL_SUPERVISOR		(1UL      <<  2)
#define M_PERFCTL_USER			(1UL      <<  3)
#define M_PERFCTL_INTERRUPT_ENABLE	(1UL      <<  4)
#define M_PERFCTL_EVENT(event)		(((event) & 0x3ff)  << 5)
#define M_PERFCTL_VPEID(vpe)		((vpe)    << 16)
#define M_PERFCTL_MT_EN(filter)		((filter) << 20)
#define    M_TC_EN_ALL			M_PERFCTL_MT_EN(0)
#define    M_TC_EN_VPE			M_PERFCTL_MT_EN(1)
#define    M_TC_EN_TC			M_PERFCTL_MT_EN(2)
#define M_PERFCTL_TCID(tcid)		((tcid)   << 22)
#define M_PERFCTL_WIDE			(1UL      << 30)
#define M_PERFCTL_MORE			(1UL      << 31)

#define M_COUNTER_OVERFLOW		(1UL      << 31)

static int (*save_perf_irq)(void);

#ifdef CONFIG_MIPS_MT_SMP
static int cpu_has_mipsmt_pertccounters;
#define WHAT		(M_TC_EN_VPE | \
			 M_PERFCTL_VPEID(cpu_data[smp_processor_id()].vpe_id))
#define vpe_id()	(cpu_has_mipsmt_pertccounters ? \
			0 : cpu_data[smp_processor_id()].vpe_id)

/*
 * The number of bits to shift to convert between counters per core and
 * counters per VPE.  There is no reasonable interface atm to obtain the
 * number of VPEs used by Linux and in the 34K this number is fixed to two
 * anyways so we hardcore a few things here for the moment.  The way it's
 * done here will ensure that oprofile VSMP kernel will run right on a lesser
 * core like a 24K also or with maxcpus=1.
 */
static inline unsigned int vpe_shift(void)
{
	if (num_possible_cpus() > 1)
		return 1;

	return 0;
}

#else

#define WHAT		0
#define vpe_id()	0

static inline unsigned int vpe_shift(void)
{
	return 0;
}

#endif

static inline unsigned int counters_total_to_per_cpu(unsigned int counters)
{
	return counters >> vpe_shift();
}

static inline unsigned int counters_per_cpu_to_total(unsigned int counters)
{
	return counters << vpe_shift();
}

#define __define_perf_accessors(r, n, np)				\
									\
static inline unsigned int r_c0_ ## r ## n(void)			\
{									\
	unsigned int cpu = vpe_id();					\
									\
	switch (cpu) {							\
	case 0:								\
		return read_c0_ ## r ## n();				\
	case 1:								\
		return read_c0_ ## r ## np();				\
	default:							\
		BUG();							\
	}								\
	return 0;							\
}									\
									\
static inline void w_c0_ ## r ## n(unsigned int value)			\
{									\
	unsigned int cpu = vpe_id();					\
									\
	switch (cpu) {							\
	case 0:								\
		write_c0_ ## r ## n(value);				\
		return;							\
	case 1:								\
		write_c0_ ## r ## np(value);				\
		return;							\
	default:							\
		BUG();							\
	}								\
	return;								\
}									\

__define_perf_accessors(perfcntr, 0, 2)
__define_perf_accessors(perfcntr, 1, 3)
__define_perf_accessors(perfcntr, 2, 0)
__define_perf_accessors(perfcntr, 3, 1)

__define_perf_accessors(perfctrl, 0, 2)
__define_perf_accessors(perfctrl, 1, 3)
__define_perf_accessors(perfctrl, 2, 0)
__define_perf_accessors(perfctrl, 3, 1)

struct op_mips_model op_model_mipsxx_ops;

static struct mipsxx_register_config {
	unsigned int control[4];
	unsigned int counter[4];
} reg;

/* Compute all of the registers in preparation for enabling profiling.  */

static void mipsxx_reg_setup(struct op_counter_config *ctr)
{
	unsigned int counters = op_model_mipsxx_ops.num_counters;
	int i;

	/* Compute the performance counter control word.  */
	for (i = 0; i < counters; i++) {
		reg.control[i] = 0;
		reg.counter[i] = 0;

		if (!ctr[i].enabled)
			continue;

		reg.control[i] = M_PERFCTL_EVENT(ctr[i].event) |
		                 M_PERFCTL_INTERRUPT_ENABLE;
		if (ctr[i].kernel)
			reg.control[i] |= M_PERFCTL_KERNEL;
		if (ctr[i].user)
			reg.control[i] |= M_PERFCTL_USER;
		if (ctr[i].exl)
			reg.control[i] |= M_PERFCTL_EXL;
		reg.counter[i] = 0x80000000 - ctr[i].count;
	}
}

/* Program all of the registers in preparation for enabling profiling.  */

static void mipsxx_cpu_setup(void *args)
{
	unsigned int counters = op_model_mipsxx_ops.num_counters;

	switch (counters) {
	case 4:
		w_c0_perfctrl3(0);
		w_c0_perfcntr3(reg.counter[3]);
	case 3:
		w_c0_perfctrl2(0);
		w_c0_perfcntr2(reg.counter[2]);
	case 2:
		w_c0_perfctrl1(0);
		w_c0_perfcntr1(reg.counter[1]);
	case 1:
		w_c0_perfctrl0(0);
		w_c0_perfcntr0(reg.counter[0]);
	}
}

/* Start all counters on current CPU */
static void mipsxx_cpu_start(void *args)
{
	unsigned int counters = op_model_mipsxx_ops.num_counters;

	switch (counters) {
	case 4:
		w_c0_perfctrl3(WHAT | reg.control[3]);
	case 3:
		w_c0_perfctrl2(WHAT | reg.control[2]);
	case 2:
		w_c0_perfctrl1(WHAT | reg.control[1]);
	case 1:
		w_c0_perfctrl0(WHAT | reg.control[0]);
	}
}

/* Stop all counters on current CPU */
static void mipsxx_cpu_stop(void *args)
{
	unsigned int counters = op_model_mipsxx_ops.num_counters;

	switch (counters) {
	case 4:
		w_c0_perfctrl3(0);
	case 3:
		w_c0_perfctrl2(0);
	case 2:
		w_c0_perfctrl1(0);
	case 1:
		w_c0_perfctrl0(0);
	}
}

static int mipsxx_perfcount_handler(void)
{
	unsigned int counters = op_model_mipsxx_ops.num_counters;
	unsigned int control;
	unsigned int counter;
	int handled = IRQ_NONE;

	if (cpu_has_mips_r2 && !(read_c0_cause() & (1 << 26)))
		return handled;

	switch (counters) {
#define HANDLE_COUNTER(n)						\
	case n + 1:							\
		control = r_c0_perfctrl ## n();				\
		counter = r_c0_perfcntr ## n();				\
		if ((control & M_PERFCTL_INTERRUPT_ENABLE) &&		\
		    (counter & M_COUNTER_OVERFLOW)) {			\
			oprofile_add_sample(get_irq_regs(), n);		\
			w_c0_perfcntr ## n(reg.counter[n]);		\
			handled = IRQ_HANDLED;				\
		}
	HANDLE_COUNTER(3)
	HANDLE_COUNTER(2)
	HANDLE_COUNTER(1)
	HANDLE_COUNTER(0)
	}

	return handled;
}

#define M_CONFIG1_PC	(1 << 4)

static inline int __n_counters(void)
{
	if (!(read_c0_config1() & M_CONFIG1_PC))
		return 0;
	if (!(read_c0_perfctrl0() & M_PERFCTL_MORE))
		return 1;
	if (!(read_c0_perfctrl1() & M_PERFCTL_MORE))
		return 2;
	if (!(read_c0_perfctrl2() & M_PERFCTL_MORE))
		return 3;

	return 4;
}

static inline int n_counters(void)
{
	int counters;

	switch (current_cpu_type()) {
	case CPU_R10000:
		counters = 2;
		break;

	case CPU_R12000:
	case CPU_R14000:
		counters = 4;
		break;

	default:
		counters = __n_counters();
	}

	return counters;
}

static void reset_counters(void *arg)
{
	int counters = (int)(long)arg;
	switch (counters) {
	case 4:
		w_c0_perfctrl3(0);
		w_c0_perfcntr3(0);
	case 3:
		w_c0_perfctrl2(0);
		w_c0_perfcntr2(0);
	case 2:
		w_c0_perfctrl1(0);
		w_c0_perfcntr1(0);
	case 1:
		w_c0_perfctrl0(0);
		w_c0_perfcntr0(0);
	}
}

static irqreturn_t mipsxx_perfcount_int(int irq, void *dev_id)
{
	return mipsxx_perfcount_handler();
}

static int __init mipsxx_init(void)
{
	int counters;

	counters = n_counters();
	if (counters == 0) {
		printk(KERN_ERR "Oprofile: CPU has no performance counters\n");
		return -ENODEV;
	}

#ifdef CONFIG_MIPS_MT_SMP
	cpu_has_mipsmt_pertccounters = read_c0_config7() & (1<<19);
	if (!cpu_has_mipsmt_pertccounters)
		counters = counters_total_to_per_cpu(counters);
#endif
	on_each_cpu(reset_counters, (void *)(long)counters, 1);

	op_model_mipsxx_ops.num_counters = counters;
	switch (current_cpu_type()) {
	case CPU_M14KC:
		op_model_mipsxx_ops.cpu_type = "mips/M14Kc";
		break;

	case CPU_20KC:
		op_model_mipsxx_ops.cpu_type = "mips/20K";
		break;

	case CPU_24K:
		op_model_mipsxx_ops.cpu_type = "mips/24K";
		break;

	case CPU_25KF:
		op_model_mipsxx_ops.cpu_type = "mips/25K";
		break;

	case CPU_1004K:
#if 0
		/* FIXME: report as 34K for now */
		op_model_mipsxx_ops.cpu_type = "mips/1004K";
		break;
#endif

	case CPU_34K:
		op_model_mipsxx_ops.cpu_type = "mips/34K";
		break;

	case CPU_74K:
		op_model_mipsxx_ops.cpu_type = "mips/74K";
		break;

	case CPU_5KC:
		op_model_mipsxx_ops.cpu_type = "mips/5K";
		break;

	case CPU_R10000:
		if ((current_cpu_data.processor_id & 0xff) == 0x20)
			op_model_mipsxx_ops.cpu_type = "mips/r10000-v2.x";
		else
			op_model_mipsxx_ops.cpu_type = "mips/r10000";
		break;

	case CPU_R12000:
	case CPU_R14000:
		op_model_mipsxx_ops.cpu_type = "mips/r12000";
		break;

	case CPU_SB1:
	case CPU_SB1A:
		op_model_mipsxx_ops.cpu_type = "mips/sb1";
		break;

	default:
		printk(KERN_ERR "Profiling unsupported for this CPU\n");

		return -ENODEV;
	}

	save_perf_irq = perf_irq;
	perf_irq = mipsxx_perfcount_handler;

	if ((cp0_perfcount_irq >= 0) && (cp0_compare_irq != cp0_perfcount_irq))
		return request_irq(cp0_perfcount_irq, mipsxx_perfcount_int,
			0, "Perfcounter", save_perf_irq);

	return 0;
}

static void mipsxx_exit(void)
{
	int counters = op_model_mipsxx_ops.num_counters;

	if ((cp0_perfcount_irq >= 0) && (cp0_compare_irq != cp0_perfcount_irq))
		free_irq(cp0_perfcount_irq, save_perf_irq);

	counters = counters_per_cpu_to_total(counters);
	on_each_cpu(reset_counters, (void *)(long)counters, 1);

	perf_irq = save_perf_irq;
}

struct op_mips_model op_model_mipsxx_ops = {
	.reg_setup	= mipsxx_reg_setup,
	.cpu_setup	= mipsxx_cpu_setup,
	.init		= mipsxx_init,
	.exit		= mipsxx_exit,
	.cpu_start	= mipsxx_cpu_start,
	.cpu_stop	= mipsxx_cpu_stop,
};
Commit	Line	Data
54176736 RB	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
937a8015	6	* Copyright (C) 2004, 05, 06 by Ralf Baechle
54176736 RB	7	* Copyright (C) 2005 by MIPS Technologies, Inc.
54176736 RB	8	*/
5e2862eb	9	#include <linux/cpumask.h>
54176736 RB	10	#include <linux/oprofile.h>
	11	#include <linux/interrupt.h>
	12	#include <linux/smp.h>
937a8015	13	#include <asm/irq_regs.h>
54176736 RB	14
	15	#include "op_impl.h"
	16
92c7b62f RB	17	#define M_PERFCTL_EXL (1UL << 0)
	18	#define M_PERFCTL_KERNEL (1UL << 1)
	19	#define M_PERFCTL_SUPERVISOR (1UL << 2)
	20	#define M_PERFCTL_USER (1UL << 3)
	21	#define M_PERFCTL_INTERRUPT_ENABLE (1UL << 4)
39a51109	22	#define M_PERFCTL_EVENT(event) (((event) & 0x3ff) << 5)
92c7b62f RB	23	#define M_PERFCTL_VPEID(vpe) ((vpe) << 16)
	24	#define M_PERFCTL_MT_EN(filter) ((filter) << 20)
	25	#define M_TC_EN_ALL M_PERFCTL_MT_EN(0)
	26	#define M_TC_EN_VPE M_PERFCTL_MT_EN(1)
	27	#define M_TC_EN_TC M_PERFCTL_MT_EN(2)
	28	#define M_PERFCTL_TCID(tcid) ((tcid) << 22)
	29	#define M_PERFCTL_WIDE (1UL << 30)
	30	#define M_PERFCTL_MORE (1UL << 31)
	31
	32	#define M_COUNTER_OVERFLOW (1UL << 31)
	33
46684734 DV	34	static int (*save_perf_irq)(void);
46684734 DV	35
92c7b62f	36	#ifdef CONFIG_MIPS_MT_SMP
39b8d525 RB	37	static int cpu_has_mipsmt_pertccounters;
	38	#define WHAT (M_TC_EN_VPE \| \
	39	M_PERFCTL_VPEID(cpu_data[smp_processor_id()].vpe_id))
	40	#define vpe_id() (cpu_has_mipsmt_pertccounters ? \
	41	0 : cpu_data[smp_processor_id()].vpe_id)
5e2862eb RB	42
	43	/*
	44	* The number of bits to shift to convert between counters per core and
	45	* counters per VPE. There is no reasonable interface atm to obtain the
	46	* number of VPEs used by Linux and in the 34K this number is fixed to two
	47	* anyways so we hardcore a few things here for the moment. The way it's
	48	* done here will ensure that oprofile VSMP kernel will run right on a lesser
	49	* core like a 24K also or with maxcpus=1.
	50	*/
	51	static inline unsigned int vpe_shift(void)
	52	{
	53	if (num_possible_cpus() > 1)
	54	return 1;
	55
	56	return 0;
	57	}
	58
92c7b62f	59	#else
5e2862eb	60
be609f35	61	#define WHAT 0
6f4c5bde	62	#define vpe_id() 0
5e2862eb RB	63
	64	static inline unsigned int vpe_shift(void)
	65	{
	66	return 0;
	67	}
	68
92c7b62f	69	#endif
54176736	70
5e2862eb RB	71	static inline unsigned int counters_total_to_per_cpu(unsigned int counters)
	72	{
	73	return counters >> vpe_shift();
	74	}
	75
	76	static inline unsigned int counters_per_cpu_to_total(unsigned int counters)
	77	{
	78	return counters << vpe_shift();
	79	}
	80
92c7b62f RB	81	#define __define_perf_accessors(r, n, np) \
	82	\
	83	static inline unsigned int r_c0_ ## r ## n(void) \
	84	{ \
be609f35	85	unsigned int cpu = vpe_id(); \
92c7b62f RB	86	\
	87	switch (cpu) { \
	88	case 0: \
	89	return read_c0_ ## r ## n(); \
	90	case 1: \
	91	return read_c0_ ## r ## np(); \
	92	default: \
	93	BUG(); \
	94	} \
30f244ae	95	return 0; \
92c7b62f RB	96	} \
	97	\
	98	static inline void w_c0_ ## r ## n(unsigned int value) \
	99	{ \
be609f35	100	unsigned int cpu = vpe_id(); \
92c7b62f RB	101	\
	102	switch (cpu) { \
	103	case 0: \
	104	write_c0_ ## r ## n(value); \
	105	return; \
	106	case 1: \
	107	write_c0_ ## r ## np(value); \
	108	return; \
	109	default: \
	110	BUG(); \
	111	} \
30f244ae	112	return; \
92c7b62f RB	113	} \
	114
	115	__define_perf_accessors(perfcntr, 0, 2)
	116	__define_perf_accessors(perfcntr, 1, 3)
795a2258 CD	117	__define_perf_accessors(perfcntr, 2, 0)
795a2258 CD	118	__define_perf_accessors(perfcntr, 3, 1)
92c7b62f RB	119
	120	__define_perf_accessors(perfctrl, 0, 2)
	121	__define_perf_accessors(perfctrl, 1, 3)
795a2258 CD	122	__define_perf_accessors(perfctrl, 2, 0)
795a2258 CD	123	__define_perf_accessors(perfctrl, 3, 1)
54176736	124
1acf1ca7	125	struct op_mips_model op_model_mipsxx_ops;
54176736 RB	126
	127	static struct mipsxx_register_config {
	128	unsigned int control[4];
	129	unsigned int counter[4];
	130	} reg;
	131
	132	/* Compute all of the registers in preparation for enabling profiling. */
	133
	134	static void mipsxx_reg_setup(struct op_counter_config *ctr)
	135	{
1acf1ca7	136	unsigned int counters = op_model_mipsxx_ops.num_counters;
54176736 RB	137	int i;
	138
	139	/* Compute the performance counter control word. */
54176736 RB	140	for (i = 0; i < counters; i++) {
	141	reg.control[i] = 0;
	142	reg.counter[i] = 0;
	143
	144	if (!ctr[i].enabled)
	145	continue;
	146
	147	reg.control[i] = M_PERFCTL_EVENT(ctr[i].event) \|
	148	M_PERFCTL_INTERRUPT_ENABLE;
	149	if (ctr[i].kernel)
	150	reg.control[i] \|= M_PERFCTL_KERNEL;
	151	if (ctr[i].user)
	152	reg.control[i] \|= M_PERFCTL_USER;
	153	if (ctr[i].exl)
	154	reg.control[i] \|= M_PERFCTL_EXL;
	155	reg.counter[i] = 0x80000000 - ctr[i].count;
	156	}
	157	}
	158
	159	/* Program all of the registers in preparation for enabling profiling. */
	160
49a89efb	161	static void mipsxx_cpu_setup(void *args)
54176736	162	{
1acf1ca7	163	unsigned int counters = op_model_mipsxx_ops.num_counters;
54176736 RB	164
	165	switch (counters) {
	166	case 4:
92c7b62f RB	167	w_c0_perfctrl3(0);
92c7b62f RB	168	w_c0_perfcntr3(reg.counter[3]);
54176736	169	case 3:
92c7b62f RB	170	w_c0_perfctrl2(0);
92c7b62f RB	171	w_c0_perfcntr2(reg.counter[2]);
54176736	172	case 2:
92c7b62f RB	173	w_c0_perfctrl1(0);
92c7b62f RB	174	w_c0_perfcntr1(reg.counter[1]);
54176736	175	case 1:
92c7b62f RB	176	w_c0_perfctrl0(0);
92c7b62f RB	177	w_c0_perfcntr0(reg.counter[0]);
54176736 RB	178	}
	179	}
	180
	181	/* Start all counters on current CPU */
	182	static void mipsxx_cpu_start(void *args)
	183	{
1acf1ca7	184	unsigned int counters = op_model_mipsxx_ops.num_counters;
54176736 RB	185
	186	switch (counters) {
	187	case 4:
92c7b62f	188	w_c0_perfctrl3(WHAT \| reg.control[3]);
54176736	189	case 3:
92c7b62f	190	w_c0_perfctrl2(WHAT \| reg.control[2]);
54176736	191	case 2:
92c7b62f	192	w_c0_perfctrl1(WHAT \| reg.control[1]);
54176736	193	case 1:
92c7b62f	194	w_c0_perfctrl0(WHAT \| reg.control[0]);
54176736 RB	195	}
	196	}
	197
	198	/* Stop all counters on current CPU */
	199	static void mipsxx_cpu_stop(void *args)
	200	{
1acf1ca7	201	unsigned int counters = op_model_mipsxx_ops.num_counters;
54176736 RB	202
	203	switch (counters) {
	204	case 4:
92c7b62f	205	w_c0_perfctrl3(0);
54176736	206	case 3:
92c7b62f	207	w_c0_perfctrl2(0);
54176736	208	case 2:
92c7b62f	209	w_c0_perfctrl1(0);
54176736	210	case 1:
92c7b62f	211	w_c0_perfctrl0(0);
54176736 RB	212	}
	213	}
	214
937a8015	215	static int mipsxx_perfcount_handler(void)
54176736	216	{
1acf1ca7	217	unsigned int counters = op_model_mipsxx_ops.num_counters;
54176736 RB	218	unsigned int control;
54176736 RB	219	unsigned int counter;
ffe9ee47 CD	220	int handled = IRQ_NONE;
	221
	222	if (cpu_has_mips_r2 && !(read_c0_cause() & (1 << 26)))
	223	return handled;
54176736 RB	224
	225	switch (counters) {
	226	#define HANDLE_COUNTER(n) \
	227	case n + 1: \
92c7b62f RB	228	control = r_c0_perfctrl ## n(); \
92c7b62f RB	229	counter = r_c0_perfcntr ## n(); \
54176736 RB	230	if ((control & M_PERFCTL_INTERRUPT_ENABLE) && \
54176736 RB	231	(counter & M_COUNTER_OVERFLOW)) { \
937a8015	232	oprofile_add_sample(get_irq_regs(), n); \
92c7b62f	233	w_c0_perfcntr ## n(reg.counter[n]); \
ffe9ee47	234	handled = IRQ_HANDLED; \
54176736 RB	235	}
	236	HANDLE_COUNTER(3)
	237	HANDLE_COUNTER(2)
	238	HANDLE_COUNTER(1)
	239	HANDLE_COUNTER(0)
	240	}
ba339c03 RB	241
ba339c03 RB	242	return handled;
54176736 RB	243	}
	244
	245	#define M_CONFIG1_PC (1 << 4)
	246
92c7b62f	247	static inline int __n_counters(void)
54176736 RB	248	{
	249	if (!(read_c0_config1() & M_CONFIG1_PC))
	250	return 0;
39b8d525	251	if (!(read_c0_perfctrl0() & M_PERFCTL_MORE))
54176736	252	return 1;
39b8d525	253	if (!(read_c0_perfctrl1() & M_PERFCTL_MORE))
54176736	254	return 2;
39b8d525	255	if (!(read_c0_perfctrl2() & M_PERFCTL_MORE))
54176736 RB	256	return 3;
	257
	258	return 4;
	259	}
	260
92c7b62f RB	261	static inline int n_counters(void)
92c7b62f RB	262	{
714cfe78 RB	263	int counters;
714cfe78 RB	264
10cc3529	265	switch (current_cpu_type()) {
714cfe78 RB	266	case CPU_R10000:
714cfe78 RB	267	counters = 2;
148171b2	268	break;
714cfe78 RB	269
	270	case CPU_R12000:
	271	case CPU_R14000:
	272	counters = 4;
148171b2	273	break;
714cfe78 RB	274
	275	default:
	276	counters = __n_counters();
	277	}
92c7b62f	278
92c7b62f RB	279	return counters;
	280	}
	281
39b8d525	282	static void reset_counters(void *arg)
54176736	283	{
005ca9a3	284	int counters = (int)(long)arg;
54176736 RB	285	switch (counters) {
54176736 RB	286	case 4:
92c7b62f RB	287	w_c0_perfctrl3(0);
92c7b62f RB	288	w_c0_perfcntr3(0);
54176736	289	case 3:
92c7b62f RB	290	w_c0_perfctrl2(0);
92c7b62f RB	291	w_c0_perfcntr2(0);
54176736	292	case 2:
92c7b62f RB	293	w_c0_perfctrl1(0);
92c7b62f RB	294	w_c0_perfcntr1(0);
54176736	295	case 1:
92c7b62f RB	296	w_c0_perfctrl0(0);
92c7b62f RB	297	w_c0_perfcntr0(0);
54176736 RB	298	}
	299	}
	300
3572a2c3 FF	301	static irqreturn_t mipsxx_perfcount_int(int irq, void *dev_id)
	302	{
	303	return mipsxx_perfcount_handler();
	304	}
	305
54176736 RB	306	static int __init mipsxx_init(void)
	307	{
	308	int counters;
	309
	310	counters = n_counters();
9efeae9a RB	311	if (counters == 0) {
9efeae9a RB	312	printk(KERN_ERR "Oprofile: CPU has no performance counters\n");
54176736	313	return -ENODEV;
9efeae9a	314	}
54176736	315
39b8d525 RB	316	#ifdef CONFIG_MIPS_MT_SMP
	317	cpu_has_mipsmt_pertccounters = read_c0_config7() & (1<<19);
	318	if (!cpu_has_mipsmt_pertccounters)
	319	counters = counters_total_to_per_cpu(counters);
	320	#endif
f6f88e9b	321	on_each_cpu(reset_counters, (void *)(long)counters, 1);
795a2258	322
1acf1ca7	323	op_model_mipsxx_ops.num_counters = counters;
10cc3529	324	switch (current_cpu_type()) {
113c62d9 SH	325	case CPU_M14KC:
	326	op_model_mipsxx_ops.cpu_type = "mips/M14Kc";
	327	break;
	328
2065988e	329	case CPU_20KC:
1acf1ca7	330	op_model_mipsxx_ops.cpu_type = "mips/20K";
2065988e RB	331	break;
2065988e RB	332
54176736	333	case CPU_24K:
1acf1ca7	334	op_model_mipsxx_ops.cpu_type = "mips/24K";
54176736 RB	335	break;
54176736 RB	336
2065988e	337	case CPU_25KF:
1acf1ca7	338	op_model_mipsxx_ops.cpu_type = "mips/25K";
2065988e RB	339	break;
2065988e RB	340
39b8d525 RB	341	case CPU_1004K:
	342	#if 0
	343	/* FIXME: report as 34K for now */
	344	op_model_mipsxx_ops.cpu_type = "mips/1004K";
	345	break;
	346	#endif
	347
fcfd980c	348	case CPU_34K:
1acf1ca7	349	op_model_mipsxx_ops.cpu_type = "mips/34K";
fcfd980c	350	break;
c620953c CD	351
c620953c CD	352	case CPU_74K:
1acf1ca7	353	op_model_mipsxx_ops.cpu_type = "mips/74K";
c620953c	354	break;
fcfd980c	355
2065988e	356	case CPU_5KC:
1acf1ca7	357	op_model_mipsxx_ops.cpu_type = "mips/5K";
2065988e RB	358	break;
2065988e RB	359
714cfe78 RB	360	case CPU_R10000:
	361	if ((current_cpu_data.processor_id & 0xff) == 0x20)
	362	op_model_mipsxx_ops.cpu_type = "mips/r10000-v2.x";
	363	else
	364	op_model_mipsxx_ops.cpu_type = "mips/r10000";
	365	break;
	366
	367	case CPU_R12000:
	368	case CPU_R14000:
	369	op_model_mipsxx_ops.cpu_type = "mips/r12000";
	370	break;
	371
c03bc121 MM	372	case CPU_SB1:
c03bc121 MM	373	case CPU_SB1A:
1acf1ca7	374	op_model_mipsxx_ops.cpu_type = "mips/sb1";
c03bc121 MM	375	break;
c03bc121 MM	376
54176736 RB	377	default:
	378	printk(KERN_ERR "Profiling unsupported for this CPU\n");
	379
	380	return -ENODEV;
	381	}
	382
46684734	383	save_perf_irq = perf_irq;
54176736 RB	384	perf_irq = mipsxx_perfcount_handler;
54176736 RB	385
3572a2c3 FF	386	if ((cp0_perfcount_irq >= 0) && (cp0_compare_irq != cp0_perfcount_irq))
	387	return request_irq(cp0_perfcount_irq, mipsxx_perfcount_int,
	388	0, "Perfcounter", save_perf_irq);
	389
54176736 RB	390	return 0;
	391	}
	392
	393	static void mipsxx_exit(void)
	394	{
795a2258	395	int counters = op_model_mipsxx_ops.num_counters;
5e2862eb	396
3572a2c3 FF	397	if ((cp0_perfcount_irq >= 0) && (cp0_compare_irq != cp0_perfcount_irq))
	398	free_irq(cp0_perfcount_irq, save_perf_irq);
	399
5e2862eb	400	counters = counters_per_cpu_to_total(counters);
f6f88e9b	401	on_each_cpu(reset_counters, (void *)(long)counters, 1);
54176736	402
46684734	403	perf_irq = save_perf_irq;
54176736 RB	404	}
54176736 RB	405
1acf1ca7	406	struct op_mips_model op_model_mipsxx_ops = {
54176736 RB	407	.reg_setup = mipsxx_reg_setup,
	408	.cpu_setup = mipsxx_cpu_setup,
	409	.init = mipsxx_init,
	410	.exit = mipsxx_exit,
	411	.cpu_start = mipsxx_cpu_start,
	412	.cpu_stop = mipsxx_cpu_stop,
	413	};