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54176736 RB |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
937a8015 | 6 | * Copyright (C) 2004, 05, 06 by Ralf Baechle |
54176736 RB |
7 | * Copyright (C) 2005 by MIPS Technologies, Inc. |
8 | */ | |
9 | #include <linux/oprofile.h> | |
10 | #include <linux/interrupt.h> | |
11 | #include <linux/smp.h> | |
937a8015 | 12 | #include <asm/irq_regs.h> |
54176736 RB |
13 | |
14 | #include "op_impl.h" | |
15 | ||
92c7b62f RB |
16 | #define M_PERFCTL_EXL (1UL << 0) |
17 | #define M_PERFCTL_KERNEL (1UL << 1) | |
18 | #define M_PERFCTL_SUPERVISOR (1UL << 2) | |
19 | #define M_PERFCTL_USER (1UL << 3) | |
20 | #define M_PERFCTL_INTERRUPT_ENABLE (1UL << 4) | |
714cfe78 | 21 | #define M_PERFCTL_EVENT(event) (((event) & 0x3f) << 5) |
92c7b62f RB |
22 | #define M_PERFCTL_VPEID(vpe) ((vpe) << 16) |
23 | #define M_PERFCTL_MT_EN(filter) ((filter) << 20) | |
24 | #define M_TC_EN_ALL M_PERFCTL_MT_EN(0) | |
25 | #define M_TC_EN_VPE M_PERFCTL_MT_EN(1) | |
26 | #define M_TC_EN_TC M_PERFCTL_MT_EN(2) | |
27 | #define M_PERFCTL_TCID(tcid) ((tcid) << 22) | |
28 | #define M_PERFCTL_WIDE (1UL << 30) | |
29 | #define M_PERFCTL_MORE (1UL << 31) | |
30 | ||
31 | #define M_COUNTER_OVERFLOW (1UL << 31) | |
32 | ||
33 | #ifdef CONFIG_MIPS_MT_SMP | |
be609f35 RB |
34 | #define WHAT (M_TC_EN_VPE | M_PERFCTL_VPEID(smp_processor_id())) |
35 | #define vpe_id() smp_processor_id() | |
92c7b62f | 36 | #else |
be609f35 RB |
37 | #define WHAT 0 |
38 | #define vpe_id() smp_processor_id() | |
92c7b62f | 39 | #endif |
54176736 | 40 | |
92c7b62f RB |
41 | #define __define_perf_accessors(r, n, np) \ |
42 | \ | |
43 | static inline unsigned int r_c0_ ## r ## n(void) \ | |
44 | { \ | |
be609f35 | 45 | unsigned int cpu = vpe_id(); \ |
92c7b62f RB |
46 | \ |
47 | switch (cpu) { \ | |
48 | case 0: \ | |
49 | return read_c0_ ## r ## n(); \ | |
50 | case 1: \ | |
51 | return read_c0_ ## r ## np(); \ | |
52 | default: \ | |
53 | BUG(); \ | |
54 | } \ | |
30f244ae | 55 | return 0; \ |
92c7b62f RB |
56 | } \ |
57 | \ | |
58 | static inline void w_c0_ ## r ## n(unsigned int value) \ | |
59 | { \ | |
be609f35 | 60 | unsigned int cpu = vpe_id(); \ |
92c7b62f RB |
61 | \ |
62 | switch (cpu) { \ | |
63 | case 0: \ | |
64 | write_c0_ ## r ## n(value); \ | |
65 | return; \ | |
66 | case 1: \ | |
67 | write_c0_ ## r ## np(value); \ | |
68 | return; \ | |
69 | default: \ | |
70 | BUG(); \ | |
71 | } \ | |
30f244ae | 72 | return; \ |
92c7b62f RB |
73 | } \ |
74 | ||
75 | __define_perf_accessors(perfcntr, 0, 2) | |
76 | __define_perf_accessors(perfcntr, 1, 3) | |
795a2258 CD |
77 | __define_perf_accessors(perfcntr, 2, 0) |
78 | __define_perf_accessors(perfcntr, 3, 1) | |
92c7b62f RB |
79 | |
80 | __define_perf_accessors(perfctrl, 0, 2) | |
81 | __define_perf_accessors(perfctrl, 1, 3) | |
795a2258 CD |
82 | __define_perf_accessors(perfctrl, 2, 0) |
83 | __define_perf_accessors(perfctrl, 3, 1) | |
54176736 | 84 | |
1acf1ca7 | 85 | struct op_mips_model op_model_mipsxx_ops; |
54176736 RB |
86 | |
87 | static struct mipsxx_register_config { | |
88 | unsigned int control[4]; | |
89 | unsigned int counter[4]; | |
90 | } reg; | |
91 | ||
92 | /* Compute all of the registers in preparation for enabling profiling. */ | |
93 | ||
94 | static void mipsxx_reg_setup(struct op_counter_config *ctr) | |
95 | { | |
1acf1ca7 | 96 | unsigned int counters = op_model_mipsxx_ops.num_counters; |
54176736 RB |
97 | int i; |
98 | ||
99 | /* Compute the performance counter control word. */ | |
54176736 RB |
100 | for (i = 0; i < counters; i++) { |
101 | reg.control[i] = 0; | |
102 | reg.counter[i] = 0; | |
103 | ||
104 | if (!ctr[i].enabled) | |
105 | continue; | |
106 | ||
107 | reg.control[i] = M_PERFCTL_EVENT(ctr[i].event) | | |
108 | M_PERFCTL_INTERRUPT_ENABLE; | |
109 | if (ctr[i].kernel) | |
110 | reg.control[i] |= M_PERFCTL_KERNEL; | |
111 | if (ctr[i].user) | |
112 | reg.control[i] |= M_PERFCTL_USER; | |
113 | if (ctr[i].exl) | |
114 | reg.control[i] |= M_PERFCTL_EXL; | |
115 | reg.counter[i] = 0x80000000 - ctr[i].count; | |
116 | } | |
117 | } | |
118 | ||
119 | /* Program all of the registers in preparation for enabling profiling. */ | |
120 | ||
121 | static void mipsxx_cpu_setup (void *args) | |
122 | { | |
1acf1ca7 | 123 | unsigned int counters = op_model_mipsxx_ops.num_counters; |
54176736 RB |
124 | |
125 | switch (counters) { | |
126 | case 4: | |
92c7b62f RB |
127 | w_c0_perfctrl3(0); |
128 | w_c0_perfcntr3(reg.counter[3]); | |
54176736 | 129 | case 3: |
92c7b62f RB |
130 | w_c0_perfctrl2(0); |
131 | w_c0_perfcntr2(reg.counter[2]); | |
54176736 | 132 | case 2: |
92c7b62f RB |
133 | w_c0_perfctrl1(0); |
134 | w_c0_perfcntr1(reg.counter[1]); | |
54176736 | 135 | case 1: |
92c7b62f RB |
136 | w_c0_perfctrl0(0); |
137 | w_c0_perfcntr0(reg.counter[0]); | |
54176736 RB |
138 | } |
139 | } | |
140 | ||
141 | /* Start all counters on current CPU */ | |
142 | static void mipsxx_cpu_start(void *args) | |
143 | { | |
1acf1ca7 | 144 | unsigned int counters = op_model_mipsxx_ops.num_counters; |
54176736 RB |
145 | |
146 | switch (counters) { | |
147 | case 4: | |
92c7b62f | 148 | w_c0_perfctrl3(WHAT | reg.control[3]); |
54176736 | 149 | case 3: |
92c7b62f | 150 | w_c0_perfctrl2(WHAT | reg.control[2]); |
54176736 | 151 | case 2: |
92c7b62f | 152 | w_c0_perfctrl1(WHAT | reg.control[1]); |
54176736 | 153 | case 1: |
92c7b62f | 154 | w_c0_perfctrl0(WHAT | reg.control[0]); |
54176736 RB |
155 | } |
156 | } | |
157 | ||
158 | /* Stop all counters on current CPU */ | |
159 | static void mipsxx_cpu_stop(void *args) | |
160 | { | |
1acf1ca7 | 161 | unsigned int counters = op_model_mipsxx_ops.num_counters; |
54176736 RB |
162 | |
163 | switch (counters) { | |
164 | case 4: | |
92c7b62f | 165 | w_c0_perfctrl3(0); |
54176736 | 166 | case 3: |
92c7b62f | 167 | w_c0_perfctrl2(0); |
54176736 | 168 | case 2: |
92c7b62f | 169 | w_c0_perfctrl1(0); |
54176736 | 170 | case 1: |
92c7b62f | 171 | w_c0_perfctrl0(0); |
54176736 RB |
172 | } |
173 | } | |
174 | ||
937a8015 | 175 | static int mipsxx_perfcount_handler(void) |
54176736 | 176 | { |
1acf1ca7 | 177 | unsigned int counters = op_model_mipsxx_ops.num_counters; |
54176736 RB |
178 | unsigned int control; |
179 | unsigned int counter; | |
ba339c03 | 180 | int handled = 0; |
54176736 RB |
181 | |
182 | switch (counters) { | |
183 | #define HANDLE_COUNTER(n) \ | |
184 | case n + 1: \ | |
92c7b62f RB |
185 | control = r_c0_perfctrl ## n(); \ |
186 | counter = r_c0_perfcntr ## n(); \ | |
54176736 RB |
187 | if ((control & M_PERFCTL_INTERRUPT_ENABLE) && \ |
188 | (counter & M_COUNTER_OVERFLOW)) { \ | |
937a8015 | 189 | oprofile_add_sample(get_irq_regs(), n); \ |
92c7b62f | 190 | w_c0_perfcntr ## n(reg.counter[n]); \ |
ba339c03 | 191 | handled = 1; \ |
54176736 RB |
192 | } |
193 | HANDLE_COUNTER(3) | |
194 | HANDLE_COUNTER(2) | |
195 | HANDLE_COUNTER(1) | |
196 | HANDLE_COUNTER(0) | |
197 | } | |
ba339c03 RB |
198 | |
199 | return handled; | |
54176736 RB |
200 | } |
201 | ||
202 | #define M_CONFIG1_PC (1 << 4) | |
203 | ||
92c7b62f | 204 | static inline int __n_counters(void) |
54176736 RB |
205 | { |
206 | if (!(read_c0_config1() & M_CONFIG1_PC)) | |
207 | return 0; | |
92c7b62f | 208 | if (!(r_c0_perfctrl0() & M_PERFCTL_MORE)) |
54176736 | 209 | return 1; |
92c7b62f | 210 | if (!(r_c0_perfctrl1() & M_PERFCTL_MORE)) |
54176736 | 211 | return 2; |
92c7b62f | 212 | if (!(r_c0_perfctrl2() & M_PERFCTL_MORE)) |
54176736 RB |
213 | return 3; |
214 | ||
215 | return 4; | |
216 | } | |
217 | ||
92c7b62f RB |
218 | static inline int n_counters(void) |
219 | { | |
714cfe78 RB |
220 | int counters; |
221 | ||
222 | switch (current_cpu_data.cputype) { | |
223 | case CPU_R10000: | |
224 | counters = 2; | |
148171b2 | 225 | break; |
714cfe78 RB |
226 | |
227 | case CPU_R12000: | |
228 | case CPU_R14000: | |
229 | counters = 4; | |
148171b2 | 230 | break; |
714cfe78 RB |
231 | |
232 | default: | |
233 | counters = __n_counters(); | |
234 | } | |
92c7b62f | 235 | |
92c7b62f RB |
236 | return counters; |
237 | } | |
238 | ||
54176736 RB |
239 | static inline void reset_counters(int counters) |
240 | { | |
241 | switch (counters) { | |
242 | case 4: | |
92c7b62f RB |
243 | w_c0_perfctrl3(0); |
244 | w_c0_perfcntr3(0); | |
54176736 | 245 | case 3: |
92c7b62f RB |
246 | w_c0_perfctrl2(0); |
247 | w_c0_perfcntr2(0); | |
54176736 | 248 | case 2: |
92c7b62f RB |
249 | w_c0_perfctrl1(0); |
250 | w_c0_perfcntr1(0); | |
54176736 | 251 | case 1: |
92c7b62f RB |
252 | w_c0_perfctrl0(0); |
253 | w_c0_perfcntr0(0); | |
54176736 RB |
254 | } |
255 | } | |
256 | ||
257 | static int __init mipsxx_init(void) | |
258 | { | |
259 | int counters; | |
260 | ||
261 | counters = n_counters(); | |
9efeae9a RB |
262 | if (counters == 0) { |
263 | printk(KERN_ERR "Oprofile: CPU has no performance counters\n"); | |
54176736 | 264 | return -ENODEV; |
9efeae9a | 265 | } |
54176736 RB |
266 | |
267 | reset_counters(counters); | |
268 | ||
795a2258 CD |
269 | #ifdef CONFIG_MIPS_MT_SMP |
270 | counters >>= 1; | |
271 | #endif | |
272 | ||
1acf1ca7 | 273 | op_model_mipsxx_ops.num_counters = counters; |
54176736 | 274 | switch (current_cpu_data.cputype) { |
2065988e | 275 | case CPU_20KC: |
1acf1ca7 | 276 | op_model_mipsxx_ops.cpu_type = "mips/20K"; |
2065988e RB |
277 | break; |
278 | ||
54176736 | 279 | case CPU_24K: |
1acf1ca7 | 280 | op_model_mipsxx_ops.cpu_type = "mips/24K"; |
54176736 RB |
281 | break; |
282 | ||
2065988e | 283 | case CPU_25KF: |
1acf1ca7 | 284 | op_model_mipsxx_ops.cpu_type = "mips/25K"; |
2065988e RB |
285 | break; |
286 | ||
fcfd980c | 287 | case CPU_34K: |
1acf1ca7 | 288 | op_model_mipsxx_ops.cpu_type = "mips/34K"; |
fcfd980c | 289 | break; |
c620953c CD |
290 | |
291 | case CPU_74K: | |
1acf1ca7 | 292 | op_model_mipsxx_ops.cpu_type = "mips/74K"; |
c620953c | 293 | break; |
fcfd980c | 294 | |
2065988e | 295 | case CPU_5KC: |
1acf1ca7 | 296 | op_model_mipsxx_ops.cpu_type = "mips/5K"; |
2065988e RB |
297 | break; |
298 | ||
714cfe78 RB |
299 | case CPU_R10000: |
300 | if ((current_cpu_data.processor_id & 0xff) == 0x20) | |
301 | op_model_mipsxx_ops.cpu_type = "mips/r10000-v2.x"; | |
302 | else | |
303 | op_model_mipsxx_ops.cpu_type = "mips/r10000"; | |
304 | break; | |
305 | ||
306 | case CPU_R12000: | |
307 | case CPU_R14000: | |
308 | op_model_mipsxx_ops.cpu_type = "mips/r12000"; | |
309 | break; | |
310 | ||
c03bc121 MM |
311 | case CPU_SB1: |
312 | case CPU_SB1A: | |
1acf1ca7 | 313 | op_model_mipsxx_ops.cpu_type = "mips/sb1"; |
c03bc121 MM |
314 | break; |
315 | ||
54176736 RB |
316 | default: |
317 | printk(KERN_ERR "Profiling unsupported for this CPU\n"); | |
318 | ||
319 | return -ENODEV; | |
320 | } | |
321 | ||
322 | perf_irq = mipsxx_perfcount_handler; | |
323 | ||
324 | return 0; | |
325 | } | |
326 | ||
327 | static void mipsxx_exit(void) | |
328 | { | |
795a2258 CD |
329 | int counters = op_model_mipsxx_ops.num_counters; |
330 | #ifdef CONFIG_MIPS_MT_SMP | |
331 | counters <<= 1; | |
332 | #endif | |
333 | reset_counters(counters); | |
54176736 RB |
334 | |
335 | perf_irq = null_perf_irq; | |
336 | } | |
337 | ||
1acf1ca7 | 338 | struct op_mips_model op_model_mipsxx_ops = { |
54176736 RB |
339 | .reg_setup = mipsxx_reg_setup, |
340 | .cpu_setup = mipsxx_cpu_setup, | |
341 | .init = mipsxx_init, | |
342 | .exit = mipsxx_exit, | |
343 | .cpu_start = mipsxx_cpu_start, | |
344 | .cpu_stop = mipsxx_cpu_stop, | |
345 | }; |