[deliverable/linux.git] / arch / mips / pci / msi-octeon.c

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 2005-2009 Cavium Networks
 */
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/msi.h>
#include <linux/spinlock.h>
#include <linux/interrupt.h>

#include <asm/octeon/octeon.h>
#include <asm/octeon/cvmx-npi-defs.h>
#include <asm/octeon/cvmx-pci-defs.h>
#include <asm/octeon/cvmx-npei-defs.h>
#include <asm/octeon/cvmx-pexp-defs.h>
#include <asm/octeon/pci-octeon.h>

/*
 * Each bit in msi_free_irq_bitmask represents a MSI interrupt that is
 * in use.
 */
static uint64_t msi_free_irq_bitmask;

/*
 * Each bit in msi_multiple_irq_bitmask tells that the device using
 * this bit in msi_free_irq_bitmask is also using the next bit. This
 * is used so we can disable all of the MSI interrupts when a device
 * uses multiple.
 */
static uint64_t msi_multiple_irq_bitmask;

/*
 * This lock controls updates to msi_free_irq_bitmask and
 * msi_multiple_irq_bitmask.
 */
static DEFINE_SPINLOCK(msi_free_irq_bitmask_lock);


/**
 * Called when a driver request MSI interrupts instead of the
 * legacy INT A-D. This routine will allocate multiple interrupts
 * for MSI devices that support them. A device can override this by
 * programming the MSI control bits [6:4] before calling
 * pci_enable_msi().
 *
 * @dev:    Device requesting MSI interrupts
 * @desc:   MSI descriptor
 *
 * Returns 0 on success.
 */
int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
{
	struct msi_msg msg;
	uint16_t control;
	int configured_private_bits;
	int request_private_bits;
	int irq;
	int irq_step;
	uint64_t search_mask;

	/*
	 * Read the MSI config to figure out how many IRQs this device
	 * wants.  Most devices only want 1, which will give
	 * configured_private_bits and request_private_bits equal 0.
	 */
	pci_read_config_word(dev, desc->msi_attrib.pos + PCI_MSI_FLAGS,
			     &control);

	/*
	 * If the number of private bits has been configured then use
	 * that value instead of the requested number. This gives the
	 * driver the chance to override the number of interrupts
	 * before calling pci_enable_msi().
	 */
	configured_private_bits = (control & PCI_MSI_FLAGS_QSIZE) >> 4;
	if (configured_private_bits == 0) {
		/* Nothing is configured, so use the hardware requested size */
		request_private_bits = (control & PCI_MSI_FLAGS_QMASK) >> 1;
	} else {
		/*
		 * Use the number of configured bits, assuming the
		 * driver wanted to override the hardware request
		 * value.
		 */
		request_private_bits = configured_private_bits;
	}

	/*
	 * The PCI 2.3 spec mandates that there are at most 32
	 * interrupts. If this device asks for more, only give it one.
	 */
	if (request_private_bits > 5)
		request_private_bits = 0;

try_only_one:
	/*
	 * The IRQs have to be aligned on a power of two based on the
	 * number being requested.
	 */
	irq_step = 1 << request_private_bits;

	/* Mask with one bit for each IRQ */
	search_mask = (1 << irq_step) - 1;

	/*
	 * We're going to search msi_free_irq_bitmask_lock for zero
	 * bits. This represents an MSI interrupt number that isn't in
	 * use.
	 */
	spin_lock(&msi_free_irq_bitmask_lock);
	for (irq = 0; irq < 64; irq += irq_step) {
		if ((msi_free_irq_bitmask & (search_mask << irq)) == 0) {
			msi_free_irq_bitmask |= search_mask << irq;
			msi_multiple_irq_bitmask |= (search_mask >> 1) << irq;
			break;
		}
	}
	spin_unlock(&msi_free_irq_bitmask_lock);

	/* Make sure the search for available interrupts didn't fail */
	if (irq >= 64) {
		if (request_private_bits) {
			pr_err("arch_setup_msi_irq: Unable to find %d free "
			       "interrupts, trying just one",
			       1 << request_private_bits);
			request_private_bits = 0;
			goto try_only_one;
		} else
			panic("arch_setup_msi_irq: Unable to find a free MSI "
			      "interrupt");
	}

	/* MSI interrupts start at logical IRQ OCTEON_IRQ_MSI_BIT0 */
	irq += OCTEON_IRQ_MSI_BIT0;

	switch (octeon_dma_bar_type) {
	case OCTEON_DMA_BAR_TYPE_SMALL:
		/* When not using big bar, Bar 0 is based at 128MB */
		msg.address_lo =
			((128ul << 20) + CVMX_PCI_MSI_RCV) & 0xffffffff;
		msg.address_hi = ((128ul << 20) + CVMX_PCI_MSI_RCV) >> 32;
	case OCTEON_DMA_BAR_TYPE_BIG:
		/* When using big bar, Bar 0 is based at 0 */
		msg.address_lo = (0 + CVMX_PCI_MSI_RCV) & 0xffffffff;
		msg.address_hi = (0 + CVMX_PCI_MSI_RCV) >> 32;
		break;
	case OCTEON_DMA_BAR_TYPE_PCIE:
		/* When using PCIe, Bar 0 is based at 0 */
		/* FIXME CVMX_NPEI_MSI_RCV* other than 0? */
		msg.address_lo = (0 + CVMX_NPEI_PCIE_MSI_RCV) & 0xffffffff;
		msg.address_hi = (0 + CVMX_NPEI_PCIE_MSI_RCV) >> 32;
		break;
	default:
		panic("arch_setup_msi_irq: Invalid octeon_dma_bar_type\n");
	}
	msg.data = irq - OCTEON_IRQ_MSI_BIT0;

	/* Update the number of IRQs the device has available to it */
	control &= ~PCI_MSI_FLAGS_QSIZE;
	control |= request_private_bits << 4;
	pci_write_config_word(dev, desc->msi_attrib.pos + PCI_MSI_FLAGS,
			      control);

	set_irq_msi(irq, desc);
	write_msi_msg(irq, &msg);
	return 0;
}


/**
 * Called when a device no longer needs its MSI interrupts. All
 * MSI interrupts for the device are freed.
 *
 * @irq:    The devices first irq number. There may be multple in sequence.
 */
void arch_teardown_msi_irq(unsigned int irq)
{
	int number_irqs;
	uint64_t bitmask;

	if ((irq < OCTEON_IRQ_MSI_BIT0) || (irq > OCTEON_IRQ_MSI_BIT63))
		panic("arch_teardown_msi_irq: Attempted to teardown illegal "
		      "MSI interrupt (%d)", irq);
	irq -= OCTEON_IRQ_MSI_BIT0;

	/*
	 * Count the number of IRQs we need to free by looking at the
	 * msi_multiple_irq_bitmask. Each bit set means that the next
	 * IRQ is also owned by this device.
	 */
	number_irqs = 0;
	while ((irq+number_irqs < 64) &&
	       (msi_multiple_irq_bitmask & (1ull << (irq + number_irqs))))
		number_irqs++;
	number_irqs++;
	/* Mask with one bit for each IRQ */
	bitmask = (1 << number_irqs) - 1;
	/* Shift the mask to the correct bit location */
	bitmask <<= irq;
	if ((msi_free_irq_bitmask & bitmask) != bitmask)
		panic("arch_teardown_msi_irq: Attempted to teardown MSI "
		      "interrupt (%d) not in use", irq);

	/* Checks are done, update the in use bitmask */
	spin_lock(&msi_free_irq_bitmask_lock);
	msi_free_irq_bitmask &= ~bitmask;
	msi_multiple_irq_bitmask &= ~bitmask;
	spin_unlock(&msi_free_irq_bitmask_lock);
}


/*
 * Called by the interrupt handling code when an MSI interrupt
 * occurs.
 */
static irqreturn_t octeon_msi_interrupt(int cpl, void *dev_id)
{
	uint64_t msi_bits;
	int irq;

	if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_PCIE)
		msi_bits = cvmx_read_csr(CVMX_PEXP_NPEI_MSI_RCV0);
	else
		msi_bits = cvmx_read_csr(CVMX_NPI_NPI_MSI_RCV);
	irq = fls64(msi_bits);
	if (irq) {
		irq += OCTEON_IRQ_MSI_BIT0 - 1;
		if (irq_desc[irq].action) {
			do_IRQ(irq);
			return IRQ_HANDLED;
		} else {
			pr_err("Spurious MSI interrupt %d\n", irq);
			if (octeon_has_feature(OCTEON_FEATURE_PCIE)) {
				/* These chips have PCIe */
				cvmx_write_csr(CVMX_PEXP_NPEI_MSI_RCV0,
					       1ull << (irq -
							OCTEON_IRQ_MSI_BIT0));
			} else {
				/* These chips have PCI */
				cvmx_write_csr(CVMX_NPI_NPI_MSI_RCV,
					       1ull << (irq -
							OCTEON_IRQ_MSI_BIT0));
			}
		}
	}
	return IRQ_NONE;
}


/*
 * Initializes the MSI interrupt handling code
 */
int octeon_msi_initialize(void)
{
	if (octeon_has_feature(OCTEON_FEATURE_PCIE)) {
		if (request_irq(OCTEON_IRQ_PCI_MSI0, octeon_msi_interrupt,
				IRQF_SHARED,
				"MSI[0:63]", octeon_msi_interrupt))
			panic("request_irq(OCTEON_IRQ_PCI_MSI0) failed");
	} else if (octeon_is_pci_host()) {
		if (request_irq(OCTEON_IRQ_PCI_MSI0, octeon_msi_interrupt,
				IRQF_SHARED,
				"MSI[0:15]", octeon_msi_interrupt))
			panic("request_irq(OCTEON_IRQ_PCI_MSI0) failed");

		if (request_irq(OCTEON_IRQ_PCI_MSI1, octeon_msi_interrupt,
				IRQF_SHARED,
				"MSI[16:31]", octeon_msi_interrupt))
			panic("request_irq(OCTEON_IRQ_PCI_MSI1) failed");

		if (request_irq(OCTEON_IRQ_PCI_MSI2, octeon_msi_interrupt,
				IRQF_SHARED,
				"MSI[32:47]", octeon_msi_interrupt))
			panic("request_irq(OCTEON_IRQ_PCI_MSI2) failed");

		if (request_irq(OCTEON_IRQ_PCI_MSI3, octeon_msi_interrupt,
				IRQF_SHARED,
				"MSI[48:63]", octeon_msi_interrupt))
			panic("request_irq(OCTEON_IRQ_PCI_MSI3) failed");

	}
	return 0;
}

subsys_initcall(octeon_msi_initialize);
Commit	Line	Data
e8635b48 DD	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
01a6221a	6	* Copyright (C) 2005-2009 Cavium Networks
e8635b48 DD	7	*/
	8	#include <linux/kernel.h>
	9	#include <linux/init.h>
	10	#include <linux/msi.h>
	11	#include <linux/spinlock.h>
	12	#include <linux/interrupt.h>
	13
	14	#include <asm/octeon/octeon.h>
	15	#include <asm/octeon/cvmx-npi-defs.h>
	16	#include <asm/octeon/cvmx-pci-defs.h>
	17	#include <asm/octeon/cvmx-npei-defs.h>
	18	#include <asm/octeon/cvmx-pexp-defs.h>
01a6221a	19	#include <asm/octeon/pci-octeon.h>
e8635b48 DD	20
	21	/*
	22	* Each bit in msi_free_irq_bitmask represents a MSI interrupt that is
	23	* in use.
	24	*/
	25	static uint64_t msi_free_irq_bitmask;
	26
	27	/*
	28	* Each bit in msi_multiple_irq_bitmask tells that the device using
	29	* this bit in msi_free_irq_bitmask is also using the next bit. This
	30	* is used so we can disable all of the MSI interrupts when a device
	31	* uses multiple.
	32	*/
	33	static uint64_t msi_multiple_irq_bitmask;
	34
	35	/*
	36	* This lock controls updates to msi_free_irq_bitmask and
	37	* msi_multiple_irq_bitmask.
	38	*/
	39	static DEFINE_SPINLOCK(msi_free_irq_bitmask_lock);
	40
	41
	42	/**
	43	* Called when a driver request MSI interrupts instead of the
	44	* legacy INT A-D. This routine will allocate multiple interrupts
	45	* for MSI devices that support them. A device can override this by
	46	* programming the MSI control bits [6:4] before calling
	47	* pci_enable_msi().
	48	*
01a6221a DD	49	* @dev: Device requesting MSI interrupts
01a6221a DD	50	* @desc: MSI descriptor
e8635b48 DD	51	*
	52	* Returns 0 on success.
	53	*/
	54	int arch_setup_msi_irq(struct pci_dev dev, struct msi_desc desc)
	55	{
	56	struct msi_msg msg;
	57	uint16_t control;
	58	int configured_private_bits;
	59	int request_private_bits;
	60	int irq;
	61	int irq_step;
	62	uint64_t search_mask;
	63
	64	/*
	65	* Read the MSI config to figure out how many IRQs this device
	66	* wants. Most devices only want 1, which will give
	67	* configured_private_bits and request_private_bits equal 0.
	68	*/
	69	pci_read_config_word(dev, desc->msi_attrib.pos + PCI_MSI_FLAGS,
	70	&control);
	71
	72	/*
	73	* If the number of private bits has been configured then use
	74	* that value instead of the requested number. This gives the
	75	* driver the chance to override the number of interrupts
	76	* before calling pci_enable_msi().
	77	*/
	78	configured_private_bits = (control & PCI_MSI_FLAGS_QSIZE) >> 4;
	79	if (configured_private_bits == 0) {
	80	/* Nothing is configured, so use the hardware requested size */
	81	request_private_bits = (control & PCI_MSI_FLAGS_QMASK) >> 1;
	82	} else {
	83	/*
	84	* Use the number of configured bits, assuming the
	85	* driver wanted to override the hardware request
	86	* value.
	87	*/
	88	request_private_bits = configured_private_bits;
	89	}
	90
	91	/*
	92	* The PCI 2.3 spec mandates that there are at most 32
	93	* interrupts. If this device asks for more, only give it one.
	94	*/
	95	if (request_private_bits > 5)
	96	request_private_bits = 0;
	97
	98	try_only_one:
	99	/*
	100	* The IRQs have to be aligned on a power of two based on the
	101	* number being requested.
	102	*/
	103	irq_step = 1 << request_private_bits;
	104
	105	/* Mask with one bit for each IRQ */
	106	search_mask = (1 << irq_step) - 1;
	107
	108	/*
	109	* We're going to search msi_free_irq_bitmask_lock for zero
	110	* bits. This represents an MSI interrupt number that isn't in
	111	* use.
	112	*/
	113	spin_lock(&msi_free_irq_bitmask_lock);
	114	for (irq = 0; irq < 64; irq += irq_step) {
115	if ((msi_free_irq_bitmask & (search_mask << irq)) == 0) {
116	msi_free_irq_bitmask \|= search_mask << irq;
117	msi_multiple_irq_bitmask \|= (search_mask >> 1) << irq;
118	break;
119	}
120	}
121	spin_unlock(&msi_free_irq_bitmask_lock);
122
123	/* Make sure the search for available interrupts didn't fail */
124	if (irq >= 64) {
125	if (request_private_bits) {
126	pr_err("arch_setup_msi_irq: Unable to find %d free "
127	"interrupts, trying just one",
128	1 << request_private_bits);
129	request_private_bits = 0;
130	goto try_only_one;
131	} else
132	panic("arch_setup_msi_irq: Unable to find a free MSI "
133	"interrupt");
134	}
135
136	/* MSI interrupts start at logical IRQ OCTEON_IRQ_MSI_BIT0 */
137	irq += OCTEON_IRQ_MSI_BIT0;
138
139	switch (octeon_dma_bar_type) {
140	case OCTEON_DMA_BAR_TYPE_SMALL:
141	/* When not using big bar, Bar 0 is based at 128MB */
142	msg.address_lo =
143	((128ul << 20) + CVMX_PCI_MSI_RCV) & 0xffffffff;
144	msg.address_hi = ((128ul << 20) + CVMX_PCI_MSI_RCV) >> 32;
145	case OCTEON_DMA_BAR_TYPE_BIG:
146	/* When using big bar, Bar 0 is based at 0 */
147	msg.address_lo = (0 + CVMX_PCI_MSI_RCV) & 0xffffffff;
148	msg.address_hi = (0 + CVMX_PCI_MSI_RCV) >> 32;
149	break;
150	case OCTEON_DMA_BAR_TYPE_PCIE:
151	/* When using PCIe, Bar 0 is based at 0 */
152	/* FIXME CVMX_NPEI_MSI_RCV* other than 0? */
153	msg.address_lo = (0 + CVMX_NPEI_PCIE_MSI_RCV) & 0xffffffff;
154	msg.address_hi = (0 + CVMX_NPEI_PCIE_MSI_RCV) >> 32;
155	break;
156	default:
157	panic("arch_setup_msi_irq: Invalid octeon_dma_bar_type\n");
158	}
159	msg.data = irq - OCTEON_IRQ_MSI_BIT0;
160
161	/* Update the number of IRQs the device has available to it */
162	control &= ~PCI_MSI_FLAGS_QSIZE;
163	control \|= request_private_bits << 4;
164	pci_write_config_word(dev, desc->msi_attrib.pos + PCI_MSI_FLAGS,
165	control);
166
167	set_irq_msi(irq, desc);
168	write_msi_msg(irq, &msg);
169	return 0;
170	}
171
172
173	/**
174	* Called when a device no longer needs its MSI interrupts. All
175	* MSI interrupts for the device are freed.
176	*
177	* @irq: The devices first irq number. There may be multple in sequence.
178	*/
179	void arch_teardown_msi_irq(unsigned int irq)
180	{
181	int number_irqs;
182	uint64_t bitmask;
183
184	if ((irq < OCTEON_IRQ_MSI_BIT0) \|\| (irq > OCTEON_IRQ_MSI_BIT63))
185	panic("arch_teardown_msi_irq: Attempted to teardown illegal "
186	"MSI interrupt (%d)", irq);
187	irq -= OCTEON_IRQ_MSI_BIT0;
188
189	/*
190	* Count the number of IRQs we need to free by looking at the
191	* msi_multiple_irq_bitmask. Each bit set means that the next
192	* IRQ is also owned by this device.
193	*/
194	number_irqs = 0;
195	while ((irq+number_irqs < 64) &&
196	(msi_multiple_irq_bitmask & (1ull << (irq + number_irqs))))
197	number_irqs++;
198	number_irqs++;
199	/* Mask with one bit for each IRQ */
200	bitmask = (1 << number_irqs) - 1;
201	/* Shift the mask to the correct bit location */
202	bitmask <<= irq;
203	if ((msi_free_irq_bitmask & bitmask) != bitmask)
204	panic("arch_teardown_msi_irq: Attempted to teardown MSI "
205	"interrupt (%d) not in use", irq);
206
207	/* Checks are done, update the in use bitmask */
208	spin_lock(&msi_free_irq_bitmask_lock);
209	msi_free_irq_bitmask &= ~bitmask;
210	msi_multiple_irq_bitmask &= ~bitmask;
211	spin_unlock(&msi_free_irq_bitmask_lock);
212	}
213
214
01a6221a	215	/*
e8635b48 DD	216	* Called by the interrupt handling code when an MSI interrupt
e8635b48 DD	217	* occurs.
e8635b48 DD	218	*/
	219	static irqreturn_t octeon_msi_interrupt(int cpl, void *dev_id)
	220	{
	221	uint64_t msi_bits;
	222	int irq;
	223
	224	if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_PCIE)
	225	msi_bits = cvmx_read_csr(CVMX_PEXP_NPEI_MSI_RCV0);
	226	else
	227	msi_bits = cvmx_read_csr(CVMX_NPI_NPI_MSI_RCV);
	228	irq = fls64(msi_bits);
	229	if (irq) {
	230	irq += OCTEON_IRQ_MSI_BIT0 - 1;
	231	if (irq_desc[irq].action) {
	232	do_IRQ(irq);
	233	return IRQ_HANDLED;
	234	} else {
	235	pr_err("Spurious MSI interrupt %d\n", irq);
	236	if (octeon_has_feature(OCTEON_FEATURE_PCIE)) {
	237	/* These chips have PCIe */
	238	cvmx_write_csr(CVMX_PEXP_NPEI_MSI_RCV0,
	239	1ull << (irq -
	240	OCTEON_IRQ_MSI_BIT0));
	241	} else {
	242	/* These chips have PCI */
	243	cvmx_write_csr(CVMX_NPI_NPI_MSI_RCV,
	244	1ull << (irq -
	245	OCTEON_IRQ_MSI_BIT0));
	246	}
	247	}
	248	}
	249	return IRQ_NONE;
	250	}
	251
	252
01a6221a	253	/*
e8635b48	254	* Initializes the MSI interrupt handling code
e8635b48 DD	255	*/
	256	int octeon_msi_initialize(void)
	257	{
e8635b48	258	if (octeon_has_feature(OCTEON_FEATURE_PCIE)) {
01a6221a	259	if (request_irq(OCTEON_IRQ_PCI_MSI0, octeon_msi_interrupt,
e8635b48	260	IRQF_SHARED,
01a6221a DD	261	"MSI[0:63]", octeon_msi_interrupt))
01a6221a DD	262	panic("request_irq(OCTEON_IRQ_PCI_MSI0) failed");
e8635b48	263	} else if (octeon_is_pci_host()) {
01a6221a	264	if (request_irq(OCTEON_IRQ_PCI_MSI0, octeon_msi_interrupt,
e8635b48	265	IRQF_SHARED,
01a6221a DD	266	"MSI[0:15]", octeon_msi_interrupt))
	267	panic("request_irq(OCTEON_IRQ_PCI_MSI0) failed");
	268
	269	if (request_irq(OCTEON_IRQ_PCI_MSI1, octeon_msi_interrupt,
	270	IRQF_SHARED,
	271	"MSI[16:31]", octeon_msi_interrupt))
	272	panic("request_irq(OCTEON_IRQ_PCI_MSI1) failed");
	273
	274	if (request_irq(OCTEON_IRQ_PCI_MSI2, octeon_msi_interrupt,
	275	IRQF_SHARED,
	276	"MSI[32:47]", octeon_msi_interrupt))
	277	panic("request_irq(OCTEON_IRQ_PCI_MSI2) failed");
	278
	279	if (request_irq(OCTEON_IRQ_PCI_MSI3, octeon_msi_interrupt,
	280	IRQF_SHARED,
	281	"MSI[48:63]", octeon_msi_interrupt))
	282	panic("request_irq(OCTEON_IRQ_PCI_MSI3) failed");
	283
e8635b48 DD	284	}
	285	return 0;
	286	}
	287
	288	subsys_initcall(octeon_msi_initialize);