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MIPS: Octeon: Dlink_dsr-1000n.dts: add more leds.
[deliverable/linux.git] / arch / mips / pci / ops-tx4927.c
CommitLineData
1da177e4 1/*
89d63fe1 2 * Define the pci_ops for the PCIC on Toshiba TX4927, TX4938, etc.
1da177e4 3 *
89d63fe1 4 * Based on linux/arch/mips/pci/ops-tx4938.c,
70342287
RB		 5 * linux/arch/mips/pci/fixup-rbtx4938.c,
6 * linux/arch/mips/txx9/rbtx4938/setup.c,
89d63fe1 7 * and RBTX49xx patch from CELF patch archive.
1da177e4 8 *
89d63fe1
AN		 9 * 2003-2005 (c) MontaVista Software, Inc.
10 * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
11 * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
1da177e4 12 *
70342287
RB		 13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
89d63fe1
AN		 15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
1da177e4 17 */
1da177e4 18#include <linux/kernel.h>
455cc256 19#include <linux/interrupt.h>
ca4d3e67 20#include <linux/irq.h>
455cc256 21#include <asm/txx9/pci.h>
89d63fe1 22#include <asm/txx9/tx4927pcic.h>
1da177e4 23
89d63fe1
AN		 24static struct {
25 struct pci_controller *channel;
26 struct tx4927_pcic_reg __iomem *pcicptr;
27} pcicptrs[2]; /* TX4938 has 2 pcic */
28
29static void __init set_tx4927_pcicptr(struct pci_controller *channel,
30 struct tx4927_pcic_reg __iomem *pcicptr)
31{
32 int i;
33
34 for (i = 0; i < ARRAY_SIZE(pcicptrs); i++) {
35 if (pcicptrs[i].channel == channel) {
36 pcicptrs[i].pcicptr = pcicptr;
37 return;
38 }
39 }
40 for (i = 0; i < ARRAY_SIZE(pcicptrs); i++) {
41 if (!pcicptrs[i].channel) {
42 pcicptrs[i].channel = channel;
43 pcicptrs[i].pcicptr = pcicptr;
44 return;
45 }
46 }
47 BUG();
48}
1da177e4 49
89d63fe1
AN		 50struct tx4927_pcic_reg __iomem *get_tx4927_pcicptr(
51 struct pci_controller *channel)
1da177e4 52{
89d63fe1 53 int i;
1da177e4 54
89d63fe1
AN		 55 for (i = 0; i < ARRAY_SIZE(pcicptrs); i++) {
56 if (pcicptrs[i].channel == channel)
57 return pcicptrs[i].pcicptr;
1da177e4 58 }
89d63fe1
AN		 59 return NULL;
60}
61
62static int mkaddr(struct pci_bus *bus, unsigned int devfn, int where,
63 struct tx4927_pcic_reg __iomem *pcicptr)
64{
65 if (bus->parent == NULL &&
66 devfn >= PCI_DEVFN(TX4927_PCIC_MAX_DEVNU, 0))
67 return -1;
68 __raw_writel(((bus->number & 0xff) << 0x10)
69 | ((devfn & 0xff) << 0x08) | (where & 0xfc)
70 | (bus->parent ? 1 : 0),
71 &pcicptr->g2pcfgadrs);
1da177e4 72 /* clear M_ABORT and Disable M_ABORT Int. */
89d63fe1
AN		 73 __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff)
74 | (PCI_STATUS_REC_MASTER_ABORT << 16),
75 &pcicptr->pcistatus);
1da177e4
LT		 76 return 0;
77}
78
89d63fe1 79static int check_abort(struct tx4927_pcic_reg __iomem *pcicptr)
1da177e4
LT		 80{
81 int code = PCIBIOS_SUCCESSFUL;
89d63fe1
AN		 82
83 /* wait write cycle completion before checking error status */
84 while (__raw_readl(&pcicptr->pcicstatus) & TX4927_PCIC_PCICSTATUS_IWB)
85 ;
86 if (__raw_readl(&pcicptr->pcistatus)
87 & (PCI_STATUS_REC_MASTER_ABORT << 16)) {
88 __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff)
89 | (PCI_STATUS_REC_MASTER_ABORT << 16),
90 &pcicptr->pcistatus);
32d00d0f
AN		 91 /* flush write buffer */
92 iob();
1da177e4
LT		 93 code = PCIBIOS_DEVICE_NOT_FOUND;
94 }
95 return code;
96}
97
89d63fe1
AN		 98static u8 icd_readb(int offset, struct tx4927_pcic_reg __iomem *pcicptr)
99{
100#ifdef __BIG_ENDIAN
101 offset ^= 3;
102#endif
103 return __raw_readb((void __iomem *)&pcicptr->g2pcfgdata + offset);
104}
105static u16 icd_readw(int offset, struct tx4927_pcic_reg __iomem *pcicptr)
106{
107#ifdef __BIG_ENDIAN
108 offset ^= 2;
109#endif
110 return __raw_readw((void __iomem *)&pcicptr->g2pcfgdata + offset);
111}
112static u32 icd_readl(struct tx4927_pcic_reg __iomem *pcicptr)
113{
114 return __raw_readl(&pcicptr->g2pcfgdata);
115}
116static void icd_writeb(u8 val, int offset,
117 struct tx4927_pcic_reg __iomem *pcicptr)
118{
119#ifdef __BIG_ENDIAN
120 offset ^= 3;
121#endif
122 __raw_writeb(val, (void __iomem *)&pcicptr->g2pcfgdata + offset);
123}
124static void icd_writew(u16 val, int offset,
125 struct tx4927_pcic_reg __iomem *pcicptr)
126{
127#ifdef __BIG_ENDIAN
128 offset ^= 2;
129#endif
130 __raw_writew(val, (void __iomem *)&pcicptr->g2pcfgdata + offset);
131}
132static void icd_writel(u32 val, struct tx4927_pcic_reg __iomem *pcicptr)
1da177e4 133{
89d63fe1
AN		 134 __raw_writel(val, &pcicptr->g2pcfgdata);
135}
1da177e4 136
89d63fe1
AN		 137static struct tx4927_pcic_reg __iomem *pci_bus_to_pcicptr(struct pci_bus *bus)
138{
139 struct pci_controller *channel = bus->sysdata;
140 return get_tx4927_pcicptr(channel);
141}
1da177e4 142
89d63fe1
AN		 143static int tx4927_pci_config_read(struct pci_bus *bus, unsigned int devfn,
144 int where, int size, u32 *val)
145{
146 struct tx4927_pcic_reg __iomem *pcicptr = pci_bus_to_pcicptr(bus);
1da177e4 147
89d63fe1
AN		 148 if (mkaddr(bus, devfn, where, pcicptr)) {
149 *val = 0xffffffff;
1da177e4 150 return -1;
89d63fe1 151 }
1da177e4
LT		 152 switch (size) {
153 case 1:
89d63fe1 154 *val = icd_readb(where & 3, pcicptr);
1da177e4
LT		 155 break;
156 case 2:
89d63fe1 157 *val = icd_readw(where & 3, pcicptr);
1da177e4 158 break;
89d63fe1
AN		 159 default:
160 *val = icd_readl(pcicptr);
1da177e4 161 }
89d63fe1
AN		 162 return check_abort(pcicptr);
163}
1da177e4 164
89d63fe1
AN		 165static int tx4927_pci_config_write(struct pci_bus *bus, unsigned int devfn,
166 int where, int size, u32 val)
167{
168 struct tx4927_pcic_reg __iomem *pcicptr = pci_bus_to_pcicptr(bus);
1da177e4 169
89d63fe1
AN		 170 if (mkaddr(bus, devfn, where, pcicptr))
171 return -1;
172 switch (size) {
173 case 1:
174 icd_writeb(val, where & 3, pcicptr);
175 break;
176 case 2:
177 icd_writew(val, where & 3, pcicptr);
178 break;
179 default:
180 icd_writel(val, pcicptr);
181 }
182 return check_abort(pcicptr);
1da177e4
LT		 183}
184
89d63fe1
AN		 185static struct pci_ops tx4927_pci_ops = {
186 .read = tx4927_pci_config_read,
187 .write = tx4927_pci_config_write,
188};
189
190static struct {
191 u8 trdyto;
192 u8 retryto;
193 u16 gbwc;
28eb0e46 194} tx4927_pci_opts = {
89d63fe1
AN		 195 .trdyto = 0,
196 .retryto = 0,
197 .gbwc = 0xfe0, /* 4064 GBUSCLK for CCFG.GTOT=0b11 */
198};
199
28eb0e46 200char *tx4927_pcibios_setup(char *str)
07517529 201{
07517529 202 if (!strncmp(str, "trdyto=", 7)) {
8e9ecbc5
DW		 203 u8 val = 0;
204 if (kstrtou8(str + 7, 0, &val) == 0)
07517529
AN		 205 tx4927_pci_opts.trdyto = val;
206 return NULL;
207 }
208 if (!strncmp(str, "retryto=", 8)) {
8e9ecbc5
DW		 209 u8 val = 0;
210 if (kstrtou8(str + 8, 0, &val) == 0)
07517529
AN		 211 tx4927_pci_opts.retryto = val;
212 return NULL;
213 }
214 if (!strncmp(str, "gbwc=", 5)) {
8e9ecbc5
DW		 215 u16 val;
216 if (kstrtou16(str + 5, 0, &val) == 0)
07517529
AN		 217 tx4927_pci_opts.gbwc = val;
218 return NULL;
219 }
220 return str;
221}
222
89d63fe1
AN		 223void __init tx4927_pcic_setup(struct tx4927_pcic_reg __iomem *pcicptr,
224 struct pci_controller *channel, int extarb)
1da177e4 225{
89d63fe1
AN		 226 int i;
227 unsigned long flags;
1da177e4 228
89d63fe1 229 set_tx4927_pcicptr(channel, pcicptr);
1da177e4 230
89d63fe1
AN		 231 if (!channel->pci_ops)
232 printk(KERN_INFO
233 "PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s\n",
234 __raw_readl(&pcicptr->pciid) >> 16,
235 __raw_readl(&pcicptr->pciid) & 0xffff,
236 __raw_readl(&pcicptr->pciccrev) & 0xff,
237 extarb ? "External" : "Internal");
238 channel->pci_ops = &tx4927_pci_ops;
1da177e4 239
89d63fe1
AN		 240 local_irq_save(flags);
241
242 /* Disable All Initiator Space */
243 __raw_writel(__raw_readl(&pcicptr->pciccfg)
244 & ~(TX4927_PCIC_PCICCFG_G2PMEN(0)
245 | TX4927_PCIC_PCICCFG_G2PMEN(1)
246 | TX4927_PCIC_PCICCFG_G2PMEN(2)
247 | TX4927_PCIC_PCICCFG_G2PIOEN),
248 &pcicptr->pciccfg);
249
250 /* GB->PCI mappings */
251 __raw_writel((channel->io_resource->end - channel->io_resource->start)
252 >> 4,
253 &pcicptr->g2piomask);
254 ____raw_writeq((channel->io_resource->start +
255 channel->io_map_base - IO_BASE) |
256#ifdef __BIG_ENDIAN
257 TX4927_PCIC_G2PIOGBASE_ECHG
1da177e4 258#else
89d63fe1 259 TX4927_PCIC_G2PIOGBASE_BSDIS
1da177e4 260#endif
89d63fe1
AN		 261 , &pcicptr->g2piogbase);
262 ____raw_writeq(channel->io_resource->start - channel->io_offset,
263 &pcicptr->g2piopbase);
264 for (i = 0; i < 3; i++) {
265 __raw_writel(0, &pcicptr->g2pmmask[i]);
266 ____raw_writeq(0, &pcicptr->g2pmgbase[i]);
267 ____raw_writeq(0, &pcicptr->g2pmpbase[i]);
268 }
269 if (channel->mem_resource->end) {
270 __raw_writel((channel->mem_resource->end
271 - channel->mem_resource->start) >> 4,
272 &pcicptr->g2pmmask[0]);
273 ____raw_writeq(channel->mem_resource->start |
274#ifdef __BIG_ENDIAN
275 TX4927_PCIC_G2PMnGBASE_ECHG
1da177e4 276#else
89d63fe1 277 TX4927_PCIC_G2PMnGBASE_BSDIS
1da177e4 278#endif
89d63fe1
AN		 279 , &pcicptr->g2pmgbase[0]);
280 ____raw_writeq(channel->mem_resource->start -
281 channel->mem_offset,
282 &pcicptr->g2pmpbase[0]);
283 }
284 /* PCI->GB mappings (I/O 256B) */
285 __raw_writel(0, &pcicptr->p2giopbase); /* 256B */
286 ____raw_writeq(0, &pcicptr->p2giogbase);
287 /* PCI->GB mappings (MEM 512MB (64MB on R1.x)) */
288 __raw_writel(0, &pcicptr->p2gm0plbase);
289 __raw_writel(0, &pcicptr->p2gm0pubase);
290 ____raw_writeq(TX4927_PCIC_P2GMnGBASE_TMEMEN |
291#ifdef __BIG_ENDIAN
292 TX4927_PCIC_P2GMnGBASE_TECHG
293#else
294 TX4927_PCIC_P2GMnGBASE_TBSDIS
295#endif
296 , &pcicptr->p2gmgbase[0]);
297 /* PCI->GB mappings (MEM 16MB) */
298 __raw_writel(0xffffffff, &pcicptr->p2gm1plbase);
299 __raw_writel(0xffffffff, &pcicptr->p2gm1pubase);
300 ____raw_writeq(0, &pcicptr->p2gmgbase[1]);
301 /* PCI->GB mappings (MEM 1MB) */
302 __raw_writel(0xffffffff, &pcicptr->p2gm2pbase); /* 1MB */
303 ____raw_writeq(0, &pcicptr->p2gmgbase[2]);
304
305 /* Clear all (including IRBER) except for GBWC */
306 __raw_writel((tx4927_pci_opts.gbwc << 16)
307 & TX4927_PCIC_PCICCFG_GBWC_MASK,
308 &pcicptr->pciccfg);
309 /* Enable Initiator Memory Space */
310 if (channel->mem_resource->end)
311 __raw_writel(__raw_readl(&pcicptr->pciccfg)
312 | TX4927_PCIC_PCICCFG_G2PMEN(0),
313 &pcicptr->pciccfg);
314 /* Enable Initiator I/O Space */
315 if (channel->io_resource->end)
316 __raw_writel(__raw_readl(&pcicptr->pciccfg)
317 | TX4927_PCIC_PCICCFG_G2PIOEN,
318 &pcicptr->pciccfg);
319 /* Enable Initiator Config */
320 __raw_writel(__raw_readl(&pcicptr->pciccfg)
321 | TX4927_PCIC_PCICCFG_ICAEN | TX4927_PCIC_PCICCFG_TCAR,
322 &pcicptr->pciccfg);
323
324 /* Do not use MEMMUL, MEMINF: YMFPCI card causes M_ABORT. */
325 __raw_writel(0, &pcicptr->pcicfg1);
326
327 __raw_writel((__raw_readl(&pcicptr->g2ptocnt) & ~0xffff)
328 | (tx4927_pci_opts.trdyto & 0xff)
329 | ((tx4927_pci_opts.retryto & 0xff) << 8),
330 &pcicptr->g2ptocnt);
331
332 /* Clear All Local Bus Status */
333 __raw_writel(TX4927_PCIC_PCICSTATUS_ALL, &pcicptr->pcicstatus);
334 /* Enable All Local Bus Interrupts */
335 __raw_writel(TX4927_PCIC_PCICSTATUS_ALL, &pcicptr->pcicmask);
336 /* Clear All Initiator Status */
337 __raw_writel(TX4927_PCIC_G2PSTATUS_ALL, &pcicptr->g2pstatus);
338 /* Enable All Initiator Interrupts */
339 __raw_writel(TX4927_PCIC_G2PSTATUS_ALL, &pcicptr->g2pmask);
340 /* Clear All PCI Status Error */
341 __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff)
342 | (TX4927_PCIC_PCISTATUS_ALL << 16),
343 &pcicptr->pcistatus);
344 /* Enable All PCI Status Error Interrupts */
345 __raw_writel(TX4927_PCIC_PCISTATUS_ALL, &pcicptr->pcimask);
346
347 if (!extarb) {
348 /* Reset Bus Arbiter */
349 __raw_writel(TX4927_PCIC_PBACFG_RPBA, &pcicptr->pbacfg);
350 __raw_writel(0, &pcicptr->pbabm);
351 /* Enable Bus Arbiter */
352 __raw_writel(TX4927_PCIC_PBACFG_PBAEN, &pcicptr->pbacfg);
1da177e4
LT		 353 }
354
89d63fe1
AN		 355 __raw_writel(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY
356 | PCI_COMMAND_PARITY | PCI_COMMAND_SERR,
357 &pcicptr->pcistatus);
358 local_irq_restore(flags);
359
360 printk(KERN_DEBUG
361 "PCI: COMMAND=%04x,PCIMASK=%04x,"
362 "TRDYTO=%02x,RETRYTO=%02x,GBWC=%03x\n",
363 __raw_readl(&pcicptr->pcistatus) & 0xffff,
364 __raw_readl(&pcicptr->pcimask) & 0xffff,
365 __raw_readl(&pcicptr->g2ptocnt) & 0xff,
366 (__raw_readl(&pcicptr->g2ptocnt) & 0xff00) >> 8,
367 (__raw_readl(&pcicptr->pciccfg) >> 16) & 0xfff);
1da177e4
LT		 368}
369
89d63fe1
AN		 370static void tx4927_report_pcic_status1(struct tx4927_pcic_reg __iomem *pcicptr)
371{
372 __u16 pcistatus = (__u16)(__raw_readl(&pcicptr->pcistatus) >> 16);
373 __u32 g2pstatus = __raw_readl(&pcicptr->g2pstatus);
374 __u32 pcicstatus = __raw_readl(&pcicptr->pcicstatus);
375 static struct {
376 __u32 flag;
377 const char *str;
378 } pcistat_tbl[] = {
379 { PCI_STATUS_DETECTED_PARITY, "DetectedParityError" },
380 { PCI_STATUS_SIG_SYSTEM_ERROR, "SignaledSystemError" },
381 { PCI_STATUS_REC_MASTER_ABORT, "ReceivedMasterAbort" },
382 { PCI_STATUS_REC_TARGET_ABORT, "ReceivedTargetAbort" },
383 { PCI_STATUS_SIG_TARGET_ABORT, "SignaledTargetAbort" },
384 { PCI_STATUS_PARITY, "MasterParityError" },
385 }, g2pstat_tbl[] = {
386 { TX4927_PCIC_G2PSTATUS_TTOE, "TIOE" },
387 { TX4927_PCIC_G2PSTATUS_RTOE, "RTOE" },
388 }, pcicstat_tbl[] = {
389 { TX4927_PCIC_PCICSTATUS_PME, "PME" },
390 { TX4927_PCIC_PCICSTATUS_TLB, "TLB" },
391 { TX4927_PCIC_PCICSTATUS_NIB, "NIB" },
392 { TX4927_PCIC_PCICSTATUS_ZIB, "ZIB" },
393 { TX4927_PCIC_PCICSTATUS_PERR, "PERR" },
394 { TX4927_PCIC_PCICSTATUS_SERR, "SERR" },
395 { TX4927_PCIC_PCICSTATUS_GBE, "GBE" },
396 { TX4927_PCIC_PCICSTATUS_IWB, "IWB" },
397 };
398 int i, cont;
1da177e4 399
89d63fe1
AN		 400 printk(KERN_ERR "");
401 if (pcistatus & TX4927_PCIC_PCISTATUS_ALL) {
402 printk(KERN_CONT "pcistat:%04x(", pcistatus);
403 for (i = 0, cont = 0; i < ARRAY_SIZE(pcistat_tbl); i++)
404 if (pcistatus & pcistat_tbl[i].flag)
405 printk(KERN_CONT "%s%s",
406 cont++ ? " " : "", pcistat_tbl[i].str);
407 printk(KERN_CONT ") ");
408 }
409 if (g2pstatus & TX4927_PCIC_G2PSTATUS_ALL) {
410 printk(KERN_CONT "g2pstatus:%08x(", g2pstatus);
411 for (i = 0, cont = 0; i < ARRAY_SIZE(g2pstat_tbl); i++)
412 if (g2pstatus & g2pstat_tbl[i].flag)
413 printk(KERN_CONT "%s%s",
414 cont++ ? " " : "", g2pstat_tbl[i].str);
415 printk(KERN_CONT ") ");
416 }
417 if (pcicstatus & TX4927_PCIC_PCICSTATUS_ALL) {
418 printk(KERN_CONT "pcicstatus:%08x(", pcicstatus);
419 for (i = 0, cont = 0; i < ARRAY_SIZE(pcicstat_tbl); i++)
420 if (pcicstatus & pcicstat_tbl[i].flag)
421 printk(KERN_CONT "%s%s",
422 cont++ ? " " : "", pcicstat_tbl[i].str);
423 printk(KERN_CONT ")");
424 }
425 printk(KERN_CONT "\n");
426}
427
428void tx4927_report_pcic_status(void)
429{
430 int i;
431
432 for (i = 0; i < ARRAY_SIZE(pcicptrs); i++) {
433 if (pcicptrs[i].pcicptr)
434 tx4927_report_pcic_status1(pcicptrs[i].pcicptr);
435 }
436}
32d00d0f 437
455cc256
AN		 438static void tx4927_dump_pcic_settings1(struct tx4927_pcic_reg __iomem *pcicptr)
439{
440 int i;
441 __u32 __iomem *preg = (__u32 __iomem *)pcicptr;
442
443 printk(KERN_INFO "tx4927 pcic (0x%p) settings:", pcicptr);
444 for (i = 0; i < sizeof(struct tx4927_pcic_reg); i += 4, preg++) {
445 if (i % 32 == 0) {
446 printk(KERN_CONT "\n");
447 printk(KERN_INFO "%04x:", i);
448 }
449 /* skip registers with side-effects */
450 if (i == offsetof(struct tx4927_pcic_reg, g2pintack)
451 || i == offsetof(struct tx4927_pcic_reg, g2pspc)
452 || i == offsetof(struct tx4927_pcic_reg, g2pcfgadrs)
453 || i == offsetof(struct tx4927_pcic_reg, g2pcfgdata)) {
454 printk(KERN_CONT " XXXXXXXX");
455 continue;
456 }
457 printk(KERN_CONT " %08x", __raw_readl(preg));
458 }
459 printk(KERN_CONT "\n");
460}
461
462void tx4927_dump_pcic_settings(void)
463{
464 int i;
465
466 for (i = 0; i < ARRAY_SIZE(pcicptrs); i++) {
467 if (pcicptrs[i].pcicptr)
468 tx4927_dump_pcic_settings1(pcicptrs[i].pcicptr);
469 }
470}
471
472irqreturn_t tx4927_pcierr_interrupt(int irq, void *dev_id)
473{
474 struct pt_regs *regs = get_irq_regs();
475 struct tx4927_pcic_reg __iomem *pcicptr =
476 (struct tx4927_pcic_reg __iomem *)(unsigned long)dev_id;
477
478 if (txx9_pci_err_action != TXX9_PCI_ERR_IGNORE) {
479 printk(KERN_WARNING "PCIERR interrupt at 0x%0*lx\n",
480 (int)(2 * sizeof(unsigned long)), regs->cp0_epc);
481 tx4927_report_pcic_status1(pcicptr);
482 }
483 if (txx9_pci_err_action != TXX9_PCI_ERR_PANIC) {
484 /* clear all pci errors */
485 __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff)
486 | (TX4927_PCIC_PCISTATUS_ALL << 16),
487 &pcicptr->pcistatus);
488 __raw_writel(TX4927_PCIC_G2PSTATUS_ALL, &pcicptr->g2pstatus);
489 __raw_writel(TX4927_PCIC_PBASTATUS_ALL, &pcicptr->pbastatus);
490 __raw_writel(TX4927_PCIC_PCICSTATUS_ALL, &pcicptr->pcicstatus);
491 return IRQ_HANDLED;
492 }
493 console_verbose();
494 tx4927_dump_pcic_settings1(pcicptr);
495 panic("PCI error.");
496}
497
32d00d0f 498#ifdef CONFIG_TOSHIBA_FPCIB0
28eb0e46 499static void tx4927_quirk_slc90e66_bridge(struct pci_dev *dev)
32d00d0f
AN		 500{
501 struct tx4927_pcic_reg __iomem *pcicptr = pci_bus_to_pcicptr(dev->bus);
502
503 if (!pcicptr)
504 return;
505 if (__raw_readl(&pcicptr->pbacfg) & TX4927_PCIC_PBACFG_PBAEN) {
506 /* Reset Bus Arbiter */
507 __raw_writel(TX4927_PCIC_PBACFG_RPBA, &pcicptr->pbacfg);
508 /*
509 * swap reqBP and reqXP (raise priority of SLC90E66).
510 * SLC90E66(PCI-ISA bridge) is connected to REQ2 on
511 * PCI Backplane board.
512 */
513 __raw_writel(0x72543610, &pcicptr->pbareqport);
514 __raw_writel(0, &pcicptr->pbabm);
515 /* Use Fixed ParkMaster (required by SLC90E66) */
516 __raw_writel(TX4927_PCIC_PBACFG_FIXPA, &pcicptr->pbacfg);
517 /* Enable Bus Arbiter */
518 __raw_writel(TX4927_PCIC_PBACFG_FIXPA |
519 TX4927_PCIC_PBACFG_PBAEN,
520 &pcicptr->pbacfg);
521 printk(KERN_INFO "PCI: Use Fixed Park Master (REQPORT %08x)\n",
522 __raw_readl(&pcicptr->pbareqport));
523 }
524}
525#define PCI_DEVICE_ID_EFAR_SLC90E66_0 0x9460
526DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_0,
527 tx4927_quirk_slc90e66_bridge);
528#endif
Linux kernel - Deliverables
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