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e7300d04 MB |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr> | |
7 | */ | |
8 | ||
9 | #include <linux/types.h> | |
10 | #include <linux/pci.h> | |
11 | #include <linux/kernel.h> | |
12 | #include <linux/init.h> | |
19c860d9 | 13 | #include <linux/delay.h> |
f2d1035e | 14 | #include <linux/clk.h> |
e7300d04 MB |
15 | #include <asm/bootinfo.h> |
16 | ||
ba00e2e5 JG |
17 | #include <bcm63xx_reset.h> |
18 | ||
e7300d04 MB |
19 | #include "pci-bcm63xx.h" |
20 | ||
21 | /* | |
22 | * Allow PCI to be disabled at runtime depending on board nvram | |
23 | * configuration | |
24 | */ | |
25 | int bcm63xx_pci_enabled; | |
26 | ||
27 | static struct resource bcm_pci_mem_resource = { | |
28 | .name = "bcm63xx PCI memory space", | |
29 | .start = BCM_PCI_MEM_BASE_PA, | |
30 | .end = BCM_PCI_MEM_END_PA, | |
31 | .flags = IORESOURCE_MEM | |
32 | }; | |
33 | ||
34 | static struct resource bcm_pci_io_resource = { | |
35 | .name = "bcm63xx PCI IO space", | |
36 | .start = BCM_PCI_IO_BASE_PA, | |
37 | #ifdef CONFIG_CARDBUS | |
38 | .end = BCM_PCI_IO_HALF_PA, | |
39 | #else | |
40 | .end = BCM_PCI_IO_END_PA, | |
41 | #endif | |
42 | .flags = IORESOURCE_IO | |
43 | }; | |
44 | ||
45 | struct pci_controller bcm63xx_controller = { | |
46 | .pci_ops = &bcm63xx_pci_ops, | |
47 | .io_resource = &bcm_pci_io_resource, | |
48 | .mem_resource = &bcm_pci_mem_resource, | |
49 | }; | |
50 | ||
51 | /* | |
52 | * We handle cardbus via a fake Cardbus bridge, memory and io spaces | |
53 | * have to be clearly separated from PCI one since we have different | |
54 | * memory decoder. | |
55 | */ | |
56 | #ifdef CONFIG_CARDBUS | |
57 | static struct resource bcm_cb_mem_resource = { | |
58 | .name = "bcm63xx Cardbus memory space", | |
59 | .start = BCM_CB_MEM_BASE_PA, | |
60 | .end = BCM_CB_MEM_END_PA, | |
61 | .flags = IORESOURCE_MEM | |
62 | }; | |
63 | ||
64 | static struct resource bcm_cb_io_resource = { | |
65 | .name = "bcm63xx Cardbus IO space", | |
66 | .start = BCM_PCI_IO_HALF_PA + 1, | |
67 | .end = BCM_PCI_IO_END_PA, | |
68 | .flags = IORESOURCE_IO | |
69 | }; | |
70 | ||
71 | struct pci_controller bcm63xx_cb_controller = { | |
72 | .pci_ops = &bcm63xx_cb_ops, | |
73 | .io_resource = &bcm_cb_io_resource, | |
74 | .mem_resource = &bcm_cb_mem_resource, | |
75 | }; | |
76 | #endif | |
77 | ||
19c860d9 JG |
78 | static struct resource bcm_pcie_mem_resource = { |
79 | .name = "bcm63xx PCIe memory space", | |
80 | .start = BCM_PCIE_MEM_BASE_PA, | |
81 | .end = BCM_PCIE_MEM_END_PA, | |
82 | .flags = IORESOURCE_MEM, | |
83 | }; | |
84 | ||
85 | static struct resource bcm_pcie_io_resource = { | |
86 | .name = "bcm63xx PCIe IO space", | |
87 | .start = 0, | |
88 | .end = 0, | |
89 | .flags = 0, | |
90 | }; | |
91 | ||
92 | struct pci_controller bcm63xx_pcie_controller = { | |
93 | .pci_ops = &bcm63xx_pcie_ops, | |
94 | .io_resource = &bcm_pcie_io_resource, | |
95 | .mem_resource = &bcm_pcie_mem_resource, | |
96 | }; | |
97 | ||
e7300d04 MB |
98 | static u32 bcm63xx_int_cfg_readl(u32 reg) |
99 | { | |
100 | u32 tmp; | |
101 | ||
102 | tmp = reg & MPI_PCICFGCTL_CFGADDR_MASK; | |
103 | tmp |= MPI_PCICFGCTL_WRITEEN_MASK; | |
104 | bcm_mpi_writel(tmp, MPI_PCICFGCTL_REG); | |
105 | iob(); | |
106 | return bcm_mpi_readl(MPI_PCICFGDATA_REG); | |
107 | } | |
108 | ||
109 | static void bcm63xx_int_cfg_writel(u32 val, u32 reg) | |
110 | { | |
111 | u32 tmp; | |
112 | ||
113 | tmp = reg & MPI_PCICFGCTL_CFGADDR_MASK; | |
114 | tmp |= MPI_PCICFGCTL_WRITEEN_MASK; | |
115 | bcm_mpi_writel(tmp, MPI_PCICFGCTL_REG); | |
116 | bcm_mpi_writel(val, MPI_PCICFGDATA_REG); | |
117 | } | |
118 | ||
119 | void __iomem *pci_iospace_start; | |
120 | ||
19c860d9 JG |
121 | static void __init bcm63xx_reset_pcie(void) |
122 | { | |
123 | u32 val; | |
124 | ||
19c860d9 JG |
125 | /* enable SERDES */ |
126 | val = bcm_misc_readl(MISC_SERDES_CTRL_REG); | |
127 | val |= SERDES_PCIE_EN | SERDES_PCIE_EXD_EN; | |
128 | bcm_misc_writel(val, MISC_SERDES_CTRL_REG); | |
129 | ||
130 | /* reset the PCIe core */ | |
ba00e2e5 JG |
131 | bcm63xx_core_set_reset(BCM63XX_RESET_PCIE, 1); |
132 | bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_EXT, 1); | |
19c860d9 JG |
133 | mdelay(10); |
134 | ||
ba00e2e5 | 135 | bcm63xx_core_set_reset(BCM63XX_RESET_PCIE, 0); |
19c860d9 JG |
136 | mdelay(10); |
137 | ||
ba00e2e5 | 138 | bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_EXT, 0); |
19c860d9 JG |
139 | mdelay(200); |
140 | } | |
141 | ||
f2d1035e JG |
142 | static struct clk *pcie_clk; |
143 | ||
19c860d9 JG |
144 | static int __init bcm63xx_register_pcie(void) |
145 | { | |
146 | u32 val; | |
147 | ||
f2d1035e JG |
148 | /* enable clock */ |
149 | pcie_clk = clk_get(NULL, "pcie"); | |
150 | if (IS_ERR_OR_NULL(pcie_clk)) | |
151 | return -ENODEV; | |
152 | ||
153 | clk_prepare_enable(pcie_clk); | |
154 | ||
19c860d9 JG |
155 | bcm63xx_reset_pcie(); |
156 | ||
157 | /* configure the PCIe bridge */ | |
158 | val = bcm_pcie_readl(PCIE_BRIDGE_OPT1_REG); | |
159 | val |= OPT1_RD_BE_OPT_EN; | |
160 | val |= OPT1_RD_REPLY_BE_FIX_EN; | |
161 | val |= OPT1_PCIE_BRIDGE_HOLE_DET_EN; | |
162 | val |= OPT1_L1_INT_STATUS_MASK_POL; | |
163 | bcm_pcie_writel(val, PCIE_BRIDGE_OPT1_REG); | |
164 | ||
165 | /* setup the interrupts */ | |
166 | val = bcm_pcie_readl(PCIE_BRIDGE_RC_INT_MASK_REG); | |
167 | val |= PCIE_RC_INT_A | PCIE_RC_INT_B | PCIE_RC_INT_C | PCIE_RC_INT_D; | |
168 | bcm_pcie_writel(val, PCIE_BRIDGE_RC_INT_MASK_REG); | |
169 | ||
170 | val = bcm_pcie_readl(PCIE_BRIDGE_OPT2_REG); | |
171 | /* enable credit checking and error checking */ | |
172 | val |= OPT2_TX_CREDIT_CHK_EN; | |
173 | val |= OPT2_UBUS_UR_DECODE_DIS; | |
174 | ||
175 | /* set device bus/func for the pcie device */ | |
176 | val |= (PCIE_BUS_DEVICE << OPT2_CFG_TYPE1_BUS_NO_SHIFT); | |
177 | val |= OPT2_CFG_TYPE1_BD_SEL; | |
178 | bcm_pcie_writel(val, PCIE_BRIDGE_OPT2_REG); | |
179 | ||
180 | /* setup class code as bridge */ | |
181 | val = bcm_pcie_readl(PCIE_IDVAL3_REG); | |
182 | val &= ~IDVAL3_CLASS_CODE_MASK; | |
183 | val |= (PCI_CLASS_BRIDGE_PCI << IDVAL3_SUBCLASS_SHIFT); | |
184 | bcm_pcie_writel(val, PCIE_IDVAL3_REG); | |
185 | ||
186 | /* disable bar1 size */ | |
187 | val = bcm_pcie_readl(PCIE_CONFIG2_REG); | |
188 | val &= ~CONFIG2_BAR1_SIZE_MASK; | |
189 | bcm_pcie_writel(val, PCIE_CONFIG2_REG); | |
190 | ||
191 | /* set bar0 to little endian */ | |
192 | val = (BCM_PCIE_MEM_BASE_PA >> 20) << BASEMASK_BASE_SHIFT; | |
193 | val |= (BCM_PCIE_MEM_BASE_PA >> 20) << BASEMASK_MASK_SHIFT; | |
194 | val |= BASEMASK_REMAP_EN; | |
195 | bcm_pcie_writel(val, PCIE_BRIDGE_BAR0_BASEMASK_REG); | |
196 | ||
197 | val = (BCM_PCIE_MEM_BASE_PA >> 20) << REBASE_ADDR_BASE_SHIFT; | |
198 | bcm_pcie_writel(val, PCIE_BRIDGE_BAR0_REBASE_ADDR_REG); | |
199 | ||
200 | register_pci_controller(&bcm63xx_pcie_controller); | |
201 | ||
202 | return 0; | |
203 | } | |
204 | ||
76f42fe8 | 205 | static int __init bcm63xx_register_pci(void) |
e7300d04 MB |
206 | { |
207 | unsigned int mem_size; | |
208 | u32 val; | |
e7300d04 MB |
209 | /* |
210 | * configuration access are done through IO space, remap 4 | |
211 | * first bytes to access it from CPU. | |
212 | * | |
213 | * this means that no io access from CPU should happen while | |
214 | * we do a configuration cycle, but there's no way we can add | |
215 | * a spinlock for each io access, so this is currently kind of | |
216 | * broken on SMP. | |
217 | */ | |
218 | pci_iospace_start = ioremap_nocache(BCM_PCI_IO_BASE_PA, 4); | |
219 | if (!pci_iospace_start) | |
220 | return -ENOMEM; | |
221 | ||
222 | /* setup local bus to PCI access (PCI memory) */ | |
223 | val = BCM_PCI_MEM_BASE_PA & MPI_L2P_BASE_MASK; | |
224 | bcm_mpi_writel(val, MPI_L2PMEMBASE1_REG); | |
225 | bcm_mpi_writel(~(BCM_PCI_MEM_SIZE - 1), MPI_L2PMEMRANGE1_REG); | |
226 | bcm_mpi_writel(val | MPI_L2PREMAP_ENABLED_MASK, MPI_L2PMEMREMAP1_REG); | |
227 | ||
228 | /* set Cardbus IDSEL (type 0 cfg access on primary bus for | |
229 | * this IDSEL will be done on Cardbus instead) */ | |
230 | val = bcm_pcmcia_readl(PCMCIA_C1_REG); | |
231 | val &= ~PCMCIA_C1_CBIDSEL_MASK; | |
232 | val |= (CARDBUS_PCI_IDSEL << PCMCIA_C1_CBIDSEL_SHIFT); | |
233 | bcm_pcmcia_writel(val, PCMCIA_C1_REG); | |
234 | ||
235 | #ifdef CONFIG_CARDBUS | |
236 | /* setup local bus to PCI access (Cardbus memory) */ | |
237 | val = BCM_CB_MEM_BASE_PA & MPI_L2P_BASE_MASK; | |
238 | bcm_mpi_writel(val, MPI_L2PMEMBASE2_REG); | |
239 | bcm_mpi_writel(~(BCM_CB_MEM_SIZE - 1), MPI_L2PMEMRANGE2_REG); | |
240 | val |= MPI_L2PREMAP_ENABLED_MASK | MPI_L2PREMAP_IS_CARDBUS_MASK; | |
241 | bcm_mpi_writel(val, MPI_L2PMEMREMAP2_REG); | |
242 | #else | |
243 | /* disable second access windows */ | |
244 | bcm_mpi_writel(0, MPI_L2PMEMREMAP2_REG); | |
245 | #endif | |
246 | ||
247 | /* setup local bus to PCI access (IO memory), we have only 1 | |
248 | * IO window for both PCI and cardbus, but it cannot handle | |
249 | * both at the same time, assume standard PCI for now, if | |
250 | * cardbus card has IO zone, PCI fixup will change window to | |
251 | * cardbus */ | |
252 | val = BCM_PCI_IO_BASE_PA & MPI_L2P_BASE_MASK; | |
253 | bcm_mpi_writel(val, MPI_L2PIOBASE_REG); | |
254 | bcm_mpi_writel(~(BCM_PCI_IO_SIZE - 1), MPI_L2PIORANGE_REG); | |
255 | bcm_mpi_writel(val | MPI_L2PREMAP_ENABLED_MASK, MPI_L2PIOREMAP_REG); | |
256 | ||
257 | /* enable PCI related GPIO pins */ | |
258 | bcm_mpi_writel(MPI_LOCBUSCTL_EN_PCI_GPIO_MASK, MPI_LOCBUSCTL_REG); | |
259 | ||
260 | /* setup PCI to local bus access, used by PCI device to target | |
261 | * local RAM while bus mastering */ | |
262 | bcm63xx_int_cfg_writel(0, PCI_BASE_ADDRESS_3); | |
04712f3f | 263 | if (BCMCPU_IS_6358() || BCMCPU_IS_6368()) |
e7300d04 MB |
264 | val = MPI_SP0_REMAP_ENABLE_MASK; |
265 | else | |
266 | val = 0; | |
267 | bcm_mpi_writel(val, MPI_SP0_REMAP_REG); | |
268 | ||
269 | bcm63xx_int_cfg_writel(0x0, PCI_BASE_ADDRESS_4); | |
270 | bcm_mpi_writel(0, MPI_SP1_REMAP_REG); | |
271 | ||
272 | mem_size = bcm63xx_get_memory_size(); | |
273 | ||
274 | /* 6348 before rev b0 exposes only 16 MB of RAM memory through | |
275 | * PCI, throw a warning if we have more memory */ | |
276 | if (BCMCPU_IS_6348() && (bcm63xx_get_cpu_rev() & 0xf0) == 0xa0) { | |
277 | if (mem_size > (16 * 1024 * 1024)) | |
278 | printk(KERN_WARNING "bcm63xx: this CPU " | |
279 | "revision cannot handle more than 16MB " | |
280 | "of RAM for PCI bus mastering\n"); | |
281 | } else { | |
282 | /* setup sp0 range to local RAM size */ | |
283 | bcm_mpi_writel(~(mem_size - 1), MPI_SP0_RANGE_REG); | |
284 | bcm_mpi_writel(0, MPI_SP1_RANGE_REG); | |
285 | } | |
286 | ||
287 | /* change host bridge retry counter to infinite number of | |
288 | * retry, needed for some broadcom wifi cards with Silicon | |
289 | * Backplane bus where access to srom seems very slow */ | |
290 | val = bcm63xx_int_cfg_readl(BCMPCI_REG_TIMERS); | |
291 | val &= ~REG_TIMER_RETRY_MASK; | |
292 | bcm63xx_int_cfg_writel(val, BCMPCI_REG_TIMERS); | |
293 | ||
294 | /* enable memory decoder and bus mastering */ | |
295 | val = bcm63xx_int_cfg_readl(PCI_COMMAND); | |
296 | val |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); | |
297 | bcm63xx_int_cfg_writel(val, PCI_COMMAND); | |
298 | ||
299 | /* enable read prefetching & disable byte swapping for bus | |
300 | * mastering transfers */ | |
301 | val = bcm_mpi_readl(MPI_PCIMODESEL_REG); | |
302 | val &= ~MPI_PCIMODESEL_BAR1_NOSWAP_MASK; | |
303 | val &= ~MPI_PCIMODESEL_BAR2_NOSWAP_MASK; | |
304 | val &= ~MPI_PCIMODESEL_PREFETCH_MASK; | |
305 | val |= (8 << MPI_PCIMODESEL_PREFETCH_SHIFT); | |
306 | bcm_mpi_writel(val, MPI_PCIMODESEL_REG); | |
307 | ||
308 | /* enable pci interrupt */ | |
309 | val = bcm_mpi_readl(MPI_LOCINT_REG); | |
310 | val |= MPI_LOCINT_MASK(MPI_LOCINT_EXT_PCI_INT); | |
311 | bcm_mpi_writel(val, MPI_LOCINT_REG); | |
312 | ||
313 | register_pci_controller(&bcm63xx_controller); | |
314 | ||
315 | #ifdef CONFIG_CARDBUS | |
316 | register_pci_controller(&bcm63xx_cb_controller); | |
317 | #endif | |
318 | ||
319 | /* mark memory space used for IO mapping as reserved */ | |
320 | request_mem_region(BCM_PCI_IO_BASE_PA, BCM_PCI_IO_SIZE, | |
321 | "bcm63xx PCI IO space"); | |
322 | return 0; | |
323 | } | |
324 | ||
76f42fe8 JG |
325 | |
326 | static int __init bcm63xx_pci_init(void) | |
327 | { | |
328 | if (!bcm63xx_pci_enabled) | |
329 | return -ENODEV; | |
330 | ||
331 | switch (bcm63xx_get_cpu_id()) { | |
19c860d9 JG |
332 | case BCM6328_CPU_ID: |
333 | return bcm63xx_register_pcie(); | |
76f42fe8 JG |
334 | case BCM6348_CPU_ID: |
335 | case BCM6358_CPU_ID: | |
336 | case BCM6368_CPU_ID: | |
337 | return bcm63xx_register_pci(); | |
338 | default: | |
339 | return -ENODEV; | |
340 | } | |
341 | } | |
342 | ||
e7300d04 | 343 | arch_initcall(bcm63xx_pci_init); |