[deliverable/linux.git] / arch / mips / pci / pci-xlp.c

/*
 * Copyright (c) 2003-2012 Broadcom Corporation
 * All Rights Reserved
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the Broadcom
 * license below:
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#include <linux/types.h>
#include <linux/pci.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/msi.h>
#include <linux/mm.h>
#include <linux/irq.h>
#include <linux/irqdesc.h>
#include <linux/console.h>

#include <asm/io.h>

#include <asm/netlogic/interrupt.h>
#include <asm/netlogic/haldefs.h>
#include <asm/netlogic/common.h>
#include <asm/netlogic/mips-extns.h>

#include <asm/netlogic/xlp-hal/iomap.h>
#include <asm/netlogic/xlp-hal/xlp.h>
#include <asm/netlogic/xlp-hal/pic.h>
#include <asm/netlogic/xlp-hal/pcibus.h>
#include <asm/netlogic/xlp-hal/bridge.h>

static void *pci_config_base;

#define pci_cfg_addr(bus, devfn, off) (((bus) << 20) | ((devfn) << 12) | (off))

/* PCI ops */
static inline u32 pci_cfg_read_32bit(struct pci_bus *bus, unsigned int devfn,
	int where)
{
	u32 data;
	u32 *cfgaddr;

	where &= ~3;
	if (cpu_is_xlp9xx()) {
		/* be very careful on SoC buses */
		if (bus->number == 0) {
			/* Scan only existing nodes - uboot bug? */
			if (PCI_SLOT(devfn) != 0 ||
					   !nlm_node_present(PCI_FUNC(devfn)))
				return 0xffffffff;
		} else if (bus->parent->number == 0) {	/* SoC bus */
			if (PCI_SLOT(devfn) == 0)	/* b.0.0 hangs */
				return 0xffffffff;
			if (devfn == 44)		/* b.5.4 hangs */
				return 0xffffffff;
		}
	} else if (bus->number == 0 && PCI_SLOT(devfn) == 1 && where == 0x954) {
		return 0xffffffff;
	}
	cfgaddr = (u32 *)(pci_config_base +
			pci_cfg_addr(bus->number, devfn, where));
	data = *cfgaddr;
	return data;
}

static inline void pci_cfg_write_32bit(struct pci_bus *bus, unsigned int devfn,
	int where, u32 data)
{
	u32 *cfgaddr;

	cfgaddr = (u32 *)(pci_config_base +
			pci_cfg_addr(bus->number, devfn, where & ~3));
	*cfgaddr = data;
}

static int nlm_pcibios_read(struct pci_bus *bus, unsigned int devfn,
	int where, int size, u32 *val)
{
	u32 data;

	if ((size == 2) && (where & 1))
		return PCIBIOS_BAD_REGISTER_NUMBER;
	else if ((size == 4) && (where & 3))
		return PCIBIOS_BAD_REGISTER_NUMBER;

	data = pci_cfg_read_32bit(bus, devfn, where);

	if (size == 1)
		*val = (data >> ((where & 3) << 3)) & 0xff;
	else if (size == 2)
		*val = (data >> ((where & 3) << 3)) & 0xffff;
	else
		*val = data;

	return PCIBIOS_SUCCESSFUL;
}


static int nlm_pcibios_write(struct pci_bus *bus, unsigned int devfn,
		int where, int size, u32 val)
{
	u32 data;

	if ((size == 2) && (where & 1))
		return PCIBIOS_BAD_REGISTER_NUMBER;
	else if ((size == 4) && (where & 3))
		return PCIBIOS_BAD_REGISTER_NUMBER;

	data = pci_cfg_read_32bit(bus, devfn, where);

	if (size == 1)
		data = (data & ~(0xff << ((where & 3) << 3))) |
			(val << ((where & 3) << 3));
	else if (size == 2)
		data = (data & ~(0xffff << ((where & 3) << 3))) |
			(val << ((where & 3) << 3));
	else
		data = val;

	pci_cfg_write_32bit(bus, devfn, where, data);

	return PCIBIOS_SUCCESSFUL;
}

struct pci_ops nlm_pci_ops = {
	.read  = nlm_pcibios_read,
	.write = nlm_pcibios_write
};

static struct resource nlm_pci_mem_resource = {
	.name		= "XLP PCI MEM",
	.start		= 0xd0000000UL, /* 256MB PCI mem @ 0xd000_0000 */
	.end		= 0xdfffffffUL,
	.flags		= IORESOURCE_MEM,
};

static struct resource nlm_pci_io_resource = {
	.name		= "XLP IO MEM",
	.start		= 0x14000000UL, /* 64MB PCI IO @ 0x1000_0000 */
	.end		= 0x17ffffffUL,
	.flags		= IORESOURCE_IO,
};

struct pci_controller nlm_pci_controller = {
	.index		= 0,
	.pci_ops	= &nlm_pci_ops,
	.mem_resource	= &nlm_pci_mem_resource,
	.mem_offset	= 0x00000000UL,
	.io_resource	= &nlm_pci_io_resource,
	.io_offset	= 0x00000000UL,
};

struct pci_dev *xlp_get_pcie_link(const struct pci_dev *dev)
{
	struct pci_bus *bus, *p;

	bus = dev->bus;

	if (cpu_is_xlp9xx()) {
		/* find bus with grand parent number == 0 */
		for (p = bus->parent; p && p->parent && p->parent->number != 0;
				p = p->parent)
			bus = p;
		return (p && p->parent) ? bus->self : NULL;
	} else {
		/* Find the bridge on bus 0 */
		for (p = bus->parent; p && p->number != 0; p = p->parent)
			bus = p;

		return p ? bus->self : NULL;
	}
}

int xlp_socdev_to_node(const struct pci_dev *lnkdev)
{
	if (cpu_is_xlp9xx())
		return PCI_FUNC(lnkdev->bus->self->devfn);
	else
		return PCI_SLOT(lnkdev->devfn) / 8;
}

int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
	struct pci_dev *lnkdev;
	int lnkfunc, node;

	/*
	 * For XLP PCIe, there is an IRQ per Link, find out which
	 * link the device is on to assign interrupts
	*/
	lnkdev = xlp_get_pcie_link(dev);
	if (lnkdev == NULL)
		return 0;

	lnkfunc = PCI_FUNC(lnkdev->devfn);
	node = xlp_socdev_to_node(lnkdev);

	return nlm_irq_to_xirq(node, PIC_PCIE_LINK_LEGACY_IRQ(lnkfunc));
}

/* Do platform specific device initialization at pci_enable_device() time */
int pcibios_plat_dev_init(struct pci_dev *dev)
{
	return 0;
}

/*
 * If big-endian, enable hardware byteswap on the PCIe bridges.
 * This will make both the SoC and PCIe devices behave consistently with
 * readl/writel.
 */
#ifdef __BIG_ENDIAN
static void xlp_config_pci_bswap(int node, int link)
{
	uint64_t nbubase, lnkbase;
	u32 reg;

	nbubase = nlm_get_bridge_regbase(node);
	lnkbase = nlm_get_pcie_base(node, link);

	/*
	 *  Enable byte swap in hardware. Program each link's PCIe SWAP regions
	 * from the link's address ranges.
	 */
	if (cpu_is_xlp9xx()) {
		reg = nlm_read_bridge_reg(nbubase,
				BRIDGE_9XX_PCIEMEM_BASE0 + link);
		nlm_write_pci_reg(lnkbase, PCIE_9XX_BYTE_SWAP_MEM_BASE, reg);

		reg = nlm_read_bridge_reg(nbubase,
				BRIDGE_9XX_PCIEMEM_LIMIT0 + link);
		nlm_write_pci_reg(lnkbase,
				PCIE_9XX_BYTE_SWAP_MEM_LIM, reg | 0xfff);

		reg = nlm_read_bridge_reg(nbubase,
				BRIDGE_9XX_PCIEIO_BASE0 + link);
		nlm_write_pci_reg(lnkbase, PCIE_9XX_BYTE_SWAP_IO_BASE, reg);

		reg = nlm_read_bridge_reg(nbubase,
				BRIDGE_9XX_PCIEIO_LIMIT0 + link);
		nlm_write_pci_reg(lnkbase,
				PCIE_9XX_BYTE_SWAP_IO_LIM, reg | 0xfff);
	} else {
		reg = nlm_read_bridge_reg(nbubase, BRIDGE_PCIEMEM_BASE0 + link);
		nlm_write_pci_reg(lnkbase, PCIE_BYTE_SWAP_MEM_BASE, reg);

		reg = nlm_read_bridge_reg(nbubase,
					BRIDGE_PCIEMEM_LIMIT0 + link);
		nlm_write_pci_reg(lnkbase, PCIE_BYTE_SWAP_MEM_LIM, reg | 0xfff);

		reg = nlm_read_bridge_reg(nbubase, BRIDGE_PCIEIO_BASE0 + link);
		nlm_write_pci_reg(lnkbase, PCIE_BYTE_SWAP_IO_BASE, reg);

		reg = nlm_read_bridge_reg(nbubase, BRIDGE_PCIEIO_LIMIT0 + link);
		nlm_write_pci_reg(lnkbase, PCIE_BYTE_SWAP_IO_LIM, reg | 0xfff);
	}
}
#else
/* Swap configuration not needed in little-endian mode */
static inline void xlp_config_pci_bswap(int node, int link) {}
#endif /* __BIG_ENDIAN */

static int __init pcibios_init(void)
{
	uint64_t pciebase;
	int link, n;
	u32 reg;

	/* Firmware assigns PCI resources */
	pci_set_flags(PCI_PROBE_ONLY);
	pci_config_base = ioremap(XLP_DEFAULT_PCI_ECFG_BASE, 64 << 20);

	/* Extend IO port for memory mapped io */
	ioport_resource.start =	 0;
	ioport_resource.end   = ~0;

	for (n = 0; n < NLM_NR_NODES; n++) {
		if (!nlm_node_present(n))
			continue;

		for (link = 0; link < PCIE_NLINKS; link++) {
			pciebase = nlm_get_pcie_base(n, link);
			if (nlm_read_pci_reg(pciebase, 0) == 0xffffffff)
				continue;
			xlp_config_pci_bswap(n, link);
			xlp_init_node_msi_irqs(n, link);

			/* put in intpin and irq - u-boot does not */
			reg = nlm_read_pci_reg(pciebase, 0xf);
			reg &= ~0x1ffu;
			reg |= (1 << 8) | PIC_PCIE_LINK_LEGACY_IRQ(link);
			nlm_write_pci_reg(pciebase, 0xf, reg);
			pr_info("XLP PCIe: Link %d-%d initialized.\n", n, link);
		}
	}

	set_io_port_base(CKSEG1);
	nlm_pci_controller.io_map_base = CKSEG1;

	register_pci_controller(&nlm_pci_controller);
	pr_info("XLP PCIe Controller %pR%pR.\n", &nlm_pci_io_resource,
		&nlm_pci_mem_resource);

	return 0;
}
arch_initcall(pcibios_init);
Commit	Line	Data
9bac624b GR	1	/*
	2	* Copyright (c) 2003-2012 Broadcom Corporation
	3	* All Rights Reserved
	4	*
	5	* This software is available to you under a choice of one of two
	6	* licenses. You may choose to be licensed under the terms of the GNU
	7	* General Public License (GPL) Version 2, available from the file
	8	* COPYING in the main directory of this source tree, or the Broadcom
	9	* license below:
	10	*
	11	* Redistribution and use in source and binary forms, with or without
	12	* modification, are permitted provided that the following conditions
	13	* are met:
	14	*
	15	* 1. Redistributions of source code must retain the above copyright
	16	* notice, this list of conditions and the following disclaimer.
	17	* 2. Redistributions in binary form must reproduce the above copyright
	18	* notice, this list of conditions and the following disclaimer in
	19	* the documentation and/or other materials provided with the
	20	* distribution.
	21	*
	22	* THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
	23	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
	24	* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
	25	* ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
	27	* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
	28	* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
	29	* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
	30	* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
	31	* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
	32	* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	33	*/
	34
	35	#include <linux/types.h>
	36	#include <linux/pci.h>
	37	#include <linux/kernel.h>
	38	#include <linux/init.h>
	39	#include <linux/msi.h>
	40	#include <linux/mm.h>
	41	#include <linux/irq.h>
	42	#include <linux/irqdesc.h>
	43	#include <linux/console.h>
	44
	45	#include <asm/io.h>
	46
	47	#include <asm/netlogic/interrupt.h>
	48	#include <asm/netlogic/haldefs.h>
7b53eb4d	49	#include <asm/netlogic/common.h>
c24a8a7a	50	#include <asm/netlogic/mips-extns.h>
9bac624b GR	51
9bac624b GR	52	#include <asm/netlogic/xlp-hal/iomap.h>
9bac624b	53	#include <asm/netlogic/xlp-hal/xlp.h>
d150cef4	54	#include <asm/netlogic/xlp-hal/pic.h>
9bac624b GR	55	#include <asm/netlogic/xlp-hal/pcibus.h>
	56	#include <asm/netlogic/xlp-hal/bridge.h>
	57
	58	static void *pci_config_base;
	59
70342287	60	#define pci_cfg_addr(bus, devfn, off) (((bus) << 20) \| ((devfn) << 12) \| (off))
9bac624b GR	61
	62	/* PCI ops */
	63	static inline u32 pci_cfg_read_32bit(struct pci_bus *bus, unsigned int devfn,
	64	int where)
	65	{
	66	u32 data;
	67	u32 *cfgaddr;
	68
8cd3d64c	69	where &= ~3;
b6ba1c52 J	70	if (cpu_is_xlp9xx()) {
	71	/* be very careful on SoC buses */
	72	if (bus->number == 0) {
	73	/* Scan only existing nodes - uboot bug? */
	74	if (PCI_SLOT(devfn) != 0 \|\|
	75	!nlm_node_present(PCI_FUNC(devfn)))
	76	return 0xffffffff;
	77	} else if (bus->parent->number == 0) { /* SoC bus */
	78	if (PCI_SLOT(devfn) == 0) /* b.0.0 hangs */
	79	return 0xffffffff;
	80	if (devfn == 44) /* b.5.4 hangs */
	81	return 0xffffffff;
	82	}
	83	} else if (bus->number == 0 && PCI_SLOT(devfn) == 1 && where == 0x954) {
8cd3d64c	84	return 0xffffffff;
b6ba1c52	85	}
9bac624b	86	cfgaddr = (u32 *)(pci_config_base +
8cd3d64c	87	pci_cfg_addr(bus->number, devfn, where));
9bac624b GR	88	data = *cfgaddr;
	89	return data;
	90	}
	91
	92	static inline void pci_cfg_write_32bit(struct pci_bus *bus, unsigned int devfn,
	93	int where, u32 data)
	94	{
	95	u32 *cfgaddr;
	96
	97	cfgaddr = (u32 *)(pci_config_base +
	98	pci_cfg_addr(bus->number, devfn, where & ~3));
	99	*cfgaddr = data;
	100	}
	101
	102	static int nlm_pcibios_read(struct pci_bus *bus, unsigned int devfn,
	103	int where, int size, u32 *val)
	104	{
	105	u32 data;
	106
	107	if ((size == 2) && (where & 1))
	108	return PCIBIOS_BAD_REGISTER_NUMBER;
	109	else if ((size == 4) && (where & 3))
	110	return PCIBIOS_BAD_REGISTER_NUMBER;
	111
	112	data = pci_cfg_read_32bit(bus, devfn, where);
	113
	114	if (size == 1)
	115	*val = (data >> ((where & 3) << 3)) & 0xff;
	116	else if (size == 2)
	117	*val = (data >> ((where & 3) << 3)) & 0xffff;
	118	else
	119	*val = data;
	120
	121	return PCIBIOS_SUCCESSFUL;
	122	}
	123
	124
	125	static int nlm_pcibios_write(struct pci_bus *bus, unsigned int devfn,
	126	int where, int size, u32 val)
	127	{
	128	u32 data;
	129
	130	if ((size == 2) && (where & 1))
	131	return PCIBIOS_BAD_REGISTER_NUMBER;
	132	else if ((size == 4) && (where & 3))
	133	return PCIBIOS_BAD_REGISTER_NUMBER;
	134
	135	data = pci_cfg_read_32bit(bus, devfn, where);
	136
	137	if (size == 1)
	138	data = (data & ~(0xff << ((where & 3) << 3))) \|
	139	(val << ((where & 3) << 3));
	140	else if (size == 2)
	141	data = (data & ~(0xffff << ((where & 3) << 3))) \|
	142	(val << ((where & 3) << 3));
	143	else
	144	data = val;
	145
	146	pci_cfg_write_32bit(bus, devfn, where, data);
	147
	148	return PCIBIOS_SUCCESSFUL;
	149	}
	150
	151	struct pci_ops nlm_pci_ops = {
152	.read = nlm_pcibios_read,
153	.write = nlm_pcibios_write
154	};
155
156	static struct resource nlm_pci_mem_resource = {
70342287 RB	157	.name = "XLP PCI MEM",
	158	.start = 0xd0000000UL, /* 256MB PCI mem @ 0xd000_0000 */
	159	.end = 0xdfffffffUL,
	160	.flags = IORESOURCE_MEM,
9bac624b GR	161	};
	162
	163	static struct resource nlm_pci_io_resource = {
70342287 RB	164	.name = "XLP IO MEM",
	165	.start = 0x14000000UL, /* 64MB PCI IO @ 0x1000_0000 */
	166	.end = 0x17ffffffUL,
	167	.flags = IORESOURCE_IO,
9bac624b GR	168	};
	169
	170	struct pci_controller nlm_pci_controller = {
70342287 RB	171	.index = 0,
	172	.pci_ops = &nlm_pci_ops,
	173	.mem_resource = &nlm_pci_mem_resource,
	174	.mem_offset = 0x00000000UL,
	175	.io_resource = &nlm_pci_io_resource,
	176	.io_offset = 0x00000000UL,
9bac624b GR	177	};
9bac624b GR	178
c24a8a7a	179	struct pci_dev xlp_get_pcie_link(const struct pci_dev dev)
9bac624b	180	{
7b53eb4d	181	struct pci_bus bus, p;
9bac624b	182
7b53eb4d	183	bus = dev->bus;
7b53eb4d	184
b6ba1c52 J	185	if (cpu_is_xlp9xx()) {
	186	/* find bus with grand parent number == 0 */
	187	for (p = bus->parent; p && p->parent && p->parent->number != 0;
	188	p = p->parent)
	189	bus = p;
	190	return (p && p->parent) ? bus->self : NULL;
	191	} else {
	192	/* Find the bridge on bus 0 */
	193	for (p = bus->parent; p && p->number != 0; p = p->parent)
	194	bus = p;
	195
	196	return p ? bus->self : NULL;
	197	}
	198	}
	199
	200	int xlp_socdev_to_node(const struct pci_dev *lnkdev)
	201	{
	202	if (cpu_is_xlp9xx())
	203	return PCI_FUNC(lnkdev->bus->self->devfn);
	204	else
	205	return PCI_SLOT(lnkdev->devfn) / 8;
7b53eb4d J	206	}
7b53eb4d J	207
9bac624b GR	208	int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
9bac624b GR	209	{
7b53eb4d	210	struct pci_dev *lnkdev;
b6ba1c52	211	int lnkfunc, node;
7b53eb4d J	212
	213	/*
	214	* For XLP PCIe, there is an IRQ per Link, find out which
	215	* link the device is on to assign interrupts
	216	*/
	217	lnkdev = xlp_get_pcie_link(dev);
	218	if (lnkdev == NULL)
	219	return 0;
b6ba1c52	220
7b53eb4d	221	lnkfunc = PCI_FUNC(lnkdev->devfn);
b6ba1c52 J	222	node = xlp_socdev_to_node(lnkdev);
	223
	224	return nlm_irq_to_xirq(node, PIC_PCIE_LINK_LEGACY_IRQ(lnkfunc));
9bac624b GR	225	}
	226
	227	/* Do platform specific device initialization at pci_enable_device() time */
	228	int pcibios_plat_dev_init(struct pci_dev *dev)
	229	{
	230	return 0;
	231	}
	232
a264b5e8 J	233	/*
	234	* If big-endian, enable hardware byteswap on the PCIe bridges.
	235	* This will make both the SoC and PCIe devices behave consistently with
	236	* readl/writel.
	237	*/
	238	#ifdef __BIG_ENDIAN
7b53eb4d	239	static void xlp_config_pci_bswap(int node, int link)
9bac624b	240	{
7b53eb4d	241	uint64_t nbubase, lnkbase;
9bac624b GR	242	u32 reg;
9bac624b GR	243
7b53eb4d J	244	nbubase = nlm_get_bridge_regbase(node);
	245	lnkbase = nlm_get_pcie_base(node, link);
	246
9bac624b GR	247	/*
	248	* Enable byte swap in hardware. Program each link's PCIe SWAP regions
	249	* from the link's address ranges.
	250	*/
b6ba1c52 J	251	if (cpu_is_xlp9xx()) {
	252	reg = nlm_read_bridge_reg(nbubase,
	253	BRIDGE_9XX_PCIEMEM_BASE0 + link);
	254	nlm_write_pci_reg(lnkbase, PCIE_9XX_BYTE_SWAP_MEM_BASE, reg);
	255
	256	reg = nlm_read_bridge_reg(nbubase,
	257	BRIDGE_9XX_PCIEMEM_LIMIT0 + link);
	258	nlm_write_pci_reg(lnkbase,
	259	PCIE_9XX_BYTE_SWAP_MEM_LIM, reg \| 0xfff);
	260
	261	reg = nlm_read_bridge_reg(nbubase,
	262	BRIDGE_9XX_PCIEIO_BASE0 + link);
	263	nlm_write_pci_reg(lnkbase, PCIE_9XX_BYTE_SWAP_IO_BASE, reg);
	264
	265	reg = nlm_read_bridge_reg(nbubase,
	266	BRIDGE_9XX_PCIEIO_LIMIT0 + link);
	267	nlm_write_pci_reg(lnkbase,
	268	PCIE_9XX_BYTE_SWAP_IO_LIM, reg \| 0xfff);
	269	} else {
	270	reg = nlm_read_bridge_reg(nbubase, BRIDGE_PCIEMEM_BASE0 + link);
	271	nlm_write_pci_reg(lnkbase, PCIE_BYTE_SWAP_MEM_BASE, reg);
	272
	273	reg = nlm_read_bridge_reg(nbubase,
	274	BRIDGE_PCIEMEM_LIMIT0 + link);
	275	nlm_write_pci_reg(lnkbase, PCIE_BYTE_SWAP_MEM_LIM, reg \| 0xfff);
	276
	277	reg = nlm_read_bridge_reg(nbubase, BRIDGE_PCIEIO_BASE0 + link);
	278	nlm_write_pci_reg(lnkbase, PCIE_BYTE_SWAP_IO_BASE, reg);
	279
	280	reg = nlm_read_bridge_reg(nbubase, BRIDGE_PCIEIO_LIMIT0 + link);
	281	nlm_write_pci_reg(lnkbase, PCIE_BYTE_SWAP_IO_LIM, reg \| 0xfff);
	282	}
9bac624b	283	}
a264b5e8 J	284	#else
a264b5e8 J	285	/* Swap configuration not needed in little-endian mode */
7b53eb4d	286	static inline void xlp_config_pci_bswap(int node, int link) {}
a264b5e8	287	#endif /* __BIG_ENDIAN */
9bac624b GR	288
	289	static int __init pcibios_init(void)
	290	{
7b53eb4d J	291	uint64_t pciebase;
	292	int link, n;
	293	u32 reg;
	294
9bac624b GR	295	/* Firmware assigns PCI resources */
	296	pci_set_flags(PCI_PROBE_ONLY);
	297	pci_config_base = ioremap(XLP_DEFAULT_PCI_ECFG_BASE, 64 << 20);
	298
	299	/* Extend IO port for memory mapped io */
70342287	300	ioport_resource.start = 0;
9bac624b GR	301	ioport_resource.end = ~0;
9bac624b GR	302
7b53eb4d	303	for (n = 0; n < NLM_NR_NODES; n++) {
cfec4c63 J	304	if (!nlm_node_present(n))
cfec4c63 J	305	continue;
7b53eb4d	306
c24a8a7a	307	for (link = 0; link < PCIE_NLINKS; link++) {
7b53eb4d J	308	pciebase = nlm_get_pcie_base(n, link);
	309	if (nlm_read_pci_reg(pciebase, 0) == 0xffffffff)
	310	continue;
	311	xlp_config_pci_bswap(n, link);
c24a8a7a	312	xlp_init_node_msi_irqs(n, link);
7b53eb4d J	313
	314	/* put in intpin and irq - u-boot does not */
	315	reg = nlm_read_pci_reg(pciebase, 0xf);
b6ba1c52	316	reg &= ~0x1ffu;
c24a8a7a	317	reg \|= (1 << 8) \| PIC_PCIE_LINK_LEGACY_IRQ(link);
7b53eb4d J	318	nlm_write_pci_reg(pciebase, 0xf, reg);
	319	pr_info("XLP PCIe: Link %d-%d initialized.\n", n, link);
	320	}
	321	}
	322
9bac624b GR	323	set_io_port_base(CKSEG1);
	324	nlm_pci_controller.io_map_base = CKSEG1;
	325
	326	register_pci_controller(&nlm_pci_controller);
	327	pr_info("XLP PCIe Controller %pR%pR.\n", &nlm_pci_io_resource,
	328	&nlm_pci_mem_resource);
	329
	330	return 0;
	331	}
	332	arch_initcall(pcibios_init);