[deliverable/linux.git] / arch / mips / pci / pci-xlp.c

/*
 * Copyright (c) 2003-2012 Broadcom Corporation
 * All Rights Reserved
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the Broadcom
 * license below:
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#include <linux/types.h>
#include <linux/pci.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/msi.h>
#include <linux/mm.h>
#include <linux/irq.h>
#include <linux/irqdesc.h>
#include <linux/console.h>

#include <asm/io.h>

#include <asm/netlogic/interrupt.h>
#include <asm/netlogic/haldefs.h>

#include <asm/netlogic/xlp-hal/iomap.h>
#include <asm/netlogic/xlp-hal/pic.h>
#include <asm/netlogic/xlp-hal/xlp.h>
#include <asm/netlogic/xlp-hal/pcibus.h>
#include <asm/netlogic/xlp-hal/bridge.h>

static void *pci_config_base;

#define pci_cfg_addr(bus, devfn, off) (((bus) << 20) | ((devfn) << 12) | (off))

/* PCI ops */
static inline u32 pci_cfg_read_32bit(struct pci_bus *bus, unsigned int devfn,
	int where)
{
	u32 data;
	u32 *cfgaddr;

	cfgaddr = (u32 *)(pci_config_base +
			pci_cfg_addr(bus->number, devfn, where & ~3));
	data = *cfgaddr;
	return data;
}

static inline void pci_cfg_write_32bit(struct pci_bus *bus, unsigned int devfn,
	int where, u32 data)
{
	u32 *cfgaddr;

	cfgaddr = (u32 *)(pci_config_base +
			pci_cfg_addr(bus->number, devfn, where & ~3));
	*cfgaddr = data;
}

static int nlm_pcibios_read(struct pci_bus *bus, unsigned int devfn,
	int where, int size, u32 *val)
{
	u32 data;

	if ((size == 2) && (where & 1))
		return PCIBIOS_BAD_REGISTER_NUMBER;
	else if ((size == 4) && (where & 3))
		return PCIBIOS_BAD_REGISTER_NUMBER;

	data = pci_cfg_read_32bit(bus, devfn, where);

	if (size == 1)
		*val = (data >> ((where & 3) << 3)) & 0xff;
	else if (size == 2)
		*val = (data >> ((where & 3) << 3)) & 0xffff;
	else
		*val = data;

	return PCIBIOS_SUCCESSFUL;
}


static int nlm_pcibios_write(struct pci_bus *bus, unsigned int devfn,
		int where, int size, u32 val)
{
	u32 data;

	if ((size == 2) && (where & 1))
		return PCIBIOS_BAD_REGISTER_NUMBER;
	else if ((size == 4) && (where & 3))
		return PCIBIOS_BAD_REGISTER_NUMBER;

	data = pci_cfg_read_32bit(bus, devfn, where);

	if (size == 1)
		data = (data & ~(0xff << ((where & 3) << 3))) |
			(val << ((where & 3) << 3));
	else if (size == 2)
		data = (data & ~(0xffff << ((where & 3) << 3))) |
			(val << ((where & 3) << 3));
	else
		data = val;

	pci_cfg_write_32bit(bus, devfn, where, data);

	return PCIBIOS_SUCCESSFUL;
}

struct pci_ops nlm_pci_ops = {
	.read  = nlm_pcibios_read,
	.write = nlm_pcibios_write
};

static struct resource nlm_pci_mem_resource = {
	.name		= "XLP PCI MEM",
	.start		= 0xd0000000UL, /* 256MB PCI mem @ 0xd000_0000 */
	.end		= 0xdfffffffUL,
	.flags		= IORESOURCE_MEM,
};

static struct resource nlm_pci_io_resource = {
	.name		= "XLP IO MEM",
	.start		= 0x14000000UL, /* 64MB PCI IO @ 0x1000_0000 */
	.end		= 0x17ffffffUL,
	.flags		= IORESOURCE_IO,
};

struct pci_controller nlm_pci_controller = {
	.index		= 0,
	.pci_ops	= &nlm_pci_ops,
	.mem_resource	= &nlm_pci_mem_resource,
	.mem_offset	= 0x00000000UL,
	.io_resource	= &nlm_pci_io_resource,
	.io_offset	= 0x00000000UL,
};

static int get_irq_vector(const struct pci_dev *dev)
{
	/*
	 * For XLP PCIe, there is an IRQ per Link, find out which
	 * link the device is on to assign interrupts
	*/
	if (dev->bus->self == NULL)
		return 0;

	switch	(dev->bus->self->devfn) {
	case 0x8:
		return PIC_PCIE_LINK_0_IRQ;
	case 0x9:
		return PIC_PCIE_LINK_1_IRQ;
	case 0xa:
		return PIC_PCIE_LINK_2_IRQ;
	case 0xb:
		return PIC_PCIE_LINK_3_IRQ;
	}
	WARN(1, "Unexpected devfn %d\n", dev->bus->self->devfn);
	return 0;
}

int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
	return get_irq_vector(dev);
}

/* Do platform specific device initialization at pci_enable_device() time */
int pcibios_plat_dev_init(struct pci_dev *dev)
{
	return 0;
}

static int xlp_enable_pci_bswap(void)
{
	uint64_t pciebase, sysbase;
	int node, i;
	u32 reg;

	/* Chip-0 so node set to 0 */
	node = 0;
	sysbase = nlm_get_bridge_regbase(node);
	/*
	 *  Enable byte swap in hardware. Program each link's PCIe SWAP regions
	 * from the link's address ranges.
	 */
	for (i = 0; i < 4; i++) {
		pciebase = nlm_pcicfg_base(XLP_IO_PCIE_OFFSET(node, i));
		if (nlm_read_pci_reg(pciebase, 0) == 0xffffffff)
			continue;

		reg = nlm_read_bridge_reg(sysbase, BRIDGE_PCIEMEM_BASE0 + i);
		nlm_write_pci_reg(pciebase, PCIE_BYTE_SWAP_MEM_BASE, reg);

		reg = nlm_read_bridge_reg(sysbase, BRIDGE_PCIEMEM_LIMIT0 + i);
		nlm_write_pci_reg(pciebase, PCIE_BYTE_SWAP_MEM_LIM,
			reg | 0xfff);

		reg = nlm_read_bridge_reg(sysbase, BRIDGE_PCIEIO_BASE0 + i);
		nlm_write_pci_reg(pciebase, PCIE_BYTE_SWAP_IO_BASE, reg);

		reg = nlm_read_bridge_reg(sysbase, BRIDGE_PCIEIO_LIMIT0 + i);
		nlm_write_pci_reg(pciebase, PCIE_BYTE_SWAP_IO_LIM, reg | 0xfff);
	}
	return 0;
}

static int __init pcibios_init(void)
{
	/* Firmware assigns PCI resources */
	pci_set_flags(PCI_PROBE_ONLY);
	pci_config_base = ioremap(XLP_DEFAULT_PCI_ECFG_BASE, 64 << 20);

	/* Extend IO port for memory mapped io */
	ioport_resource.start =	 0;
	ioport_resource.end   = ~0;

	xlp_enable_pci_bswap();
	set_io_port_base(CKSEG1);
	nlm_pci_controller.io_map_base = CKSEG1;

	register_pci_controller(&nlm_pci_controller);
	pr_info("XLP PCIe Controller %pR%pR.\n", &nlm_pci_io_resource,
		&nlm_pci_mem_resource);

	return 0;
}
arch_initcall(pcibios_init);
Commit	Line	Data
9bac624b GR	1	/*
	2	* Copyright (c) 2003-2012 Broadcom Corporation
	3	* All Rights Reserved
	4	*
	5	* This software is available to you under a choice of one of two
	6	* licenses. You may choose to be licensed under the terms of the GNU
	7	* General Public License (GPL) Version 2, available from the file
	8	* COPYING in the main directory of this source tree, or the Broadcom
	9	* license below:
	10	*
	11	* Redistribution and use in source and binary forms, with or without
	12	* modification, are permitted provided that the following conditions
	13	* are met:
	14	*
	15	* 1. Redistributions of source code must retain the above copyright
	16	* notice, this list of conditions and the following disclaimer.
	17	* 2. Redistributions in binary form must reproduce the above copyright
	18	* notice, this list of conditions and the following disclaimer in
	19	* the documentation and/or other materials provided with the
	20	* distribution.
	21	*
	22	* THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
	23	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
	24	* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
	25	* ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
	27	* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
	28	* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
	29	* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
	30	* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
	31	* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
	32	* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	33	*/
	34
	35	#include <linux/types.h>
	36	#include <linux/pci.h>
	37	#include <linux/kernel.h>
	38	#include <linux/init.h>
	39	#include <linux/msi.h>
	40	#include <linux/mm.h>
	41	#include <linux/irq.h>
	42	#include <linux/irqdesc.h>
	43	#include <linux/console.h>
	44
	45	#include <asm/io.h>
	46
	47	#include <asm/netlogic/interrupt.h>
	48	#include <asm/netlogic/haldefs.h>
	49
	50	#include <asm/netlogic/xlp-hal/iomap.h>
	51	#include <asm/netlogic/xlp-hal/pic.h>
	52	#include <asm/netlogic/xlp-hal/xlp.h>
	53	#include <asm/netlogic/xlp-hal/pcibus.h>
	54	#include <asm/netlogic/xlp-hal/bridge.h>
	55
	56	static void *pci_config_base;
	57
70342287	58	#define pci_cfg_addr(bus, devfn, off) (((bus) << 20) \| ((devfn) << 12) \| (off))
9bac624b GR	59
	60	/* PCI ops */
	61	static inline u32 pci_cfg_read_32bit(struct pci_bus *bus, unsigned int devfn,
	62	int where)
	63	{
	64	u32 data;
	65	u32 *cfgaddr;
	66
	67	cfgaddr = (u32 *)(pci_config_base +
	68	pci_cfg_addr(bus->number, devfn, where & ~3));
	69	data = *cfgaddr;
	70	return data;
	71	}
	72
	73	static inline void pci_cfg_write_32bit(struct pci_bus *bus, unsigned int devfn,
	74	int where, u32 data)
	75	{
	76	u32 *cfgaddr;
	77
	78	cfgaddr = (u32 *)(pci_config_base +
	79	pci_cfg_addr(bus->number, devfn, where & ~3));
	80	*cfgaddr = data;
	81	}
	82
	83	static int nlm_pcibios_read(struct pci_bus *bus, unsigned int devfn,
	84	int where, int size, u32 *val)
	85	{
	86	u32 data;
	87
	88	if ((size == 2) && (where & 1))
	89	return PCIBIOS_BAD_REGISTER_NUMBER;
	90	else if ((size == 4) && (where & 3))
	91	return PCIBIOS_BAD_REGISTER_NUMBER;
	92
	93	data = pci_cfg_read_32bit(bus, devfn, where);
	94
	95	if (size == 1)
	96	*val = (data >> ((where & 3) << 3)) & 0xff;
	97	else if (size == 2)
	98	*val = (data >> ((where & 3) << 3)) & 0xffff;
	99	else
	100	*val = data;
	101
	102	return PCIBIOS_SUCCESSFUL;
	103	}
	104
	105
	106	static int nlm_pcibios_write(struct pci_bus *bus, unsigned int devfn,
	107	int where, int size, u32 val)
	108	{
	109	u32 data;
	110
	111	if ((size == 2) && (where & 1))
	112	return PCIBIOS_BAD_REGISTER_NUMBER;
	113	else if ((size == 4) && (where & 3))
	114	return PCIBIOS_BAD_REGISTER_NUMBER;
	115
	116	data = pci_cfg_read_32bit(bus, devfn, where);
	117
	118	if (size == 1)
	119	data = (data & ~(0xff << ((where & 3) << 3))) \|
	120	(val << ((where & 3) << 3));
	121	else if (size == 2)
	122	data = (data & ~(0xffff << ((where & 3) << 3))) \|
123	(val << ((where & 3) << 3));
124	else
125	data = val;
126
127	pci_cfg_write_32bit(bus, devfn, where, data);
128
129	return PCIBIOS_SUCCESSFUL;
130	}
131
132	struct pci_ops nlm_pci_ops = {
133	.read = nlm_pcibios_read,
134	.write = nlm_pcibios_write
135	};
136
137	static struct resource nlm_pci_mem_resource = {
70342287 RB	138	.name = "XLP PCI MEM",
	139	.start = 0xd0000000UL, /* 256MB PCI mem @ 0xd000_0000 */
	140	.end = 0xdfffffffUL,
	141	.flags = IORESOURCE_MEM,
9bac624b GR	142	};
	143
	144	static struct resource nlm_pci_io_resource = {
70342287 RB	145	.name = "XLP IO MEM",
	146	.start = 0x14000000UL, /* 64MB PCI IO @ 0x1000_0000 */
	147	.end = 0x17ffffffUL,
	148	.flags = IORESOURCE_IO,
9bac624b GR	149	};
	150
	151	struct pci_controller nlm_pci_controller = {
70342287 RB	152	.index = 0,
	153	.pci_ops = &nlm_pci_ops,
	154	.mem_resource = &nlm_pci_mem_resource,
	155	.mem_offset = 0x00000000UL,
	156	.io_resource = &nlm_pci_io_resource,
	157	.io_offset = 0x00000000UL,
9bac624b GR	158	};
	159
	160	static int get_irq_vector(const struct pci_dev *dev)
	161	{
	162	/*
	163	* For XLP PCIe, there is an IRQ per Link, find out which
	164	* link the device is on to assign interrupts
	165	*/
	166	if (dev->bus->self == NULL)
	167	return 0;
	168
	169	switch (dev->bus->self->devfn) {
	170	case 0x8:
	171	return PIC_PCIE_LINK_0_IRQ;
	172	case 0x9:
	173	return PIC_PCIE_LINK_1_IRQ;
	174	case 0xa:
	175	return PIC_PCIE_LINK_2_IRQ;
	176	case 0xb:
	177	return PIC_PCIE_LINK_3_IRQ;
	178	}
	179	WARN(1, "Unexpected devfn %d\n", dev->bus->self->devfn);
	180	return 0;
	181	}
	182
	183	int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
	184	{
	185	return get_irq_vector(dev);
	186	}
	187
	188	/* Do platform specific device initialization at pci_enable_device() time */
	189	int pcibios_plat_dev_init(struct pci_dev *dev)
	190	{
	191	return 0;
	192	}
	193
	194	static int xlp_enable_pci_bswap(void)
	195	{
	196	uint64_t pciebase, sysbase;
	197	int node, i;
	198	u32 reg;
	199
	200	/* Chip-0 so node set to 0 */
	201	node = 0;
	202	sysbase = nlm_get_bridge_regbase(node);
	203	/*
	204	* Enable byte swap in hardware. Program each link's PCIe SWAP regions
	205	* from the link's address ranges.
	206	*/
	207	for (i = 0; i < 4; i++) {
	208	pciebase = nlm_pcicfg_base(XLP_IO_PCIE_OFFSET(node, i));
	209	if (nlm_read_pci_reg(pciebase, 0) == 0xffffffff)
	210	continue;
	211
	212	reg = nlm_read_bridge_reg(sysbase, BRIDGE_PCIEMEM_BASE0 + i);
	213	nlm_write_pci_reg(pciebase, PCIE_BYTE_SWAP_MEM_BASE, reg);
	214
	215	reg = nlm_read_bridge_reg(sysbase, BRIDGE_PCIEMEM_LIMIT0 + i);
	216	nlm_write_pci_reg(pciebase, PCIE_BYTE_SWAP_MEM_LIM,
	217	reg \| 0xfff);
	218
	219	reg = nlm_read_bridge_reg(sysbase, BRIDGE_PCIEIO_BASE0 + i);
	220	nlm_write_pci_reg(pciebase, PCIE_BYTE_SWAP_IO_BASE, reg);
	221
222	reg = nlm_read_bridge_reg(sysbase, BRIDGE_PCIEIO_LIMIT0 + i);
223	nlm_write_pci_reg(pciebase, PCIE_BYTE_SWAP_IO_LIM, reg \| 0xfff);
224	}
225	return 0;
226	}
227
228	static int __init pcibios_init(void)
229	{
230	/* Firmware assigns PCI resources */
231	pci_set_flags(PCI_PROBE_ONLY);
232	pci_config_base = ioremap(XLP_DEFAULT_PCI_ECFG_BASE, 64 << 20);
233
234	/* Extend IO port for memory mapped io */
70342287	235	ioport_resource.start = 0;
9bac624b GR	236	ioport_resource.end = ~0;
	237
	238	xlp_enable_pci_bswap();
	239	set_io_port_base(CKSEG1);
	240	nlm_pci_controller.io_map_base = CKSEG1;
	241
	242	register_pci_controller(&nlm_pci_controller);
	243	pr_info("XLP PCIe Controller %pR%pR.\n", &nlm_pci_io_resource,
	244	&nlm_pci_mem_resource);
	245
	246	return 0;
	247	}
	248	arch_initcall(pcibios_init);