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9b130f80 J |
1 | /* |
2 | * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights | |
3 | * reserved. | |
4 | * | |
5 | * This software is available to you under a choice of one of two | |
6 | * licenses. You may choose to be licensed under the terms of the GNU | |
7 | * General Public License (GPL) Version 2, available from the file | |
8 | * COPYING in the main directory of this source tree, or the NetLogic | |
9 | * license below: | |
10 | * | |
11 | * Redistribution and use in source and binary forms, with or without | |
12 | * modification, are permitted provided that the following conditions | |
13 | * are met: | |
14 | * | |
15 | * 1. Redistributions of source code must retain the above copyright | |
16 | * notice, this list of conditions and the following disclaimer. | |
17 | * 2. Redistributions in binary form must reproduce the above copyright | |
18 | * notice, this list of conditions and the following disclaimer in | |
19 | * the documentation and/or other materials provided with the | |
20 | * distribution. | |
21 | * | |
22 | * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR | |
23 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED | |
24 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |
25 | * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE | |
26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | |
27 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | |
28 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR | |
29 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, | |
30 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE | |
31 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN | |
32 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
33 | */ | |
34 | ||
35 | #include <linux/types.h> | |
36 | #include <linux/pci.h> | |
37 | #include <linux/kernel.h> | |
38 | #include <linux/init.h> | |
f32671a8 | 39 | #include <linux/msi.h> |
9b130f80 | 40 | #include <linux/mm.h> |
f32671a8 GR |
41 | #include <linux/irq.h> |
42 | #include <linux/irqdesc.h> | |
9b130f80 | 43 | #include <linux/console.h> |
249e2a38 | 44 | #include <linux/pci_regs.h> |
9b130f80 J |
45 | |
46 | #include <asm/io.h> | |
47 | ||
48 | #include <asm/netlogic/interrupt.h> | |
0c965407 | 49 | #include <asm/netlogic/haldefs.h> |
ea49b750 | 50 | #include <asm/netlogic/common.h> |
0c965407 | 51 | |
f32671a8 | 52 | #include <asm/netlogic/xlr/msidef.h> |
9b130f80 J |
53 | #include <asm/netlogic/xlr/iomap.h> |
54 | #include <asm/netlogic/xlr/pic.h> | |
55 | #include <asm/netlogic/xlr/xlr.h> | |
56 | ||
57 | static void *pci_config_base; | |
58 | ||
59 | #define pci_cfg_addr(bus, devfn, off) (((bus) << 16) | ((devfn) << 8) | (off)) | |
60 | ||
61 | /* PCI ops */ | |
62 | static inline u32 pci_cfg_read_32bit(struct pci_bus *bus, unsigned int devfn, | |
63 | int where) | |
64 | { | |
65 | u32 data; | |
66 | u32 *cfgaddr; | |
67 | ||
68 | cfgaddr = (u32 *)(pci_config_base + | |
69 | pci_cfg_addr(bus->number, devfn, where & ~3)); | |
70 | data = *cfgaddr; | |
71 | return cpu_to_le32(data); | |
72 | } | |
73 | ||
74 | static inline void pci_cfg_write_32bit(struct pci_bus *bus, unsigned int devfn, | |
75 | int where, u32 data) | |
76 | { | |
77 | u32 *cfgaddr; | |
78 | ||
79 | cfgaddr = (u32 *)(pci_config_base + | |
80 | pci_cfg_addr(bus->number, devfn, where & ~3)); | |
81 | *cfgaddr = cpu_to_le32(data); | |
82 | } | |
83 | ||
84 | static int nlm_pcibios_read(struct pci_bus *bus, unsigned int devfn, | |
85 | int where, int size, u32 *val) | |
86 | { | |
87 | u32 data; | |
88 | ||
89 | if ((size == 2) && (where & 1)) | |
90 | return PCIBIOS_BAD_REGISTER_NUMBER; | |
91 | else if ((size == 4) && (where & 3)) | |
92 | return PCIBIOS_BAD_REGISTER_NUMBER; | |
93 | ||
94 | data = pci_cfg_read_32bit(bus, devfn, where); | |
95 | ||
96 | if (size == 1) | |
97 | *val = (data >> ((where & 3) << 3)) & 0xff; | |
98 | else if (size == 2) | |
99 | *val = (data >> ((where & 3) << 3)) & 0xffff; | |
100 | else | |
101 | *val = data; | |
102 | ||
103 | return PCIBIOS_SUCCESSFUL; | |
104 | } | |
105 | ||
106 | ||
107 | static int nlm_pcibios_write(struct pci_bus *bus, unsigned int devfn, | |
108 | int where, int size, u32 val) | |
109 | { | |
110 | u32 data; | |
111 | ||
112 | if ((size == 2) && (where & 1)) | |
113 | return PCIBIOS_BAD_REGISTER_NUMBER; | |
114 | else if ((size == 4) && (where & 3)) | |
115 | return PCIBIOS_BAD_REGISTER_NUMBER; | |
116 | ||
117 | data = pci_cfg_read_32bit(bus, devfn, where); | |
118 | ||
119 | if (size == 1) | |
120 | data = (data & ~(0xff << ((where & 3) << 3))) | | |
121 | (val << ((where & 3) << 3)); | |
122 | else if (size == 2) | |
123 | data = (data & ~(0xffff << ((where & 3) << 3))) | | |
124 | (val << ((where & 3) << 3)); | |
125 | else | |
126 | data = val; | |
127 | ||
128 | pci_cfg_write_32bit(bus, devfn, where, data); | |
129 | ||
130 | return PCIBIOS_SUCCESSFUL; | |
131 | } | |
132 | ||
133 | struct pci_ops nlm_pci_ops = { | |
134 | .read = nlm_pcibios_read, | |
135 | .write = nlm_pcibios_write | |
136 | }; | |
137 | ||
138 | static struct resource nlm_pci_mem_resource = { | |
139 | .name = "XLR PCI MEM", | |
140 | .start = 0xd0000000UL, /* 256MB PCI mem @ 0xd000_0000 */ | |
141 | .end = 0xdfffffffUL, | |
142 | .flags = IORESOURCE_MEM, | |
143 | }; | |
144 | ||
145 | static struct resource nlm_pci_io_resource = { | |
146 | .name = "XLR IO MEM", | |
147 | .start = 0x10000000UL, /* 16MB PCI IO @ 0x1000_0000 */ | |
148 | .end = 0x100fffffUL, | |
149 | .flags = IORESOURCE_IO, | |
150 | }; | |
151 | ||
152 | struct pci_controller nlm_pci_controller = { | |
153 | .index = 0, | |
154 | .pci_ops = &nlm_pci_ops, | |
155 | .mem_resource = &nlm_pci_mem_resource, | |
156 | .mem_offset = 0x00000000UL, | |
157 | .io_resource = &nlm_pci_io_resource, | |
158 | .io_offset = 0x00000000UL, | |
159 | }; | |
160 | ||
249e2a38 GR |
161 | /* |
162 | * The top level PCIe links on the XLS PCIe controller appear as | |
163 | * bridges. Given a device, this function finds which link it is | |
164 | * on. | |
165 | */ | |
166 | static struct pci_dev *xls_get_pcie_link(const struct pci_dev *dev) | |
167 | { | |
168 | struct pci_bus *bus, *p; | |
169 | ||
170 | /* Find the bridge on bus 0 */ | |
171 | bus = dev->bus; | |
172 | for (p = bus->parent; p && p->number != 0; p = p->parent) | |
173 | bus = p; | |
174 | ||
175 | return p ? bus->self : NULL; | |
176 | } | |
177 | ||
ea49b750 | 178 | static int nlm_pci_link_to_irq(int link) |
9b130f80 | 179 | { |
ea49b750 | 180 | switch (link) { |
249e2a38 | 181 | case 0: |
9b130f80 | 182 | return PIC_PCIE_LINK0_IRQ; |
249e2a38 | 183 | case 1: |
9b130f80 | 184 | return PIC_PCIE_LINK1_IRQ; |
249e2a38 | 185 | case 2: |
9b130f80 J |
186 | if (nlm_chip_is_xls_b()) |
187 | return PIC_PCIE_XLSB0_LINK2_IRQ; | |
188 | else | |
189 | return PIC_PCIE_LINK2_IRQ; | |
249e2a38 | 190 | case 3: |
9b130f80 J |
191 | if (nlm_chip_is_xls_b()) |
192 | return PIC_PCIE_XLSB0_LINK3_IRQ; | |
193 | else | |
194 | return PIC_PCIE_LINK3_IRQ; | |
195 | } | |
ea49b750 | 196 | WARN(1, "Unexpected link %d\n", link); |
9b130f80 J |
197 | return 0; |
198 | } | |
199 | ||
ea49b750 J |
200 | static int get_irq_vector(const struct pci_dev *dev) |
201 | { | |
202 | struct pci_dev *lnk; | |
203 | int link; | |
204 | ||
205 | if (!nlm_chip_is_xls()) | |
206 | return PIC_PCIX_IRQ; /* for XLR just one IRQ */ | |
207 | ||
208 | lnk = xls_get_pcie_link(dev); | |
209 | if (lnk == NULL) | |
210 | return 0; | |
211 | ||
212 | link = PCI_SLOT(lnk->devfn); | |
213 | return nlm_pci_link_to_irq(link); | |
214 | } | |
215 | ||
f32671a8 GR |
216 | #ifdef CONFIG_PCI_MSI |
217 | void destroy_irq(unsigned int irq) | |
218 | { | |
219 | /* nothing to do yet */ | |
220 | } | |
221 | ||
222 | void arch_teardown_msi_irq(unsigned int irq) | |
223 | { | |
224 | destroy_irq(irq); | |
225 | } | |
226 | ||
227 | int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc) | |
228 | { | |
229 | struct msi_msg msg; | |
249e2a38 | 230 | struct pci_dev *lnk; |
f32671a8 | 231 | int irq, ret; |
249e2a38 GR |
232 | u16 val; |
233 | ||
234 | /* MSI not supported on XLR */ | |
235 | if (!nlm_chip_is_xls()) | |
236 | return 1; | |
237 | ||
238 | /* | |
239 | * Enable MSI on the XLS PCIe controller bridge which was disabled | |
240 | * at enumeration, the bridge MSI capability is at 0x50 | |
241 | */ | |
242 | lnk = xls_get_pcie_link(dev); | |
243 | if (lnk == NULL) | |
244 | return 1; | |
245 | ||
246 | pci_read_config_word(lnk, 0x50 + PCI_MSI_FLAGS, &val); | |
247 | if ((val & PCI_MSI_FLAGS_ENABLE) == 0) { | |
248 | val |= PCI_MSI_FLAGS_ENABLE; | |
249 | pci_write_config_word(lnk, 0x50 + PCI_MSI_FLAGS, val); | |
250 | } | |
f32671a8 GR |
251 | |
252 | irq = get_irq_vector(dev); | |
253 | if (irq <= 0) | |
254 | return 1; | |
255 | ||
256 | msg.address_hi = MSI_ADDR_BASE_HI; | |
257 | msg.address_lo = MSI_ADDR_BASE_LO | | |
258 | MSI_ADDR_DEST_MODE_PHYSICAL | | |
259 | MSI_ADDR_REDIRECTION_CPU; | |
260 | ||
261 | msg.data = MSI_DATA_TRIGGER_EDGE | | |
262 | MSI_DATA_LEVEL_ASSERT | | |
263 | MSI_DATA_DELIVERY_FIXED; | |
264 | ||
265 | ret = irq_set_msi_desc(irq, desc); | |
266 | if (ret < 0) { | |
267 | destroy_irq(irq); | |
268 | return ret; | |
269 | } | |
270 | ||
271 | write_msi_msg(irq, &msg); | |
272 | return 0; | |
273 | } | |
274 | #endif | |
275 | ||
0c965407 J |
276 | /* Extra ACK needed for XLR on chip PCI controller */ |
277 | static void xlr_pci_ack(struct irq_data *d) | |
278 | { | |
279 | uint64_t pcibase = nlm_mmio_base(NETLOGIC_IO_PCIX_OFFSET); | |
280 | ||
281 | nlm_read_reg(pcibase, (0x140 >> 2)); | |
282 | } | |
283 | ||
284 | /* Extra ACK needed for XLS on chip PCIe controller */ | |
285 | static void xls_pcie_ack(struct irq_data *d) | |
286 | { | |
287 | uint64_t pciebase_le = nlm_mmio_base(NETLOGIC_IO_PCIE_1_OFFSET); | |
288 | ||
289 | switch (d->irq) { | |
290 | case PIC_PCIE_LINK0_IRQ: | |
291 | nlm_write_reg(pciebase_le, (0x90 >> 2), 0xffffffff); | |
292 | break; | |
293 | case PIC_PCIE_LINK1_IRQ: | |
294 | nlm_write_reg(pciebase_le, (0x94 >> 2), 0xffffffff); | |
295 | break; | |
296 | case PIC_PCIE_LINK2_IRQ: | |
297 | nlm_write_reg(pciebase_le, (0x190 >> 2), 0xffffffff); | |
298 | break; | |
299 | case PIC_PCIE_LINK3_IRQ: | |
300 | nlm_write_reg(pciebase_le, (0x194 >> 2), 0xffffffff); | |
301 | break; | |
302 | } | |
303 | } | |
304 | ||
305 | /* For XLS B silicon, the 3,4 PCI interrupts are different */ | |
306 | static void xls_pcie_ack_b(struct irq_data *d) | |
307 | { | |
308 | uint64_t pciebase_le = nlm_mmio_base(NETLOGIC_IO_PCIE_1_OFFSET); | |
309 | ||
310 | switch (d->irq) { | |
311 | case PIC_PCIE_LINK0_IRQ: | |
312 | nlm_write_reg(pciebase_le, (0x90 >> 2), 0xffffffff); | |
313 | break; | |
314 | case PIC_PCIE_LINK1_IRQ: | |
315 | nlm_write_reg(pciebase_le, (0x94 >> 2), 0xffffffff); | |
316 | break; | |
317 | case PIC_PCIE_XLSB0_LINK2_IRQ: | |
318 | nlm_write_reg(pciebase_le, (0x190 >> 2), 0xffffffff); | |
319 | break; | |
320 | case PIC_PCIE_XLSB0_LINK3_IRQ: | |
321 | nlm_write_reg(pciebase_le, (0x194 >> 2), 0xffffffff); | |
322 | break; | |
323 | } | |
324 | } | |
325 | ||
f32671a8 GR |
326 | int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) |
327 | { | |
328 | return get_irq_vector(dev); | |
329 | } | |
330 | ||
9b130f80 J |
331 | /* Do platform specific device initialization at pci_enable_device() time */ |
332 | int pcibios_plat_dev_init(struct pci_dev *dev) | |
333 | { | |
334 | return 0; | |
335 | } | |
336 | ||
337 | static int __init pcibios_init(void) | |
338 | { | |
ea49b750 J |
339 | void (*extra_ack)(struct irq_data *); |
340 | int link, irq; | |
341 | ||
9b130f80 | 342 | /* PSB assigns PCI resources */ |
29090606 | 343 | pci_set_flags(PCI_PROBE_ONLY); |
9b130f80 J |
344 | pci_config_base = ioremap(DEFAULT_PCI_CONFIG_BASE, 16 << 20); |
345 | ||
346 | /* Extend IO port for memory mapped io */ | |
347 | ioport_resource.start = 0; | |
348 | ioport_resource.end = ~0; | |
349 | ||
350 | set_io_port_base(CKSEG1); | |
351 | nlm_pci_controller.io_map_base = CKSEG1; | |
352 | ||
353 | pr_info("Registering XLR/XLS PCIX/PCIE Controller.\n"); | |
354 | register_pci_controller(&nlm_pci_controller); | |
355 | ||
0c965407 J |
356 | /* |
357 | * For PCI interrupts, we need to ack the PCI controller too, overload | |
358 | * irq handler data to do this | |
359 | */ | |
ea49b750 | 360 | if (!nlm_chip_is_xls()) { |
0c965407 | 361 | /* XLR PCI controller ACK */ |
ea49b750 J |
362 | nlm_set_pic_extra_ack(0, PIC_PCIX_IRQ, xlr_pci_ack); |
363 | } else { | |
364 | if (nlm_chip_is_xls_b()) | |
365 | extra_ack = xls_pcie_ack_b; | |
366 | else | |
367 | extra_ack = xls_pcie_ack; | |
368 | for (link = 0; link < 4; link++) { | |
369 | irq = nlm_pci_link_to_irq(link); | |
370 | nlm_set_pic_extra_ack(0, irq, extra_ack); | |
371 | } | |
0c965407 | 372 | } |
9b130f80 J |
373 | return 0; |
374 | } | |
375 | ||
376 | arch_initcall(pcibios_init); |