Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
70342287 RB |
2 | * This program is free software; you can redistribute it and/or modify it |
3 | * under the terms of the GNU General Public License as published by the | |
1da177e4 LT |
4 | * Free Software Foundation; either version 2 of the License, or (at your |
5 | * option) any later version. | |
6 | * | |
c539ef7d RB |
7 | * Copyright (C) 2003, 04, 11 Ralf Baechle (ralf@linux-mips.org) |
8 | * Copyright (C) 2011 Wind River Systems, | |
9 | * written by Ralf Baechle (ralf@linux-mips.org) | |
1da177e4 | 10 | */ |
c539ef7d | 11 | #include <linux/bug.h> |
1da177e4 LT |
12 | #include <linux/kernel.h> |
13 | #include <linux/mm.h> | |
14 | #include <linux/bootmem.h> | |
cae39d13 | 15 | #include <linux/export.h> |
1da177e4 LT |
16 | #include <linux/init.h> |
17 | #include <linux/types.h> | |
18 | #include <linux/pci.h> | |
a48cf37a | 19 | #include <linux/of_address.h> |
1da177e4 | 20 | |
c539ef7d RB |
21 | #include <asm/cpu-info.h> |
22 | ||
1da177e4 | 23 | /* |
29090606 BH |
24 | * If PCI_PROBE_ONLY in pci_flags is set, we don't change any PCI resource |
25 | * assignments. | |
1da177e4 | 26 | */ |
1da177e4 | 27 | |
1da177e4 LT |
28 | /* |
29 | * The PCI controller list. | |
30 | */ | |
31 | ||
d58eaab5 | 32 | static struct pci_controller *hose_head, **hose_tail = &hose_head; |
1da177e4 | 33 | |
982f6ffe RB |
34 | unsigned long PCIBIOS_MIN_IO; |
35 | unsigned long PCIBIOS_MIN_MEM; | |
1da177e4 | 36 | |
540799e3 AJ |
37 | static int pci_initialized; |
38 | ||
1da177e4 LT |
39 | /* |
40 | * We need to avoid collisions with `mirrored' VGA ports | |
41 | * and other strange ISA hardware, so we always want the | |
42 | * addresses to be allocated in the 0x000-0x0ff region | |
43 | * modulo 0x400. | |
44 | * | |
45 | * Why? Because some silly external IO cards only decode | |
46 | * the low 10 bits of the IO address. The 0x00-0xff region | |
47 | * is reserved for motherboard devices that decode all 16 | |
48 | * bits, so it's ok to allocate at, say, 0x2800-0x28ff, | |
49 | * but we want to try to avoid allocating at 0x2900-0x2bff | |
50 | * which might have be mirrored at 0x0100-0x03ff.. | |
51 | */ | |
b26b2d49 | 52 | resource_size_t |
3b7a17fc | 53 | pcibios_align_resource(void *data, const struct resource *res, |
e31dd6e4 | 54 | resource_size_t size, resource_size_t align) |
1da177e4 LT |
55 | { |
56 | struct pci_dev *dev = data; | |
57 | struct pci_controller *hose = dev->sysdata; | |
e31dd6e4 | 58 | resource_size_t start = res->start; |
1da177e4 LT |
59 | |
60 | if (res->flags & IORESOURCE_IO) { | |
61 | /* Make sure we start at our min on all hoses */ | |
62 | if (start < PCIBIOS_MIN_IO + hose->io_resource->start) | |
63 | start = PCIBIOS_MIN_IO + hose->io_resource->start; | |
64 | ||
65 | /* | |
66 | * Put everything into 0x00-0xff region modulo 0x400 | |
67 | */ | |
68 | if (start & 0x300) | |
69 | start = (start + 0x3ff) & ~0x3ff; | |
70 | } else if (res->flags & IORESOURCE_MEM) { | |
71 | /* Make sure we start at our min on all hoses */ | |
72 | if (start < PCIBIOS_MIN_MEM + hose->mem_resource->start) | |
73 | start = PCIBIOS_MIN_MEM + hose->mem_resource->start; | |
74 | } | |
75 | ||
b26b2d49 | 76 | return start; |
1da177e4 LT |
77 | } |
78 | ||
28eb0e46 | 79 | static void pcibios_scanbus(struct pci_controller *hose) |
540799e3 AJ |
80 | { |
81 | static int next_busno; | |
82 | static int need_domain_info; | |
7c090e5b | 83 | LIST_HEAD(resources); |
540799e3 AJ |
84 | struct pci_bus *bus; |
85 | ||
29090606 | 86 | if (hose->get_busno && pci_has_flag(PCI_PROBE_ONLY)) |
540799e3 AJ |
87 | next_busno = (*hose->get_busno)(); |
88 | ||
96a6b9ad BH |
89 | pci_add_resource_offset(&resources, |
90 | hose->mem_resource, hose->mem_offset); | |
a2e50f53 JK |
91 | pci_add_resource_offset(&resources, |
92 | hose->io_resource, hose->io_offset); | |
93 | pci_add_resource_offset(&resources, | |
94 | hose->busn_resource, hose->busn_offset); | |
7c090e5b BH |
95 | bus = pci_scan_root_bus(NULL, next_busno, hose->pci_ops, hose, |
96 | &resources); | |
540799e3 AJ |
97 | hose->bus = bus; |
98 | ||
99 | need_domain_info = need_domain_info || hose->index; | |
100 | hose->need_domain_info = need_domain_info; | |
9e808eb6 BH |
101 | |
102 | if (!bus) { | |
103 | pci_free_resource_list(&resources); | |
104 | return; | |
105 | } | |
106 | ||
107 | next_busno = bus->busn_res.end + 1; | |
108 | /* Don't allow 8-bit bus number overflow inside the hose - | |
109 | reserve some space for bridges. */ | |
110 | if (next_busno > 224) { | |
111 | next_busno = 0; | |
112 | need_domain_info = 1; | |
113 | } | |
114 | ||
115 | if (!pci_has_flag(PCI_PROBE_ONLY)) { | |
116 | pci_bus_size_bridges(bus); | |
117 | pci_bus_assign_resources(bus); | |
540799e3 | 118 | } |
9e808eb6 | 119 | pci_bus_add_devices(bus); |
540799e3 AJ |
120 | } |
121 | ||
a48cf37a | 122 | #ifdef CONFIG_OF |
28eb0e46 | 123 | void pci_load_of_ranges(struct pci_controller *hose, struct device_node *node) |
a48cf37a | 124 | { |
cffe00c0 AM |
125 | struct of_pci_range range; |
126 | struct of_pci_range_parser parser; | |
a48cf37a JC |
127 | |
128 | pr_info("PCI host bridge %s ranges:\n", node->full_name); | |
a48cf37a JC |
129 | hose->of_node = node; |
130 | ||
cffe00c0 AM |
131 | if (of_pci_range_parser_init(&parser, node)) |
132 | return; | |
133 | ||
134 | for_each_of_pci_range(&parser, &range) { | |
a48cf37a | 135 | struct resource *res = NULL; |
cffe00c0 AM |
136 | |
137 | switch (range.flags & IORESOURCE_TYPE_BITS) { | |
138 | case IORESOURCE_IO: | |
a48cf37a | 139 | pr_info(" IO 0x%016llx..0x%016llx\n", |
cffe00c0 AM |
140 | range.cpu_addr, |
141 | range.cpu_addr + range.size - 1); | |
a48cf37a | 142 | hose->io_map_base = |
cffe00c0 AM |
143 | (unsigned long)ioremap(range.cpu_addr, |
144 | range.size); | |
a48cf37a | 145 | res = hose->io_resource; |
a48cf37a | 146 | break; |
cffe00c0 | 147 | case IORESOURCE_MEM: |
a48cf37a | 148 | pr_info(" MEM 0x%016llx..0x%016llx\n", |
cffe00c0 AM |
149 | range.cpu_addr, |
150 | range.cpu_addr + range.size - 1); | |
a48cf37a | 151 | res = hose->mem_resource; |
a48cf37a JC |
152 | break; |
153 | } | |
cffe00c0 AM |
154 | if (res != NULL) |
155 | of_pci_range_to_resource(&range, node, res); | |
a48cf37a JC |
156 | } |
157 | } | |
9a97cd43 GJ |
158 | |
159 | struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus) | |
160 | { | |
161 | struct pci_controller *hose = bus->sysdata; | |
162 | ||
163 | return of_node_get(hose->of_node); | |
164 | } | |
a48cf37a JC |
165 | #endif |
166 | ||
540799e3 AJ |
167 | static DEFINE_MUTEX(pci_scan_mutex); |
168 | ||
28eb0e46 | 169 | void register_pci_controller(struct pci_controller *hose) |
1da177e4 | 170 | { |
22283178 GJ |
171 | struct resource *parent; |
172 | ||
173 | parent = hose->mem_resource->parent; | |
174 | if (!parent) | |
175 | parent = &iomem_resource; | |
176 | ||
177 | if (request_resource(parent, hose->mem_resource) < 0) | |
639702bd | 178 | goto out; |
22283178 GJ |
179 | |
180 | parent = hose->io_resource->parent; | |
181 | if (!parent) | |
182 | parent = &ioport_resource; | |
183 | ||
184 | if (request_resource(parent, hose->io_resource) < 0) { | |
639702bd TB |
185 | release_resource(hose->mem_resource); |
186 | goto out; | |
187 | } | |
188 | ||
1da177e4 LT |
189 | *hose_tail = hose; |
190 | hose_tail = &hose->next; | |
140c1729 RB |
191 | |
192 | /* | |
25985edc | 193 | * Do not panic here but later - this might happen before console init. |
140c1729 RB |
194 | */ |
195 | if (!hose->io_map_base) { | |
196 | printk(KERN_WARNING | |
197 | "registering PCI controller with io_map_base unset\n"); | |
198 | } | |
540799e3 AJ |
199 | |
200 | /* | |
201 | * Scan the bus if it is register after the PCI subsystem | |
202 | * initialization. | |
203 | */ | |
204 | if (pci_initialized) { | |
205 | mutex_lock(&pci_scan_mutex); | |
206 | pcibios_scanbus(hose); | |
207 | mutex_unlock(&pci_scan_mutex); | |
208 | } | |
209 | ||
639702bd TB |
210 | return; |
211 | ||
212 | out: | |
213 | printk(KERN_WARNING | |
214 | "Skipping PCI bus scan due to resource conflict\n"); | |
1da177e4 LT |
215 | } |
216 | ||
c539ef7d RB |
217 | static void __init pcibios_set_cache_line_size(void) |
218 | { | |
219 | struct cpuinfo_mips *c = ¤t_cpu_data; | |
220 | unsigned int lsize; | |
221 | ||
222 | /* | |
223 | * Set PCI cacheline size to that of the highest level in the | |
224 | * cache hierarchy. | |
225 | */ | |
226 | lsize = c->dcache.linesz; | |
227 | lsize = c->scache.linesz ? : lsize; | |
228 | lsize = c->tcache.linesz ? : lsize; | |
229 | ||
230 | BUG_ON(!lsize); | |
231 | ||
232 | pci_dfl_cache_line_size = lsize >> 2; | |
233 | ||
234 | pr_debug("PCI: pci_cache_line_size set to %d bytes\n", lsize); | |
235 | } | |
236 | ||
1da177e4 LT |
237 | static int __init pcibios_init(void) |
238 | { | |
239 | struct pci_controller *hose; | |
1da177e4 | 240 | |
c539ef7d RB |
241 | pcibios_set_cache_line_size(); |
242 | ||
1da177e4 | 243 | /* Scan all of the recorded PCI controllers. */ |
540799e3 AJ |
244 | for (hose = hose_head; hose; hose = hose->next) |
245 | pcibios_scanbus(hose); | |
1da177e4 | 246 | |
67eed580 | 247 | pci_fixup_irqs(pci_common_swizzle, pcibios_map_irq); |
1da177e4 | 248 | |
540799e3 AJ |
249 | pci_initialized = 1; |
250 | ||
1da177e4 LT |
251 | return 0; |
252 | } | |
253 | ||
254 | subsys_initcall(pcibios_init); | |
255 | ||
256 | static int pcibios_enable_resources(struct pci_dev *dev, int mask) | |
257 | { | |
258 | u16 cmd, old_cmd; | |
259 | int idx; | |
260 | struct resource *r; | |
261 | ||
262 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
263 | old_cmd = cmd; | |
e5de3b46 | 264 | for (idx=0; idx < PCI_NUM_RESOURCES; idx++) { |
1da177e4 LT |
265 | /* Only set up the requested stuff */ |
266 | if (!(mask & (1<<idx))) | |
267 | continue; | |
268 | ||
269 | r = &dev->resource[idx]; | |
986c9485 RB |
270 | if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM))) |
271 | continue; | |
272 | if ((idx == PCI_ROM_RESOURCE) && | |
273 | (!(r->flags & IORESOURCE_ROM_ENABLE))) | |
274 | continue; | |
1da177e4 | 275 | if (!r->start && r->end) { |
40d7c1aa RB |
276 | printk(KERN_ERR "PCI: Device %s not available " |
277 | "because of resource collisions\n", | |
278 | pci_name(dev)); | |
1da177e4 LT |
279 | return -EINVAL; |
280 | } | |
281 | if (r->flags & IORESOURCE_IO) | |
282 | cmd |= PCI_COMMAND_IO; | |
283 | if (r->flags & IORESOURCE_MEM) | |
284 | cmd |= PCI_COMMAND_MEMORY; | |
285 | } | |
1da177e4 | 286 | if (cmd != old_cmd) { |
40d7c1aa RB |
287 | printk("PCI: Enabling device %s (%04x -> %04x)\n", |
288 | pci_name(dev), old_cmd, cmd); | |
1da177e4 LT |
289 | pci_write_config_word(dev, PCI_COMMAND, cmd); |
290 | } | |
291 | return 0; | |
292 | } | |
293 | ||
1da177e4 LT |
294 | unsigned int pcibios_assign_all_busses(void) |
295 | { | |
14be538c | 296 | return 1; |
1da177e4 LT |
297 | } |
298 | ||
299 | int pcibios_enable_device(struct pci_dev *dev, int mask) | |
300 | { | |
301 | int err; | |
302 | ||
303 | if ((err = pcibios_enable_resources(dev, mask)) < 0) | |
304 | return err; | |
305 | ||
306 | return pcibios_plat_dev_init(dev); | |
307 | } | |
308 | ||
28eb0e46 | 309 | void pcibios_fixup_bus(struct pci_bus *bus) |
1da177e4 | 310 | { |
237865f1 BH |
311 | struct pci_dev *dev = bus->self; |
312 | ||
313 | if (pci_has_flag(PCI_PROBE_ONLY) && dev && | |
314 | (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) { | |
315 | pci_read_bridge_bases(bus); | |
316 | } | |
1da177e4 LT |
317 | } |
318 | ||
1da177e4 LT |
319 | EXPORT_SYMBOL(PCIBIOS_MIN_IO); |
320 | EXPORT_SYMBOL(PCIBIOS_MIN_MEM); | |
1da177e4 | 321 | |
98873f53 RB |
322 | int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, |
323 | enum pci_mmap_state mmap_state, int write_combine) | |
324 | { | |
325 | unsigned long prot; | |
326 | ||
327 | /* | |
328 | * I/O space can be accessed via normal processor loads and stores on | |
329 | * this platform but for now we elect not to do this and portable | |
330 | * drivers should not do this anyway. | |
331 | */ | |
332 | if (mmap_state == pci_mmap_io) | |
333 | return -EINVAL; | |
334 | ||
335 | /* | |
336 | * Ignore write-combine; for now only return uncached mappings. | |
337 | */ | |
338 | prot = pgprot_val(vma->vm_page_prot); | |
339 | prot = (prot & ~_CACHE_MASK) | _CACHE_UNCACHED; | |
340 | vma->vm_page_prot = __pgprot(prot); | |
341 | ||
342 | return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, | |
343 | vma->vm_end - vma->vm_start, vma->vm_page_prot); | |
344 | } | |
345 | ||
938ca516 | 346 | char * (*pcibios_plat_setup)(char *str) __initdata; |
47a5c976 | 347 | |
938ca516 | 348 | char *__init pcibios_setup(char *str) |
1da177e4 | 349 | { |
47a5c976 AN |
350 | if (pcibios_plat_setup) |
351 | return pcibios_plat_setup(str); | |
1da177e4 LT |
352 | return str; |
353 | } |