[deliverable/linux.git] / arch / mips / pci / pci.c

/*
 * This program is free software; you can redistribute	it and/or modify it
 * under  the terms of	the GNU General	 Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 *
 * Copyright (C) 2003, 04, 11 Ralf Baechle (ralf@linux-mips.org)
 * Copyright (C) 2011 Wind River Systems,
 *   written by Ralf Baechle (ralf@linux-mips.org)
 */
#include <linux/bug.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/bootmem.h>
#include <linux/export.h>
#include <linux/init.h>
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/of_address.h>

#include <asm/cpu-info.h>

/*
 * If PCI_PROBE_ONLY in pci_flags is set, we don't change any PCI resource
 * assignments.
 */

/*
 * The PCI controller list.
 */

static struct pci_controller *hose_head, **hose_tail = &hose_head;

unsigned long PCIBIOS_MIN_IO;
unsigned long PCIBIOS_MIN_MEM;

static int pci_initialized;

/*
 * We need to avoid collisions with `mirrored' VGA ports
 * and other strange ISA hardware, so we always want the
 * addresses to be allocated in the 0x000-0x0ff region
 * modulo 0x400.
 *
 * Why? Because some silly external IO cards only decode
 * the low 10 bits of the IO address. The 0x00-0xff region
 * is reserved for motherboard devices that decode all 16
 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
 * but we want to try to avoid allocating at 0x2900-0x2bff
 * which might have be mirrored at 0x0100-0x03ff..
 */
resource_size_t
pcibios_align_resource(void *data, const struct resource *res,
		       resource_size_t size, resource_size_t align)
{
	struct pci_dev *dev = data;
	struct pci_controller *hose = dev->sysdata;
	resource_size_t start = res->start;

	if (res->flags & IORESOURCE_IO) {
		/* Make sure we start at our min on all hoses */
		if (start < PCIBIOS_MIN_IO + hose->io_resource->start)
			start = PCIBIOS_MIN_IO + hose->io_resource->start;

		/*
		 * Put everything into 0x00-0xff region modulo 0x400
		 */
		if (start & 0x300)
			start = (start + 0x3ff) & ~0x3ff;
	} else if (res->flags & IORESOURCE_MEM) {
		/* Make sure we start at our min on all hoses */
		if (start < PCIBIOS_MIN_MEM + hose->mem_resource->start)
			start = PCIBIOS_MIN_MEM + hose->mem_resource->start;
	}

	return start;
}

static void pcibios_scanbus(struct pci_controller *hose)
{
	static int next_busno;
	static int need_domain_info;
	LIST_HEAD(resources);
	struct pci_bus *bus;

	if (!hose->iommu)
		PCI_DMA_BUS_IS_PHYS = 1;

	if (hose->get_busno && pci_has_flag(PCI_PROBE_ONLY))
		next_busno = (*hose->get_busno)();

	pci_add_resource_offset(&resources,
				hose->mem_resource, hose->mem_offset);
	pci_add_resource_offset(&resources, hose->io_resource, hose->io_offset);
	bus = pci_scan_root_bus(NULL, next_busno, hose->pci_ops, hose,
				&resources);
	if (!bus)
		pci_free_resource_list(&resources);

	hose->bus = bus;

	need_domain_info = need_domain_info || hose->index;
	hose->need_domain_info = need_domain_info;
	if (bus) {
		next_busno = bus->busn_res.end + 1;
		/* Don't allow 8-bit bus number overflow inside the hose -
		   reserve some space for bridges. */
		if (next_busno > 224) {
			next_busno = 0;
			need_domain_info = 1;
		}

		if (!pci_has_flag(PCI_PROBE_ONLY)) {
			pci_bus_size_bridges(bus);
			pci_bus_assign_resources(bus);
			pci_enable_bridges(bus);
		}
		bus->dev.of_node = hose->of_node;
	}
}

#ifdef CONFIG_OF
void pci_load_of_ranges(struct pci_controller *hose, struct device_node *node)
{
	const __be32 *ranges;
	int rlen;
	int pna = of_n_addr_cells(node);
	int np = pna + 5;

	pr_info("PCI host bridge %s ranges:\n", node->full_name);
	ranges = of_get_property(node, "ranges", &rlen);
	if (ranges == NULL)
		return;
	hose->of_node = node;

	while ((rlen -= np * 4) >= 0) {
		u32 pci_space;
		struct resource *res = NULL;
		u64 addr, size;

		pci_space = be32_to_cpup(&ranges[0]);
		addr = of_translate_address(node, ranges + 3);
		size = of_read_number(ranges + pna + 3, 2);
		ranges += np;
		switch ((pci_space >> 24) & 0x3) {
		case 1:		/* PCI IO space */
			pr_info("  IO 0x%016llx..0x%016llx\n",
					addr, addr + size - 1);
			hose->io_map_base =
				(unsigned long)ioremap(addr, size);
			res = hose->io_resource;
			res->flags = IORESOURCE_IO;
			break;
		case 2:		/* PCI Memory space */
		case 3:		/* PCI 64 bits Memory space */
			pr_info(" MEM 0x%016llx..0x%016llx\n",
					addr, addr + size - 1);
			res = hose->mem_resource;
			res->flags = IORESOURCE_MEM;
			break;
		}
		if (res != NULL) {
			res->start = addr;
			res->name = node->full_name;
			res->end = res->start + size - 1;
			res->parent = NULL;
			res->sibling = NULL;
			res->child = NULL;
		}
	}
}
#endif

static DEFINE_MUTEX(pci_scan_mutex);

void register_pci_controller(struct pci_controller *hose)
{
	struct resource *parent;

	parent = hose->mem_resource->parent;
	if (!parent)
		parent = &iomem_resource;

	if (request_resource(parent, hose->mem_resource) < 0)
		goto out;

	parent = hose->io_resource->parent;
	if (!parent)
		parent = &ioport_resource;

	if (request_resource(parent, hose->io_resource) < 0) {
		release_resource(hose->mem_resource);
		goto out;
	}

	*hose_tail = hose;
	hose_tail = &hose->next;

	/*
	 * Do not panic here but later - this might happen before console init.
	 */
	if (!hose->io_map_base) {
		printk(KERN_WARNING
		       "registering PCI controller with io_map_base unset\n");
	}

	/*
	 * Scan the bus if it is register after the PCI subsystem
	 * initialization.
	 */
	if (pci_initialized) {
		mutex_lock(&pci_scan_mutex);
		pcibios_scanbus(hose);
		mutex_unlock(&pci_scan_mutex);
	}

	return;

out:
	printk(KERN_WARNING
	       "Skipping PCI bus scan due to resource conflict\n");
}

static void __init pcibios_set_cache_line_size(void)
{
	struct cpuinfo_mips *c = &current_cpu_data;
	unsigned int lsize;

	/*
	 * Set PCI cacheline size to that of the highest level in the
	 * cache hierarchy.
	 */
	lsize = c->dcache.linesz;
	lsize = c->scache.linesz ? : lsize;
	lsize = c->tcache.linesz ? : lsize;

	BUG_ON(!lsize);

	pci_dfl_cache_line_size = lsize >> 2;

	pr_debug("PCI: pci_cache_line_size set to %d bytes\n", lsize);
}

static int __init pcibios_init(void)
{
	struct pci_controller *hose;

	pcibios_set_cache_line_size();

	/* Scan all of the recorded PCI controllers.  */
	for (hose = hose_head; hose; hose = hose->next)
		pcibios_scanbus(hose);

	pci_fixup_irqs(pci_common_swizzle, pcibios_map_irq);

	pci_initialized = 1;

	return 0;
}

subsys_initcall(pcibios_init);

static int pcibios_enable_resources(struct pci_dev *dev, int mask)
{
	u16 cmd, old_cmd;
	int idx;
	struct resource *r;

	pci_read_config_word(dev, PCI_COMMAND, &cmd);
	old_cmd = cmd;
	for (idx=0; idx < PCI_NUM_RESOURCES; idx++) {
		/* Only set up the requested stuff */
		if (!(mask & (1<<idx)))
			continue;

		r = &dev->resource[idx];
		if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
			continue;
		if ((idx == PCI_ROM_RESOURCE) &&
				(!(r->flags & IORESOURCE_ROM_ENABLE)))
			continue;
		if (!r->start && r->end) {
			printk(KERN_ERR "PCI: Device %s not available "
			       "because of resource collisions\n",
			       pci_name(dev));
			return -EINVAL;
		}
		if (r->flags & IORESOURCE_IO)
			cmd |= PCI_COMMAND_IO;
		if (r->flags & IORESOURCE_MEM)
			cmd |= PCI_COMMAND_MEMORY;
	}
	if (cmd != old_cmd) {
		printk("PCI: Enabling device %s (%04x -> %04x)\n",
		       pci_name(dev), old_cmd, cmd);
		pci_write_config_word(dev, PCI_COMMAND, cmd);
	}
	return 0;
}

unsigned int pcibios_assign_all_busses(void)
{
	return 1;
}

int pcibios_enable_device(struct pci_dev *dev, int mask)
{
	int err;

	if ((err = pcibios_enable_resources(dev, mask)) < 0)
		return err;

	return pcibios_plat_dev_init(dev);
}

void pcibios_fixup_bus(struct pci_bus *bus)
{
	struct pci_dev *dev = bus->self;

	if (pci_has_flag(PCI_PROBE_ONLY) && dev &&
	    (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
		pci_read_bridge_bases(bus);
	}
}

EXPORT_SYMBOL(PCIBIOS_MIN_IO);
EXPORT_SYMBOL(PCIBIOS_MIN_MEM);

int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
			enum pci_mmap_state mmap_state, int write_combine)
{
	unsigned long prot;

	/*
	 * I/O space can be accessed via normal processor loads and stores on
	 * this platform but for now we elect not to do this and portable
	 * drivers should not do this anyway.
	 */
	if (mmap_state == pci_mmap_io)
		return -EINVAL;

	/*
	 * Ignore write-combine; for now only return uncached mappings.
	 */
	prot = pgprot_val(vma->vm_page_prot);
	prot = (prot & ~_CACHE_MASK) | _CACHE_UNCACHED;
	vma->vm_page_prot = __pgprot(prot);

	return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
		vma->vm_end - vma->vm_start, vma->vm_page_prot);
}

char * (*pcibios_plat_setup)(char *str) __initdata;

char *__init pcibios_setup(char *str)
{
	if (pcibios_plat_setup)
		return pcibios_plat_setup(str);
	return str;
}
Commit	Line	Data
1da177e4	1	/*
70342287 RB	2	* This program is free software; you can redistribute it and/or modify it
70342287 RB	3	* under the terms of the GNU General Public License as published by the
1da177e4 LT	4	* Free Software Foundation; either version 2 of the License, or (at your
	5	* option) any later version.
	6	*
c539ef7d RB	7	* Copyright (C) 2003, 04, 11 Ralf Baechle (ralf@linux-mips.org)
	8	* Copyright (C) 2011 Wind River Systems,
	9	* written by Ralf Baechle (ralf@linux-mips.org)
1da177e4	10	*/
c539ef7d	11	#include <linux/bug.h>
1da177e4 LT	12	#include <linux/kernel.h>
	13	#include <linux/mm.h>
	14	#include <linux/bootmem.h>
cae39d13	15	#include <linux/export.h>
1da177e4 LT	16	#include <linux/init.h>
	17	#include <linux/types.h>
	18	#include <linux/pci.h>
a48cf37a	19	#include <linux/of_address.h>
1da177e4	20
c539ef7d RB	21	#include <asm/cpu-info.h>
c539ef7d RB	22
1da177e4	23	/*
29090606 BH	24	* If PCI_PROBE_ONLY in pci_flags is set, we don't change any PCI resource
29090606 BH	25	* assignments.
1da177e4	26	*/
1da177e4	27
1da177e4 LT	28	/*
	29	* The PCI controller list.
	30	*/
	31
d58eaab5	32	static struct pci_controller hose_head, *hose_tail = &hose_head;
1da177e4	33
982f6ffe RB	34	unsigned long PCIBIOS_MIN_IO;
982f6ffe RB	35	unsigned long PCIBIOS_MIN_MEM;
1da177e4	36
540799e3 AJ	37	static int pci_initialized;
540799e3 AJ	38
1da177e4 LT	39	/*
	40	* We need to avoid collisions with `mirrored' VGA ports
	41	* and other strange ISA hardware, so we always want the
	42	* addresses to be allocated in the 0x000-0x0ff region
	43	* modulo 0x400.
	44	*
	45	* Why? Because some silly external IO cards only decode
	46	* the low 10 bits of the IO address. The 0x00-0xff region
	47	* is reserved for motherboard devices that decode all 16
	48	* bits, so it's ok to allocate at, say, 0x2800-0x28ff,
	49	* but we want to try to avoid allocating at 0x2900-0x2bff
	50	* which might have be mirrored at 0x0100-0x03ff..
	51	*/
b26b2d49	52	resource_size_t
3b7a17fc	53	pcibios_align_resource(void data, const struct resource res,
e31dd6e4	54	resource_size_t size, resource_size_t align)
1da177e4 LT	55	{
	56	struct pci_dev *dev = data;
	57	struct pci_controller *hose = dev->sysdata;
e31dd6e4	58	resource_size_t start = res->start;
1da177e4 LT	59
	60	if (res->flags & IORESOURCE_IO) {
	61	/* Make sure we start at our min on all hoses */
	62	if (start < PCIBIOS_MIN_IO + hose->io_resource->start)
	63	start = PCIBIOS_MIN_IO + hose->io_resource->start;
	64
	65	/*
	66	* Put everything into 0x00-0xff region modulo 0x400
	67	*/
	68	if (start & 0x300)
	69	start = (start + 0x3ff) & ~0x3ff;
	70	} else if (res->flags & IORESOURCE_MEM) {
	71	/* Make sure we start at our min on all hoses */
	72	if (start < PCIBIOS_MIN_MEM + hose->mem_resource->start)
	73	start = PCIBIOS_MIN_MEM + hose->mem_resource->start;
	74	}
	75
b26b2d49	76	return start;
1da177e4 LT	77	}
1da177e4 LT	78
28eb0e46	79	static void pcibios_scanbus(struct pci_controller *hose)
540799e3 AJ	80	{
	81	static int next_busno;
	82	static int need_domain_info;
7c090e5b	83	LIST_HEAD(resources);
540799e3 AJ	84	struct pci_bus *bus;
	85
	86	if (!hose->iommu)
	87	PCI_DMA_BUS_IS_PHYS = 1;
	88
29090606	89	if (hose->get_busno && pci_has_flag(PCI_PROBE_ONLY))
540799e3 AJ	90	next_busno = (*hose->get_busno)();
540799e3 AJ	91
96a6b9ad BH	92	pci_add_resource_offset(&resources,
	93	hose->mem_resource, hose->mem_offset);
	94	pci_add_resource_offset(&resources, hose->io_resource, hose->io_offset);
7c090e5b BH	95	bus = pci_scan_root_bus(NULL, next_busno, hose->pci_ops, hose,
	96	&resources);
	97	if (!bus)
	98	pci_free_resource_list(&resources);
	99
540799e3 AJ	100	hose->bus = bus;
	101
	102	need_domain_info = need_domain_info \|\| hose->index;
	103	hose->need_domain_info = need_domain_info;
	104	if (bus) {
b918c62e	105	next_busno = bus->busn_res.end + 1;
540799e3 AJ	106	/* Don't allow 8-bit bus number overflow inside the hose -
	107	reserve some space for bridges. */
	108	if (next_busno > 224) {
	109	next_busno = 0;
	110	need_domain_info = 1;
	111	}
	112
29090606	113	if (!pci_has_flag(PCI_PROBE_ONLY)) {
540799e3 AJ	114	pci_bus_size_bridges(bus);
	115	pci_bus_assign_resources(bus);
	116	pci_enable_bridges(bus);
	117	}
a48cf37a	118	bus->dev.of_node = hose->of_node;
540799e3 AJ	119	}
	120	}
	121
a48cf37a	122	#ifdef CONFIG_OF
28eb0e46	123	void pci_load_of_ranges(struct pci_controller hose, struct device_node node)
a48cf37a JC	124	{
	125	const __be32 *ranges;
	126	int rlen;
	127	int pna = of_n_addr_cells(node);
	128	int np = pna + 5;
	129
	130	pr_info("PCI host bridge %s ranges:\n", node->full_name);
	131	ranges = of_get_property(node, "ranges", &rlen);
	132	if (ranges == NULL)
	133	return;
	134	hose->of_node = node;
	135
	136	while ((rlen -= np * 4) >= 0) {
	137	u32 pci_space;
	138	struct resource *res = NULL;
	139	u64 addr, size;
	140
	141	pci_space = be32_to_cpup(&ranges[0]);
	142	addr = of_translate_address(node, ranges + 3);
	143	size = of_read_number(ranges + pna + 3, 2);
	144	ranges += np;
	145	switch ((pci_space >> 24) & 0x3) {
	146	case 1: /* PCI IO space */
	147	pr_info(" IO 0x%016llx..0x%016llx\n",
	148	addr, addr + size - 1);
	149	hose->io_map_base =
	150	(unsigned long)ioremap(addr, size);
	151	res = hose->io_resource;
	152	res->flags = IORESOURCE_IO;
	153	break;
	154	case 2: /* PCI Memory space */
	155	case 3: /* PCI 64 bits Memory space */
	156	pr_info(" MEM 0x%016llx..0x%016llx\n",
	157	addr, addr + size - 1);
	158	res = hose->mem_resource;
	159	res->flags = IORESOURCE_MEM;
	160	break;
	161	}
	162	if (res != NULL) {
	163	res->start = addr;
	164	res->name = node->full_name;
	165	res->end = res->start + size - 1;
	166	res->parent = NULL;
	167	res->sibling = NULL;
	168	res->child = NULL;
	169	}
	170	}
	171	}
	172	#endif
	173
540799e3 AJ	174	static DEFINE_MUTEX(pci_scan_mutex);
540799e3 AJ	175
28eb0e46	176	void register_pci_controller(struct pci_controller *hose)
1da177e4	177	{
22283178 GJ	178	struct resource *parent;
	179
	180	parent = hose->mem_resource->parent;
	181	if (!parent)
	182	parent = &iomem_resource;
	183
	184	if (request_resource(parent, hose->mem_resource) < 0)
639702bd	185	goto out;
22283178 GJ	186
	187	parent = hose->io_resource->parent;
	188	if (!parent)
	189	parent = &ioport_resource;
	190
	191	if (request_resource(parent, hose->io_resource) < 0) {
639702bd TB	192	release_resource(hose->mem_resource);
	193	goto out;
	194	}
	195
1da177e4 LT	196	*hose_tail = hose;
1da177e4 LT	197	hose_tail = &hose->next;
140c1729 RB	198
140c1729 RB	199	/*
25985edc	200	* Do not panic here but later - this might happen before console init.
140c1729 RB	201	*/
	202	if (!hose->io_map_base) {
	203	printk(KERN_WARNING
	204	"registering PCI controller with io_map_base unset\n");
	205	}
540799e3 AJ	206
	207	/*
	208	* Scan the bus if it is register after the PCI subsystem
	209	* initialization.
	210	*/
	211	if (pci_initialized) {
	212	mutex_lock(&pci_scan_mutex);
	213	pcibios_scanbus(hose);
	214	mutex_unlock(&pci_scan_mutex);
	215	}
	216
639702bd TB	217	return;
	218
	219	out:
	220	printk(KERN_WARNING
	221	"Skipping PCI bus scan due to resource conflict\n");
1da177e4 LT	222	}
1da177e4 LT	223
c539ef7d RB	224	static void __init pcibios_set_cache_line_size(void)
	225	{
	226	struct cpuinfo_mips *c = &current_cpu_data;
	227	unsigned int lsize;
	228
	229	/*
	230	* Set PCI cacheline size to that of the highest level in the
	231	* cache hierarchy.
	232	*/
	233	lsize = c->dcache.linesz;
	234	lsize = c->scache.linesz ? : lsize;
	235	lsize = c->tcache.linesz ? : lsize;
	236
	237	BUG_ON(!lsize);
	238
	239	pci_dfl_cache_line_size = lsize >> 2;
	240
	241	pr_debug("PCI: pci_cache_line_size set to %d bytes\n", lsize);
	242	}
	243
1da177e4 LT	244	static int __init pcibios_init(void)
	245	{
	246	struct pci_controller *hose;
1da177e4	247
c539ef7d RB	248	pcibios_set_cache_line_size();
c539ef7d RB	249
1da177e4	250	/* Scan all of the recorded PCI controllers. */
540799e3 AJ	251	for (hose = hose_head; hose; hose = hose->next)
540799e3 AJ	252	pcibios_scanbus(hose);
1da177e4	253
67eed580	254	pci_fixup_irqs(pci_common_swizzle, pcibios_map_irq);
1da177e4	255
540799e3 AJ	256	pci_initialized = 1;
540799e3 AJ	257
1da177e4 LT	258	return 0;
	259	}
	260
	261	subsys_initcall(pcibios_init);
	262
	263	static int pcibios_enable_resources(struct pci_dev *dev, int mask)
	264	{
	265	u16 cmd, old_cmd;
	266	int idx;
	267	struct resource *r;
	268
	269	pci_read_config_word(dev, PCI_COMMAND, &cmd);
	270	old_cmd = cmd;
e5de3b46	271	for (idx=0; idx < PCI_NUM_RESOURCES; idx++) {
1da177e4 LT	272	/* Only set up the requested stuff */
	273	if (!(mask & (1<<idx)))
	274	continue;
	275
	276	r = &dev->resource[idx];
986c9485 RB	277	if (!(r->flags & (IORESOURCE_IO \| IORESOURCE_MEM)))
	278	continue;
	279	if ((idx == PCI_ROM_RESOURCE) &&
	280	(!(r->flags & IORESOURCE_ROM_ENABLE)))
	281	continue;
1da177e4	282	if (!r->start && r->end) {
40d7c1aa RB	283	printk(KERN_ERR "PCI: Device %s not available "
	284	"because of resource collisions\n",
	285	pci_name(dev));
1da177e4 LT	286	return -EINVAL;
	287	}
	288	if (r->flags & IORESOURCE_IO)
	289	cmd \|= PCI_COMMAND_IO;
	290	if (r->flags & IORESOURCE_MEM)
	291	cmd \|= PCI_COMMAND_MEMORY;
	292	}
1da177e4	293	if (cmd != old_cmd) {
40d7c1aa RB	294	printk("PCI: Enabling device %s (%04x -> %04x)\n",
40d7c1aa RB	295	pci_name(dev), old_cmd, cmd);
1da177e4 LT	296	pci_write_config_word(dev, PCI_COMMAND, cmd);
	297	}
	298	return 0;
	299	}
	300
1da177e4 LT	301	unsigned int pcibios_assign_all_busses(void)
1da177e4 LT	302	{
14be538c	303	return 1;
1da177e4 LT	304	}
	305
	306	int pcibios_enable_device(struct pci_dev *dev, int mask)
	307	{
	308	int err;
	309
	310	if ((err = pcibios_enable_resources(dev, mask)) < 0)
	311	return err;
	312
	313	return pcibios_plat_dev_init(dev);
	314	}
	315
28eb0e46	316	void pcibios_fixup_bus(struct pci_bus *bus)
1da177e4	317	{
1da177e4 LT	318	struct pci_dev *dev = bus->self;
1da177e4 LT	319
29090606	320	if (pci_has_flag(PCI_PROBE_ONLY) && dev &&
7c090e5b	321	(dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
1da177e4	322	pci_read_bridge_bases(bus);
1da177e4 LT	323	}
	324	}
	325
1da177e4 LT	326	EXPORT_SYMBOL(PCIBIOS_MIN_IO);
1da177e4 LT	327	EXPORT_SYMBOL(PCIBIOS_MIN_MEM);
1da177e4	328
98873f53 RB	329	int pci_mmap_page_range(struct pci_dev dev, struct vm_area_struct vma,
	330	enum pci_mmap_state mmap_state, int write_combine)
	331	{
	332	unsigned long prot;
	333
	334	/*
	335	* I/O space can be accessed via normal processor loads and stores on
	336	* this platform but for now we elect not to do this and portable
	337	* drivers should not do this anyway.
	338	*/
	339	if (mmap_state == pci_mmap_io)
	340	return -EINVAL;
	341
	342	/*
	343	* Ignore write-combine; for now only return uncached mappings.
	344	*/
	345	prot = pgprot_val(vma->vm_page_prot);
	346	prot = (prot & ~_CACHE_MASK) \| _CACHE_UNCACHED;
	347	vma->vm_page_prot = __pgprot(prot);
	348
	349	return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
	350	vma->vm_end - vma->vm_start, vma->vm_page_prot);
	351	}
	352
938ca516	353	char * (pcibios_plat_setup)(char str) __initdata;
47a5c976	354
938ca516	355	char __init pcibios_setup(char str)
1da177e4	356	{
47a5c976 AN	357	if (pcibios_plat_setup)
47a5c976 AN	358	return pcibios_plat_setup(str);
1da177e4 LT	359	return str;
1da177e4 LT	360	}